Product Overview

Product Overview
MC100LVE210: Clock / Data Fanout Buffer, 1:4 / 1:5 Differential, Dual ECL, 3.3
V
For complete documentation, see the data sheet
Product Description
The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The
device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to
minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the
skew between the two fundamental signals from a part-to-part skew down to an output-to-output skew. This capability reduces the
skew by a factor of 4 as compared to using two LVE111's to accomplish the same task.
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are identically terminated,
even if only one side is being used. In most applications all nine differential pairs will be used and therefore terminated. In the case
where fewer than nine pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in
order to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of
10-20 ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in skew. Note that the
package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side
of the package.
The MC100LVE210, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the
LVE210 to be used for high performance clock distribution in +3.3 V systems. Designers can take advantage of the LVE210's
performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line
terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of
VCC -2.0 V will need to be provided. For more inf
Features
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200ps Part-to-Part Skew
50ps Typical Output-to-Output Skew
The 100 Series Contains Temperature Compensation
ESD Protection: >2 KV HBM, >200 V MM
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
For more features, see the data sheet
Part Electrical Specifications
Product
Compliance
Status
Type
Chann
els
Input / Input
Output Level
Ratio
MC100LVE210FNG
Pb-free
Active
Buffer
1
1:5
Halide free
ECL
Output VCC
Level
Typ
(V)
tJitterR
MS
Typ
(ps)
tskew(oo) Max
(ps)
tpd Typ
(ns)
tR & tF
Max
(ps)
fmaxClo fmaxDat Packa
ck Typ a Typ ge
(MHz) (Mbps) Type
ECL
<1
75
0.7
600
700
3.3
1:4
For more information please contact your local sales support at www.onsemi.com
Created on: 6/30/2016
PLCC28