SEMICONDUCTOR TECHNICAL DATA The MC100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The MC100LVE111’s function and performance are similar to the popular MC100E111, with the added feature of low voltage operation. It accepts one signal input, which can be either differential or single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. • • • • • • • LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/PECL CLOCK DRIVER 200ps Part-to-Part Skew 50ps Output-to-Output Skew Differential Design VBB Output Voltage and Temperature Compensated Outputs Low Voltage VEE Range of –3.0 to –3.8V 75kΩ Input Pulldown Resistors The LVE111 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device, and empirical modeling is used to determineprocess control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. FN SUFFIX PLASTIC PACKAGE CASE 776-02 To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10–20ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. The MC100LVE111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE111 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE111’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For systems incorporating GTL, parallel termination offers the lowest power by taking advantage of the 1.2V supply as a terminating voltage. For more information on using PECL, designers should refer to Motorola Application Note AN1406/D. 12/94 Motorola, Inc. 1996 4–1 REV 1 MC100LVE111 Pins Function Differential Input Pair Differential Outputs VBB Output Q0 Q1 VCCO Q1 Q2 Q2 25 24 23 20 19 22 21 VEE 26 18 Q3 NC 27 17 Q3 IN 28 16 Q4 15 VCCO PIN NAMES IN, IN Q0, Q0–Q8, Q8 VBB Q0 VCC Pinout: 28-Lead PLCC (Top View) 1 IN 2 14 Q4 VBB 3 13 Q5 NC 4 12 Q5 5 6 7 Q8 Q8 Q7 8 9 VCCO Q7 10 11 Q6 Q6 LOGIC SYMBOL Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 IN Q4 IN Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 VBB MOTOROLA 4–2 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVE111 ECL DC CHARACTERISTICS –40°C Symbol 0°C 25°C 85°C Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit VOH Output HIGH Voltage –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 V VOL Output LOW Voltage –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 V VIH Input HIGH Voltage –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 V VIL Input LOW Voltage –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 V VBB Output Reference Voltage –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V VEE Power Supply Voltage –3.0 –3.8 –3.0 –3.8 –3.0 –3.8 –3.0 –3.8 V IIH Input HIGH Current 150 µA IEE Power Supply Current 78 mA 150 55 150 66 55 150 66 55 66 65 PECL DC CHARACTERISTICS –40°C Symbol Characteristic 0°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit VOH Output HIGH Voltage1 2.275 2.345 2.420 2.275 2.345 2.420 2.275 2.345 2.420 2.275 2.345 2.420 V VOL Output LOW Voltage1 1.490 1.595 1.680 1.490 1.595 1.680 1.490 1.595 1.680 1.490 1.595 1.680 V VIH Input HIGH Voltage1 2.135 2.420 2.135 2.420 2.135 2.420 2.135 2.420 V VIL Input LOW Voltage1 1.490 1.825 1.490 1.825 1.490 1.825 1.490 1.825 V VBB Output Reference Voltage1 1.92 2.04 1.92 2.04 1.92 2.04 1.92 2.04 V VCC Power Supply Voltage 3.0 3.8 3.0 3.8 3.0 3.8 3.0 IIH Input HIGH Current IEE Power Supply Current 150 55 150 66 55 150 66 55 66 65 3.8 V 150 µA 78 mA 1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC. AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND) –40°C Symbol Typ 0°C Max Min 650 700 435 385 Typ 25°C Max Min 625 675 440 390 Typ 85°C Characteristic Min Max Min tPLH tPHL Propagation Delay to Output IN (differential) IN (single-ended) 400 350 630 680 445 395 tskew Within-Device Skew Part-to-Part Skew (Diff) VPP Minimum Input Swing 500 VCMR Common Mode Range –1.5 –0.4 –1.5 –0.4 –1.5 –0.4 –1.5 tr/tf Output Rise/Fall Time 200 600 200 600 200 600 200 Typ Max Unit Condition ps 50 250 50 200 500 50 200 500 635 685 50 200 Note 1 Note 2 ps Note 3 mV Note 4 –0.4 V Note 5 600 ps 20%–80% 500 1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D). 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D). 3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the E111 as a differential input as low as 50 mV will still produce full ECL levels at the output. 5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min). ECLinPS and ECLinPS Lite DL140 — Rev 3 4–3 MOTOROLA MC100LVE111 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PACKAGE CASE 776-02 ISSUE D 0.18 (0.007) B Y BRK -N- D -L- T N 0.18 (0.007) U M S –P T N L S S –P S S –M S L S –M S S –P -M- 28 LEADS ACTUAL 28 M Z1 W D 1 -P- G1 V X 0.25 (0.010) M T N S L S –M –P S –M S VIEW D-D A 0.18 (0.007) M T L S –M S N S –P S R 0.18 (0.007) M T L S –M S N S –P S Z C E H 0.10 (0.004) -T- J G SEATING PLANE 0.18 (0.007) 0.18 (0.007) M M T L T N S S S N L S S –P –M S S K1 DETAIL S K G1 0.25 (0.010) S T L S –M S N S –P S F 0.18 (0.007) 0.18 (0.007) M M T L T N S S –M –P S S N L S S –P –M S S DETAIL S DIM A B C E F G H J K R U V W X Y Z G1 K1 Z1 MOTOROLA MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 — 0.50 2° 10° 10.42 10.92 1.02 — 2° 10° INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 — 0.025 — 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 — 0.020 2° 10° 0.410 0.430 0.040 — 2° 10° NOTES: 1. DUE TO SPACE LIMITATION, CASE 776-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 28 LEADS. 2. DATUMS -L-, -M-, -N-, AND -P- DETERMINED WHERE TOP OF LEAD SHOULDER EXIT PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.25 (0.010) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. 7. 776-01 IS OBSOLETE, NEW STANDARD 776-02. 4–4 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVE111 Motorola reserves the right to make changes without further notice to any products herein. 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