LTC4417 Prioritized PowerPath™ Controller Description Features Selects Highest Priority Supply from Three Inputs n Blocks Reverse and Cross Conduction Currents n Wide Operating Voltage Range: 2.5V to 36V n–42V Protection Against Reverse Battery Connection n Fast Switchover Minimizes Output Voltage Droop n Low 28µA Operating Current n<1µA Current Draw from Supplies Less than V OUT n1.5% Input Overvoltage/Undervoltage Protection n Adjustable Overvoltage/Undervoltage Hysteresis n P-Channel MOSFET Gate Protection Clamp n Cascadable for Additional Input Supplies n 24-Lead Narrow SSOP and 4mm × 4mm QFN Packages The LTC®4417 connects one of three valid power supplies to a common output based on priority. Priority is defined by pin assignment, with V1 assigned the highest priority and V3 the lowest priority. A power supply is defined as valid when its voltage has been within its overvoltage (OV) and undervoltage (UV) window continuously for at least 256ms. If the highest priority valid input falls out of the OV/UV window, the channel is immediately disconnected and the next highest priority valid input is connected to the common output. Two or more LTC4417s can be cascaded to provide switchover between more than three inputs. n The LTC4417 incorporates fast non-overlap switching circuitry to prevent both reverse and cross conduction while minimizing output droop. The gate driver includes a 6V clamp to protect external MOSFETs. A controlled output ramp feature minimizes start-up inrush current. Open drain VALID outputs indicate the input supplies have been within their OV/UV window for 256ms. Applications n n n n Industrial Handheld Instruments High Availability Systems Battery Backup Systems Servers and Computer Peripherals L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PowerPath, ThinSOT and Hot Swap are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application V1: 12V WALL ADAPTER IRF7324 V2: 14.8V Li-Ion MAIN/SWAPPABLE 2A OUTPUT IRF7324 V3: 12V SLA BACKUP Priority Switching from 12V V1 to 14.8V V2 IRF7324 V2 V1 VS1 G1 VS2 G2 806k VS3 G3 VOUT UV1 V1 1M 39.2k 1M 1M 14.8V VOUT 12V 2V/DIV VALID1 OV1 VALID2 60.4k V1 UV FAULT VALID3 V2 V3 = 0V, IL = 2A CL = 120µF 1.05M UV2 LTC4417 50ms/DIV 31.6k 4417 TA01b OV2 68.1k V3 EN SHDN HYS CAS 698k UV3 16.9k OV3 49.9k GND 4417 TA01a 4417f 1 LTC4417 Absolute Maximum Ratings (Notes 1, 2) Supply Voltages V1, V2, V3................................................ –42V to 42V VOUT, VS1, VS2, VS3............................... –0.3V to 42V Voltage from V1, V2, V3 to VOUT.................. –84V to 42V Voltage from VS1, VS2, VS3 to G1, G2, G3...................................................–0.3V to 7.5V Input Voltages EN, SHDN............................................... –0.3V to 42V OV1, OV2, OV3, UV1, UV2, UV3................ –0.3V to 6V HYS.......................................................... –0.3V to 1V Input Currents OV1, OV2, OV3, UV1, UV2, UV3, HYS................ –3mA Output Voltages VALID1, VALID2, VALID3......................... –0.3V to 42V CAS........................................................... –0.3V to 6V Output Currents VALID1, VALID2, VALID3, CAS..............................2mA Operating Ambient Temperature Range LTC4417C................................................. 0°C to 70°C LTC4417I..............................................–40°C to 85°C LTC4417H........................................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature GN Package (Soldering, 10 sec)......................... 300°C Pin Configuration 24 23 22 21 20 19 3 22 V3 UV1 1 18 VS1 UV1 4 21 VS1 OV1 2 17 G1 OV1 5 20 G1 UV2 3 UV2 6 19 VS2 OV2 4 OV2 7 18 G2 UV3 5 14 VS3 UV3 8 17 VS3 OV3 6 13 G3 OV3 9 16 G3 VOUT CAS 13 GND 15 G2 9 10 11 12 GND 14 CAS VALID3 12 8 VALID3 VALID2 11 7 VALID2 15 VOUT 16 VS2 25 VALID1 VALID1 10 V3 23 V2 HYS V2 24 V1 2 V1 1 SHDN EN EN HYS SHDN TOP VIEW UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 47°C/W, θJC = 4.5°C/W EXPOSED PAD (PIN 25) PCB GND CONNECTION OPTIONAL GN PACKAGE 24-LEAD NARROW PLASTIC SSOP TJMAX = 150°C, θJA = 85°C/W, θJC = 30°C/W Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4417CGN#PBF LTC4417CGN#TRPBF LTC4417GN 24-Lead Narrow Plastic SSOP 0°C to 70°C LTC4417IGN#PBF LTC4417IGN#TRPBF LTC4417GN 24-Lead Narrow Plastic SSOP –40°C to 85°C LTC4417HGN#PBF LTC4417HGN#TRPBF LTC4417GN 24-Lead Narrow Plastic SSOP –40°C to 125°C LTC4417CUF#PBF LTC4417CUF#TRPBF 4417 24-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C LTC4417IUF#PBF LTC4417IUF#TRPBF 4417 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C LTC4417HUF#PBF LTC4417HUF#TRPBF 4417 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4417f 2 LTC4417 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. For all tests, V1 = VS1, V2 = VS2, V3 = VS3. Unless otherwise noted, V1 = V2 = V3 = VOUT = 12V, HYS = GND. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Start-Up 36 V IV1-V3,VOUT(EN) Total Supply Current with Channels Enabled V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = 4V, (Notes 3, 4) l 28 78 µA IV1-V3(EN) Total Supply Current with Channels Disabled V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = EN = 0V, (Notes 3, 4) l 31 93 µA IV1-V3(SHDN) Total Supply Current When Shutdown V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = SHDN = 0V, (Notes 3, 4) l 15.4 84 µA V1-V3,VOUT V1 to V3,VOUT Operating Supply Range l 2.5 IVOUT VOUT Supply Current V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = 4V l 14 30 µA IPRIORITY Current from Highest V1 to V3 Priority Input Source (V1) V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = 4V V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = EN = 0V l l 2.6 20 6 45 µA µA IHIGHEST Current from Highest V1 to V3 Voltage Input Source V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = 4V, (Note 3, 4) l 11 72 µA V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = EN = 0V, SHDN = 0V, (Note 3, 4) l 15 80 µA –5 0.2 1 µA Current from V1 to V3 Input Voltage Sources Lower than VOUT V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = 4V Not Highest Valid Priority ∆VG Open (VS – VG) Clamp Voltage VOUT = 11V, G1 to G3 = Open l 5.4 6.2 6.7 V ∆VG(SOURCE) Sourcing (VS – VG) Clamp Voltage VOUT = 11V, I = –10µA l 5.8 6.6 7 V ∆VG(SINK) Sinking (VS – VG) Clamp Voltage VOUT = 11V, I = 10µA l 4.5 5.2 6 V ∆VG(OFF) G1 to G3 Off (VS – VG) Threshold V1 = V2 = V3 = 2.8V, VOUT = 2.6V, G1 to G3 Rising Edge l 0.12 0.35 0.6 V ∆VG(SLEW,ON) G1 to G3 Pull-Down Slew Rate VOUT = 11V, CGATE = 10nF (Note 5) l 4 9 20 V/µs ∆VG(SLEW,OFF) G1 to G3 Pull-Up Slew Rate VOUT = 11V, CGATE = 10nF (Note 6) l 7.5 13 22 V/µs IG(DN) G1 to G3 Low Pull-Down Current VOUT = 2.6V, V1 to V3 = 2.8V, (G1 to G3) = ∆VG + 300mV 0.8 2 7 µA RG(OFF) G1 to G3 OFF Resistance VOUT = 4V, V1 to V3 = 5V, IG = –10mA l 9 16 26 Ω VREV Reverse Voltage Threshold Measure (V1 to V3) – VOUT, VOUT Falling l 30 120 200 mV ILOWER Gate Control VOUT = 11V, CGATE = 10nF, (Note 7) l 0.7 2 3 µs tpG(SHDN) tG(SWITCHOVER) Pin Break-Before-Make Time G1 to G3 Turn-Off Delay From SHDN VOUT = 11V, Falling Edge SHDN to (G1 to G3) = (VS1 to VS3) – 3V, CGATE = 10nF l 20 50 100 µs tpG(EN,OFF) G1 to G3 Turn-Off Delay From EN VOUT = 11V, Falling EN Edge to (G1 to G3) = (VS1 to VS3) – 3V, CGATE = 10nF l 0.3 0.7 1.4 µs tpG(EN,ON) G1 to G3 Turn-On Delay From EN VOUT = 11V, Rising EN Edge to (G1 to G3) = (VS1 to VS3) – 3V, CGATE = 10nF l 1 1.4 2 µs 4417f 3 LTC4417 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. For all tests, V1 = VS1, V2 = VS2, V3 = VS3. Unless otherwise noted, V1 = V2 = V3 = VOUT = 12V, HYS = GND. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.25 0.55 V 8 13 µs Input/Output Pins VVALID(OL) VALID1 to VALID3 Output Low Voltage tpVALID(OFF) VALID1 to VALID3 Delay OFF From OV/UV Fault I = 1mA, (V1 to V3) = 2.5V, VOUT = 0V l l 5 1.4 VCAS(OH) CAS Output High Voltage I = –1µA l VCAS(OL) CAS Output Low Voltage I = 1mA l ICAS CAS Pull-Up Current SHDN = 0V, CAS = 1V l 2 3 V 0.2 0.4 V –6 –20 –40 µA tpCAS(EN) CAS Delay from VG(OFF) VOUT = 11V l 0.4 0.7 1.3 µs VEN(THR) EN Threshold Voltage EN Rising l 0.6 1 1.4 V VSHDN(THR) SHDN Threshold Voltage SHDN Rising l 0.4 0.8 1.2 VSHDN_EN(HYS) SHDN, EN Threshold Hysteresis 100 ISHDN_EN SHDN, EN Pull-Up Current SHDN = EN = 0V l ILEAK SHDN, EN, VALID1 to VALID3, CAS Leakage Current SHDN = EN = (VALID1 to VALID3) = 36V, CAS = 5.5V l –0.5 –2 V mV –5 µA ±1 µA V OV, UV Protection Circuitry VOV_UV(THR) OV1 to OV3, UV1 to UV3 Comparator Threshold VOUT = 11V, OV1 to OV3 Rising, UV1 to UV3 Falling l 0.985 1 1.015 VOV_UV(HYS) OV1 to OV3, UV1 to UV3 Comparator Hysteresis VOUT = 11V l 15 30 45 mV IUV_OV(LEAK) OV1 to OV3, UV1 to UV3 Leakage Current OV1 to OV3 = 1.015V, UV1 to UV3 = 0.985V l ±20 nA IOV_UV(MIN) Minimum External Hysteresis Current IHYS = –400nA l 35 50 75 nA IOV_UV(MAX) Maximum External Hysteresis Current IHYS = –4µA l 420 520 620 nA VHYS HYS Voltage IHYS = –4µA l 470 495 520 mV tVALID V1 to V3 Validation Time 100 256 412 ms Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND unless otherwise specified. Note 3: Each V1 to V3 supply current specification includes current into the corresponding VS1 to VS3 for the channel(s) being tested. Note 4: Specification represents the total diode-ORed current of V1 to V3 input supplies, selecting the highest voltage as the input source. If two input supplies are similar in voltage and higher than the remaining input supply voltage, the current is split evenly between the two higher voltage supplies. Current is split evenly if all supplies are equal. Note 5: Falling edge of G1 to G3 measured from 11V to 8V. Note 6: Rising edge of G1 to G3 measured from 7V to 11V. Note 7: UV1 driven below VOV,UV(THR). Time is measured from respective rising edge G1 to G3 crossing (VS1 to VS3) – 3V to next valid priority falling edge G1 to G3 crossing (VS1 to VS3) – 3V. 4417f 4 LTC4417 Typical Performance Characteristics Total Shutdown Supply Current vs Supply Voltage Total Enabled Supply Current vs Supply Voltage 20 15 10 5 0 35 14 30 12 25 20 15 10 ALL SUPPLY, VS AND VOUT PINS CONNECTED TOGETHER 16 6.35 14 GATE FALLING SLEW RATE (V/µs) 6.40 ∆VG (V) 6.15 6.10 6.05 6.00 –50 –25 0 25 50 75 TEMPERATURE (°C) 10 20 30 SUPPLY VOLTAGE (V) 0 100 V1 = 36V 125 10 V1 = 12V 8 6 4 V1 = 5V 2 V1 = 2.7V –25 0 25 50 75 TEMPERATURE (°C) 100 125 0 25 50 75 TEMPERATURE (°C) V1 = 5V 8 4 100 125 4417 G07 V1 = 2.7V V1 = V2 = V3 CGATE = 10nF –25 75 0 25 50 TEMPERATURE (°C) 125 4417 G06 8.5 8.4 2.0 1.5 1.0 0 –50 100 Valid Delay Off Time vs Temperature 0.5 –25 12 0 –50 VALID DELAY TIME (µs) tG(SWITCHOVER) (µs) 0.5 40 V1 = 12V, 24V, 36V 2.5 1.0 10 20 30 V2 = VS2 VOLTAGE (V) 0 16 CGATE = 10nF V1 = V2 = V3 3.0 1.5 V3 = VS3 = 2.8V 4417 G03 Switchover Time vs Temperature 2.0 V1 = VS1 = 5V 4417 G05 2.5 IG(DN) (µA) 0 40 V1 = 24V 12 0 –50 IG(DN) vs Temperature 0 –50 6 Gate Rising Slew Rate vs Temperature 4417 G04 3.0 8 Gate Falling Slew Rate vs Temperature 6.20 V2 = VS2 10 4417 G02 ΔVG vs Temperature 6.25 VOUT = 4.9V 2 4417 G01 6.30 IV1-V3,VOUT(EN) vs Supply Voltage 4 5 0 40 10 20 30 SUPPLY VOLTAGE (V) 16 GATE RISING SLEW RATE (V/µs) 0 ALL SUPPLY AND VS PINS CONNECTED TOGETHER, VOUT = 0V 40 IV1-V3,VOUT(EN) (µA) TOTAL ENABLE SUPPLY CURRENT (µA) TOTAL SHUTDOWN SUPPLY CURRENT (µA) 25 8.3 8.2 8.1 8.0 7.9 7.8 –25 0 25 50 75 TEMPERATURE (°C) 100 125 4417 G08 7.7 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 4417 G09 4417f 5 LTC4417 Typical Performance Characteristics 0.5 VVALID(OL) vs Pull-Up Current 1.04 VOV,UV vs Temperature 1.03 0.3 0.2 1.01 V1 1.00 VOV,UV(THR) 0.99 100ms/DIV 0 2.0 0.5 1.0 1.5 PULL-UP CURRENT (mA) 0.96 –50 –25 0 25 50 75 TEMPERATURE (°C) 125 VOUT Switching from Lower to Higher Voltage with Slew Rate Control Circuitry VOUT Switching from Higher to Lower Voltage V2 2V/DIV VOUT 100 4417 G11 4417 G10 V2 V1 = 20V IVOUT 5A/DIV 100µs/DIV CL = 122µF IL = 1A –40V PCH FDD4685 Reverse Voltage Blocking V2, VOUT 10V/DIV VOUT V1 2V/DIV 2V/DIV V1 4417 G12 CL = 122µF IL = 1A –40V PCH FDD4685 VOV(FALLING) 0.97 0 VOUT 2V/DIV 0.98 0.1 V2 VUV(RISING) 1.02 VOV,UV (V) VVALID(OL) (V) 0.4 Deglitched Connection V1 = –20V 4417 G13 20µs/DIV RS = 1.43kΩ CS = 6.8nF CL = 100µF IL = 1A –40V PCH FDD4685 4417 G14 5µs/DIV 4417 G15 CL = 122µF IL = 1A –40V PCH FDD4685 Pin Functions CAS: Cascade Output. Digital output used for cascading multiple LTC4417s. Connect CAS to EN of another LTC4417 to increase the number of multiplexed input supplies. CAS is pulled up to the internal VLDO voltage by an internal 20µA current source to indicate when all inputs are invalid, the external P-channel MOSFETs are determined to be off, and EN is above 1V. CAS also pulls high when SHDN is driven below 1V. CAS is pulled low when any input supply is within the OV/UV window for at least 256ms and both SHDN and EN are above 1V. CAS also pulls low when EN is driven below 1V. CAS can be driven to 5.5V independent of the input supply voltages. Leave open if not used. EN: Channel Enable Input. EN is a high voltage input that allows the user to quickly connect and disconnect channels without resetting the OV/UV timers. When below 1V, all external back-to-back P-channel MOSFETs are driven off by pulling G1, G2 and G3 to their respective VS1, VS2 and VS3. When above 1V, the highest valid priority channel is connected to the output. EN is pulled to the internal VLDO voltage with a 2µA current source and can be pulled up externally to a maximum voltage of 36V. Leave open when not used. Exposed Pad (UF Package Only): Exposed pad may be left open or connected to device ground. 4417f 6 LTC4417 Pin Functions G1, G2, G3: P-Channel MOSFET Gate Drive Outputs. G1, G2 and G3 are used to control external back-to-back Pchannel MOSFETs. When driven low, G1, G2 and G3 are clamped 6V below their corresponding VS1, VS2 and VS3. Connect G1, G2 and G3 to external P-channel MOSFET gate pins. See Dual Channel Applications Section for connecting unused channels. GND: Device Ground. HYS: OV/UV Comparator Hysteresis Input. Connecting HYS to ground sets a fixed 30mV hysteresis for the OV and UV comparators. Connecting a resistor, RHYS, between HYS and ground disables the internal 30mV hysteresis and sets a 63mV/RHYS hysteresis current which is sourced from each OV1, OV2 and OV3 and sunk into each UV1, UV2 and UV3 pin. Connect to ground when not used. OV1, OV2, OV3: Overvoltage Comparator Inputs. Rising voltages above 1V signal an over voltage event, invalidating the respective input supply channel. Connect OV1, OV2 and OV3 to an external resistive divider from its respective V1, V2 and V3 to achieve the desired overvoltage threshold. The comparator hysteresis can be set to an internally fixed 30mV or set externally via the HYS pin. Connect unused pins to ground. SHDN: Shutdown Input. Driving SHDN below 0.8V turns off all external back-to-back P-channel MOSFET devices, forces the LTC4417 into a low current state, and resets the 256ms timers used to validate V1, V2 and V3. Driving SHDN above 0.8V allows channels to validate and connect. SHDN is pulled high to the internal VLDO voltage with a 2µA current source and can be pulled up externally to a maximum voltage of 36V. Leave open when not used. UV1, UV2, UV3: Undervoltage Comparator Inputs. Falling voltages below 1V signal an undervoltage event, invalidating the respective input supply channel. Connect UV1, UV2 and UV3 through a resistive divider between the respective V1, V2 and V3 and ground to achieve the desired undervoltage threshold. The comparator hysteresis can be set to an internally fixed 30mV or set externally via the HYS pin. Connect pins from unused channels to ground. V1: Highest Priority Input Supply. When V1 is within its user defined OV/UV window for 256ms, it is connected to VOUT via its external back-to-back P-channel MOSFETs. Connect V1 to ground when channel is not used. See Applications Information for bypass capacitor recommendations. V2: Second Priority Input Supply. When V2 is within its OV/UV window for 256ms, it is connected to VOUT via its external back-to-back P-channel MOSFETs only if V1 does not meet its OV/UV requirements. Connect to ground when channel is not used. See Applications Information for bypass capacitor recommendations. V3: Third Priority Input Supply. When V3 is within its OV/UV window for 256ms, it is connected to VOUT via its external back-to-back P-channel MOSFETs only if V1 and V2 do not meet their OV/UV requirements. Connect to ground when channel is not used. See Applications Information for bypass capacitor recommendations. VALID1, VALID2, VALID3: Valid Channel Indicator Outputs. VALID1, VALID2 and VALID3 are high voltage open drain outputs that pull low when the respective V1, V2 and V3 are within the OV/UV window for at least 256ms and release when the respective V1, V2 and V3 are outside the OV/ UV window. Connect a resistor between VALID1, VALID2 and VALID3 and a desired supply, up to a maximum of 36V, to provide the pull-up. Leave open when not used. VS1, VS2, VS3: External P-Channel MOSFET Common Source Connection. VS1, VS2 and VS3 supply the higher voltage of V1, V2 and V3 or VOUT to the gate drivers. Connect VS1, VS2 and VS3 to the respective common source connection of the back-to-back P-channel MOSFETs. Connect to ground when channel is not used. See Applications Information section for bypass capacitor recommendations. VOUT: Output Voltage Supply and Sense. VOUT is an output voltage sense pin used to prevent any input supply from connecting to the output if the output voltage is not at least 120mV below the input supply voltage. During normal operation, VOUT powers most of the internal circuitry when its voltage exceeds 2.4V. Connect VOUT to the output. See Applications Information section for bypass capacitor recommendations. 4417f 7 LTC4417 Functional Block Diagram VLDO + – 1V VLDO + – 1V VLDO V3 VBEST VLDO D3 V2 BANDGAP UVLO EN VBLDO LDO P1 V1 VBLDO IEN 2µA EN VBESTGEN SHDN P2 P3 P4 LDO PRIORITIZER P5 VLDO SHDN ILIM 5µA 0.24V 0.5V 1V UV3 OV1 1V OV2 VLDO ICAS 20µA VLDO D1 HYS CAS 30mV IHYS/8 VLDO UV2 + – EXTERNAL HYS VS1 HYSTERESIS + – REV UV VLDO + – M3 GND PRIORITIZED NONOVERLAP CONTROL LOGIC OV + 256ms TIMER 120mV +– V1 V2 CH1 VALID V3 VS1 VGS + – + – OTA UV1 VS1 +– VS2 350mV OV3 VALID3 DZ1 6.2V VS3 G1 VALID1 VALID2 2.4V VLDO + – VLDO HYS + – M2 CURRENT SENSE/8 M4 VOUT HIGHEST VALID PRIORITY VLDO D2 SHDN VOUT V1 V2 V3 ISHDN 2µA GATE DRIVER M1 CHANNEL 1 G2 G3 CHANNEL 2 CHANNEL 3 4417 BD 4417f 8 LTC4417 Timing Diagram G2 G1 VALID2 VALID1 UV2 UV1 EN SHDN 4417 TD t VALID tpVALID(OFF) tG(SWITCHOVER) tpG(EN,OFF) tpG(EN,ON) tpG(SHDN) 4417f 9 LTC4417 Operation The Functional Block Diagram displays the main functional blocks of this device. The LTC4417 connects one of three power supplies to a common output, VOUT, based on user defined priority. Connection is made by enhancing external back-to-back P-channel MOSFETs. Unlike a diode-OR, which always passes the highest supply voltage to the output, the LTC4417 lets one use a lower voltage supply for primary power and a higher voltage supply as secondary or backup power. During normal operation the LTC4417 continuously monitors V1, V2 and V3 through its respective OV1, OV2 and OV3 and UV1, UV2 and UV3 pins using precision overvoltage and undervoltage comparators. The highest priority input supply whose voltage is within its respective OV/UV window for at least 256ms is considered valid and is connected to VOUT through external back-to-back P-channel MOSFETs. VALID1, VALID2 and VALID3 pull low to indicate when the V1, V2 and V3 input supplies are valid. Hysteresis on the OV and UV threshold is adjustable. Connecting a resistor, RHYS, between HYS and ground forces 63mV/RHYS current to flow out of OV1, OV2 and OV3 and into UV1, UV2 and UV3 to create hysteresis when outside their respective OV/UV windows. Connecting HYS to ground sets the OV and UV comparator hysteresis to 30mV. See the Application Information for more details. During channel transitions, monitoring circuitry prevents cross conduction between input channels and reverse conduction from VOUT using a break-before-make architecture. The VGS comparator monitors the disconnecting channel’s gate pin voltage (G1, G2 or G3). When the gate voltage is 350mV from its common source connection (VS1, VS2 or VS3), the VGS comparator latches the output to indicate the channel is off and allows the next valid priority input supply to connect to VOUT, preventing cross conduction between channels. The latch is reset when the channel is turned on. To prevent reverse conduction from VOUT to V1, V2 and V3 during channel switchover, the REV comparator monitors the connecting input supply (V1, V2 or V3) and output voltage (VOUT). The REV comparator delays the connection until the output voltage droops lower than the input voltage by the reverse current blocking threshold of 120mV. The output of the REV comparator is latched, resetting when its respective channel is turned off. The LTC4417 gate driver pulls down on G1, G2 and G3 with a strong P-channel source follower and a 2µA current source. When the clamp voltage is reached, the P-channel source follower is back biased, leaving the 2µA current source to hold G1, G2 and G3 at the clamp voltage. To minimize inrush current at start-up, the gate driver soft-starts the first input supply to connect VOUT, at a rate of around 5V/ms terminating when any channel disconnects or 32ms has elapsed. Once slew rate control has terminated, the gate driver quickly turns on and off external back-to-back P-channel MOSFETs as needed. A SHDN low to high transition or VOUT drooping below 0.7V reactivates soft-start. When EN is driven above 1V the highest valid priority input supply is connected to VOUT. The high voltage EN comparator disconnects all channels when EN is driven below 1V. The LTC4417 continues to monitor the OV and UV pins and reflects the current input supply status with VALID1, VALID2 and VALID3. When four or more supplies need to be prioritized, connect the higher priority LTC4417’s CAS to the lower priority LTC4417’s EN. If VOUT is allowed to fall below 0.7V, the next connecting input supply is soft-started. The high voltage SHDN comparator forces the LTC4417 into a low current state when SHDN is forced below 0.8V. While in the low current state, all channels are disconnected, OV and UV comparators are disabled, and all 256ms timers are reset. When SHDN transitions from low to high, the first validated input to connect to VOUT is soft-started. Two separate internal power rails ensure the LTC4417 is functional when one or more input supply is present and above 2.3V. VBESTGEN generates a VBLDO rail from the highest V1, V2 and V3 and VOUT voltage. VBLDO powers the UVLO, bandgap, and VOUT comparator. The internal VLDO powers all other circuits from VOUT provided VOUT is greater than 2.4V. If VOUT is less than 2.3V, VLDO powers all other circuits from the highest priority supply available. If all sources are invalid or the LTC4417 is shut down, VLDO connects to VBLDO. 4417f 10 LTC4417 Applications Information Introduction highest valid priority is connected to the common output. If a lower priority input supply is connected to VOUT and a higher priority input supply becomes valid, the LTC4417 disconnects the lower priority supply and connects the higher priority input supply to VOUT. The LTC4417 is an intelligent high voltage triple load switch which automatically connects one of three input supplies to a common output based on predefined pin priorities and validity. V1 is defined to be the highest priority and V3 the lowest priority, regardless of voltage. An input supply is defined valid when the voltage remains in the user defined overvoltage (OV) and undervoltage (UV) window for at least 256ms. Typical LTC4417 applications are systems where predictable autonomous load control of multiple input supplies is desired. These supplies may not necessarily be different in voltage, nor must the highest voltage be the primary supply. A typical LTC4417 application circuit is shown in Figure 1. External component selection is discussed in detail in the following sections. If a connected input supply falls out of the user defined OV/UV window and remains outside the OV/UV window for at least 8µs, the channel is disconnected and the next 12V WALL ADAPTER + M1 IRF7324 VOUT M2 + CIN1 2200µF 7.4V Li-Ion PRIMARY BATTERY M3 + IRF7324 M4 7.4V Li-Ion SECONDARY BATTERY M5 + IRF7324 M6 LTC3690 SWITCHING REGULATOR CVS1 0.1µF CV3 0.1µF CL 100µF CV2 0.1µF CV1 0.1µF VS1 R3 806k R2 39.2k R1 60.4k R6 931k R5 63.4k R4 137k R9 931k R8 63.4k R7 137k CVS2 0.1µF G1 CVS3 0.1µF VS2 G2 V1 VS3 G3 R10 1M VOUT UV1 VALID1 VALID2 OV1 VALID3 R11 1M R12 1M 3.3V 4A ADAPTER INVALID PRIMARY INVALID SECONDARY INVALID V2 UV2 LTC4417 OV2 V3 EN SHDN HYS CAS UV3 OV3 GND 4417 F01 Figure 1. Typical Hand Held Computer Application. 4417f 11 LTC4417 Applications Information Defining Operational Range V1 INPUT SUPPLY To guard against noise and transient voltage events during live insertion, the LTC4417 requires an input supply remain in the OV/UV window for at least 256ms to be valid. The OV/UV window for each input supply is set by a resistive divider (for example, R1, R2 and R3 for V1 input supply) connected from the input supply to GND, as shown in Figure 1. When setting the resistive divider values for the OV and UV input supply threshold, take into consideration the tolerance of the input supply, 1.5% error in the OV and UV comparators, tolerance of R1, R2 and R3, and the ±20nA maximum OV/UV pin leakage currents. In addition to tolerance considerations, hysteresis reduces the valid input supply operating range. Input supplies will need to be within the reduced input supply operating range to validate. Referring to Figure 2, V1 supply voltage must be greater than UVHYS to exit the UV fault. If an OV fault occurs, the V1 supply voltage must return to a voltage lower than the OVHYS voltage to exit the OV fault. V1 R10 R12 R11 OV1 R4 LTC4417 UV1 VALID VOUT VALID1 RP R2 256ms TIMER VLDO HYS IHYS/8 OV1 1V R1 GND + – M1 OV IHYS RHYS 124k TO 1.24M OV1 VALID 4417 F03 Figure 3. LTC4417 External Hysteresis Independent OV and UV hysteresis values are available by separating the single string resistive dividers R1, R2 and R3, shown in Figure 3, into two resistive strings, R4R5 and R6-R7. In such a configuration, the top resistor defines the amount of hysteresis and the bottom resistor defines the threshold. Use Equations (2) and (3) to calculate the values. RTOP = HYST IOVUV(HYS) (2) where HYST is the desired hysteresis voltage at V1. OV1 FAULT V1 VALID 4417 F02 Figure 2. OV and UV Thresholds and Hysteresis Voltage Hysteresis for the OV and UV comparators are set via the HYS pin. Two options are available. Connecting a resistor, RHYS, between HYS and GND, as shown in Figure 3, sets the hysteresis current IOV_UV(HYS) that is sunk into UV1, UV2 and UV3 and sourced out of OV1, OV2 and OV3. The value of RHYS is calculated with Equation (1). Choose RHYS to limit the hysteresis current to between 50nA and 500nA. UV IHYS/8 DUALRESISTIVE CONNECTION OPTIONAL INDEPENDENT HYSTERESIS UV1 FAULT 63mV IOVUV(HYS) 1V + – R5 V1 RHYS = UV1 R6 OV1 T-RESISTIVE CONNECTION UVHYS UV UV1 UV1 R8 OV OV/UV WINDOW R3 R9 OVHYS REDUCED OPERATING WINDOW R7 (1) where 50nA ≤ IOVUV(HYS) ≤ 500nA RBOTTOM = RTOP (OV/ UV Threshold) – 1 (3) When large independent hysteresis voltages are required, a resistive T structure can be used to define hysteresis values, also shown in Figure 3. After the desired OV and UV thresholds are set with resistors R8 through R10, R11 and R12 are calculated using: R11= R12 = R8 • ⎡⎣OVHYS – IOVUV(HYS) • (R9 +R10)⎤⎦ IOVUV(HYS) • (R8 +R9 +R10) (4) (R8 +R9) • ⎡⎣UVHYS – IOVUV(HYS) • R10⎤⎦ IOVUV(HYS) • (R8 +R9 +R10) (5) where OVHYS, UVHYS are the desired OV and UV hysteresis voltage magnitudes at V1 through V3, and IOVUV(HYS) is the programmed hysteresis current. 4417f 12 LTC4417 Applications Information Reduction of the valid operating range can be used to prevent disconnected high impedance input supplies from reconnecting. For example, if 3 series connected AA Alkaline batteries with a total series resistance of 675mΩ is used to source 500mA, the voltage drop due to the series resistance would be 337.5mV. Once the batteries are discharged and are disconnected due to a UV fault, the AA battery stack would recover the 337.5mV drop across the internal series resistance. Using the 30mV fixed internal hysteresis allows only 81mV of hysteresis at the input pin, possibly allowing the input supply to revalidate and reconnect. Using external hysteresis, the hysteresis voltage can be increased to 400mV, reducing or eliminating the reconnection issue, as shown in Figure 4. VALID UV RANGE FOR 400mV HYSTERESIS VALID UV RANGE FOR 81mV HYSTERESIS 337.5mV RECOVERY WHEN LOAD IS DISCONNECTED 400mV HYSTERESIS The LTC4417 provides an 8µs OV/UV fault filter time. If the 8µs filter time is not sufficient, add a filter capacitor between the OV or UV pin and GND to extend the fault filter time and ride through transient events. A UV pin fault filter time extension capacitor, CUVF, is shown in Figure 5. Use Equation (6) to select CUVF for the UV pin and Equation (7) to select COVF for the OV pin. FULLY CHARGED 3 × AA BATTERY V1 Filtering Noise on OV and UV Pins 81mV HYSTERESIS 2.7V UV THRESHOLD CUVF = tDELAY • ⎡V –V ⎤ R1+R2+R3 • ln⎢ i f ⎥ R3 • (R1+R2) ⎣ 1V – Vf ⎦ (6) COVF = tDELAY • ⎡V –V ⎤ R1+R2+R3 • ln⎢ i f ⎥ R1• (R2+R3) ⎣ 1V – Vf ⎦ (7) where the final input voltage Vf and the initial voltage Vi are the resistively divided down values of the input supply step, as shown in Figure 6. VIN(INIT) INPUT SUPPLY STEP 4417 F06 V1 UV FAULT AND DISCONNECTS VIN(FINAL) Figure 4. Setting a Higher UV Hysteresis to Prevent Unwanted Reconnections Vi = Connecting HYS to GND, as shown in Figure 5, selects an internal 30mV fixed hysteresis, resulting in 3% of the input supply voltage. V1 R3 1V CUVF 1.03V + – UV UV1 VALID OPTIONAL FILTER CAPACITOR OPTIONAL DISCONNECT VALID1 256ms TIMER 1V M2 R2 OV1 0.97V + – OV WITH FAULT FILTER TIME EXTENSION 1V VOVUV(THR) VIN(FINAL) •(R1+R2) R1+R2+R3 tDELAY VOUT LTC4417 UV1 R1+R2+R3 WITHOUT FAULT FILTER TIME EXTENSION Vf = V1 INPUT SUPPLY VIN(INIT) •(R1+R2) M1 OV1 VALID RP 4417 F05 Figure 6. Fault Filter Time Extension Extending the filter time delay will result in a slower response to fast UV and OV faults. Extending the UV pin fault filter time delay will also add delay to the OV pin. If this is not desirable, separate the single resistive string into two resistive strings, as shown in Figure 3. R1 GND HYS Priority Reassignment 4417 F04 Figure 5. LTC4417 Internal Hysteresis with Optional Filter Capacitor and Manual Disconnect MOSFET A connected input supply can be manually disconnected by artificially creating a UV fault. An example is shown in Figure 5. When N-channel MOSFET, M2, is turned on, the 4417f 13 LTC4417 Applications Information UV1 pin is pulled below 1V. The LTC4417 then disconnects V1 and connects the next highest valid priority to VOUT. When selecting the external N-channel MOSFET, be sure to account for drain leakage current when setting UV and OV thresholds by adjusting the resistive divider to consume more current. Selecting External P-Channel MOSFETS The LTC4417 drives external back-to-back P-channel MOSFETs to conduct or block load current between an input supply and load. When selecting external P-channel MOSFETs, the key parameters to consider are on-resistance (RDS(ON)), absolute maximum rated drain to source breakdown voltage (BVDSS(MAX)), threshold voltage (VGS(TH)), power dissipation, and safe operating area (SOA). To determine the required RDS(ON) use Equation (8), where VDROP is the maximum desired voltage drop across the two series MOSFETs at full load current, IL(MAX), for the application. External P-channel MOSFET devices may be paralleled to further decrease resistance and decrease power dissipation of each paralleled MOSFET. V RDS(ON) ≤ DROP 2 •IL(MAX) (8) The clamped gate drive output is 4.5V (minimum) from the common source connection. Select logic level or lower threshold external MOSFETs to ensure adequate overdrive. For applications with input supplies lower than the clamp voltage, choose external MOSFET with thresholds sufficiently lower than the input supply voltage to guarantee full enhancement. It is imperative that external P-channel MOSFET devices never exceed their BVDSS(MAX) rating in the application. Select devices with BVDSS(MAX) ratings higher than seen in the application. Switching inductive supply inputs with low value input and/or output capacitances may require additional precautions; see Transient Supply Protection section in this data sheet for more information. In normal operation, the external P-channel MOSFET devices are either fully on, dissipating relatively low power, or off, dissipating no power. However, during slew-rate controlled start-up, significant power is dissipated in the external P-channel MOSFETs. The external P-channel MOSFETs dissipate the maximum amount of power during the initial slew-rate limited turn on, where the full input voltage is applied across the MOSFET while it sources current. Power dissipation immediately starts to decrease as the output voltage rises, decreasing the voltage drop across the MOSFETs. A conservative approach for determining if a particular device is capable of supporting soft-start, is to ensure its maximum instantaneous power, at the start of the output slewing, is within the manufacturer’s SOA curve. First determine the duration of soft-start using Equation (9) and find the inrush current into the load capacitor using Equation (10). tSTARTUP = VIN 5 [ V/ ms] (9) IMAXCAP = CL • 5000[V/s](10) Using VIN and IMAXCAP, the power dissipated by the external MOSFETs during start-up, PSS, is defined by Equation (11). If the LTC4417 soft-starts with a live IL, the extra load current needs to be added to IMAXCAP, and PSS is calculated by Equation (12). PSS = VIN • IMAXCAP(11) PSS = VIN • (IMAXCAP + IL)(12) Check to ensure PSS with a tSTARTUP single pulse duration lies within the safe operating area (SOA) of the chosen MOSFET. Ensure the resistive dividers can sink the drainsource leakage current at the maximum operating temperature. Refer to manufacturer’s data sheet for maximum drain to source leakage currents, IDSS. A list of suggested P-channel MOSFETs is shown in Table 1. Use procedures outlined in this section and the SOA curves in the chosen MOSFET manufacturer’s data sheet to verify suitability for the application. 4417f 14 LTC4417 Applications Information Table 1. List of Suggested P-Channel MOSFETs V1, V2, V3 MOSFET ≤5V Si4465ADY V2 DISCONNECTS V2 = 18V MAX RATED VTH(MAX) VGS(MAX) VDS(MAX) RDS(ON) AT 25°C –1V ±8V –8V VOUT 9mΩ at –4.5V 11mΩ at –2.5V V1 VALIDATES ≤10V Si4931DY* –1V ±8V –12V 18mΩ at –4.5V 22mΩ at –2.5V ≤18V FDS8433A –1V ±8V –20V 47mΩ at –4.5V 70mΩ at –2.5V VOUT V1 = 12V ≤18V IRF7324* –1V ±12V –20V 18mΩ at –4.5V 26mΩ at –2.5V ≤28V Si7135DP –3V ±20V –30V 6.2mΩ at –4.5V ≤28V FDS6675BNZ –3V ±20V –30V 22mΩ at –4.5V ≤28V AO4803A* –2.5V ±20V –30V 46mΩ at –4.5V ≤36V SUD50P04 –2.5V ±20V –40V 30mΩ at –4.5V ≤36V FDD4685 –3V ±20V –40V 35mΩ at –4.5V ≤36V FDS4685 –3V ±20V –40V 35mΩ at –4.5V ≤36V Si4909DY* –2.5V ±20V –40V 34mΩ at –4.5V ≤36V Si7489DP –3V ±20V –100V 47mΩ at –4.5V dVOUT IL = dt CL V1 = 12V 256ms VREV = 120mV V1 CONNECTS AT VOUT = 11.88V 4417 F07 Figure 7. Reverse Current Blocking *Denotes Dual P-Channel The LTC4417 validates V1 and disconnects V2, allowing VOUT to decay from 18V to 11.88V at a slew rate determined by the load current divided by the load capacitance. Once VOUT falls to 11.88V, the LTC4417 connects V1 to VOUT. Reverse Voltage Protection Selecting VOUT Capacitance The LTC4417 is designed to withstand reverse voltages applied to V1, V2 and V3 with respect to VOUT of up to –84V. The large reverse voltage rating protects 36V input supplies and downstream devices connected to VOUT against high reverse voltage connections of –42V (absolute maximum) with margin. Select back-to-back P-channel MOSFETS with BVDSS(MAX) ratings capable of handling any anticipated reverse voltages between VOUT and V1, V2 or V3. Ensure transient voltage suppressors (TVS) connected to reverse connection protected inputs (V1, V2 and V3) are bidirectional and input capacitors are rated for the negative voltage. Reverse Current Blocking When switching channels from higher voltages to lower voltages, the REV comparator verifies the VOUT voltage is below the connecting channel’s voltage by 120mV before the new channel is allowed to connect to VOUT. This ensures little to no reverse conduction occurs during switching. An example is shown in Figure 7. V2 is initially connected to VOUT when a higher priority input supply, V1, is inserted. To ensure there is minimal droop at the output, select a low ESR capacitor large enough to ride through the dead time between channel switchover. A low ESR bulk capacitor will reduce IR drops to the output voltage while the load current is sourced from the capacitor. Use Equation (13) to calculate the load capacitor value that will ride through the OV/UV comparator delay, tpVALID(OFF), plus the breakbefore-make time, tG(SWITCHOVER). CL ( IL(MAX) • tG(SWITCHOVER) + tpVALID(OFF) VOUT _DROOP(MAX) ) (13) where IL(MAX) is the maximum load current drawn and VOUT_DROOP(MAX) is the maximum acceptable amount of voltage droop at the output. Equation (13) assumes no inrush current limiting circuitry is required. If it is required, refer to Figure 8 and use the following Equation (14) for CL. CL ≥ ( IL(MAX) • tG(SWITCHOVER) + tpVALID(OFF) + 0.79 •RS • CS VOUT _DROOP(MAX) ) (14) 4417f 15 LTC4417 Applications Information where RS and CS are component values shown in Figure 8. The selection of RS and CL involves an iterative process. Begin by assuming 0.79 • RS • CS = 10µs and choosing CL using Equation (14). See the Inrush Current and Input Voltage Droop section for more details regarding inrush current limiting circuitry, and for selecting RS. 12V WALL ADAPTER V1 + M1 IRF7324 Inrush Current and Input Voltage Droop M2 CIN1 68µF CS DS BAT54 CVS1 VS1 channel disconnects or 32ms has elapsed. Once soft-start has terminated, the gate driver quickly turns on and off external back-to-back P-channel MOSFETs as needed. A SHDN low to high transition or VOUT drooping below 0.7V reactivates soft-start. G1 RS VOUT + LTC4417 VOUT CL 47µF 4417 F08 Figure 8. Slew Rate Limiting Gate Drive Gate Driver When switching control of VOUT from a lower voltage supply to a higher voltage supply, the higher voltage supply may experience significant voltage droop due to high inrush current during a fast connection to a lower voltage output bulk capacitor with low ESR. This high inrush current may be sufficient to trigger an undesirable UV Fault. To prevent a UV fault when connecting a higher voltage input to a lower voltage output, without adding any inrush current limiting, size the input bypass capacitor large enough to provide the required inrush current, as shown by Equation (15). ⎛ V1– VOUT(INIT) ⎞ CV1 ≥ CL • ⎜ – 1⎟ V1DROOP ⎝ ⎠ When turning a channel on, the LTC4417 pulls the common gate connection (G1, G2 and G3) down with a P-channel source follower and a 2µA current source. VS1, VS2 and VS3 voltages at or above 5V will produce rising slew rates of 12V/µs and falling slew rates of 4V/µs with 10nF between the VS and G pins. VS1, VS2 and VS3 voltages lower than 5V will result in lower slew rates, see typical curves for more detail. As G1, G2 and G3 approaches the 6.2V clamp voltage, the source follower smoothly reduces its current while the 2µA hold current continues to pull G1, G2 and G3 to the final clamp voltage, back biasing the source follower. Clamping the G1, G2 and G3 voltage prevents any overvoltage stress on the gate to source oxide of the external back-to-back P-channel MOSFETs. If leakage into G1, G2 and G3 exceeds the 2µA hold current, the G1, G2 and G3 voltage will rise above the clamp voltage, where the source follower enhances to sink the excess current. When turning a channel off, the gate driver pulls the common gate to the common source with a switch having an on-resistance of 16Ω, to effect a quick turn-off. In situations where input and output capacitances cannot be chosen to set the desired maximum input voltage droop, or the peak inrush current violates the maximum Pulsed Drain Current (IDM) of the external P-channel MOSFETs, inrush current can be limited by slew rate limiting the output voltage. The gate driver can be configured to slew rate limit the output with a resistor, capacitor and Schottky diode, as shown in Figure 8. The series resistor RS and capacitor, CS, slew rate limit the output, while the Schottky diode, DS, provides a fast turn off path when G1 is pulled to VS1. To minimize inrush current at start-up, the gate driver softstarts the gate drive of the first input to connect to VOUT. The gate pin is regulated to create a constant 5V/ms rise rate on VOUT. Slew rate control is terminated when any With a desired input voltage drop, V1DROOP, and known supply resistance RSRC, the series resistance, RS, can be calculated with Equation (16), where ∆VG(SINK) is the LTC4417’s sink clamp voltage, VGS is the external (15) where VOUT(INIT) is the initial output voltage when being powered from a supply voltage less than V1, CV1 is the bypass capacitor connected to V1, CL is the output capacitor and V1DROOP is the maximum allowed voltage droop on V1. Make sure CV1 is a low ESR capacitor to minimize the voltage step across the ESR. 4417f 16 LTC4417 Applications Information P-channel’s gate to source voltage when driving the load and inrush current, CS is the slew rate capacitor and CL is the VOUT hold up capacitance. The output load current IL is neglected for simplicity. Choose CS to be at least ten times the external P-channel MOSFET’s CRSS(MAX), and CVS to be ten times CS. RS ≥ (ΔVG(SINK) – VGS ) • CL • RSRC CS • V1DROOP (16) Use Equation (17) to verify the inrush current limit is lower than the absolute maximum pulsed drain current, IDM. IINRUSH = V1DROOP RSRC (17) If the external P-channel MOSFET’s reverse transfer capacitance, CRSS, is used instead of CS, replace CS with CRSS in Equation (16), where CRSS is taken at the minimum VDS voltage, and calculate for RS. Depending on the size of CRSS, RS may be large. Care should be used to ensure gate leakages do not inadvertently turn off the channel over temperature. This is particularly true of built in Zener gatesource protected devices. Careful bench characterization is strongly recommended, as CRSS is non-linear. The preceding analysis assumes a small input inductance between the input supply voltage and the drain of the external P-channel MOSFET. If the input inductance is large, choose CV1 to be much greater than CL and replace RSRC with the ESR of CV1. When slew rate limiting the output, ensure power dissipation does not exceed the manufacturer’s SOA for the chosen external P-channel MOSFET. Refer to the Selecting External P-channel MOSFETs section. 24V WALL ADAPTER INPUT PARASITIC INDUCTANCE Transient Supply Protection The LTC4417’s abrupt switching due to OV or UV faults can create large transient overvoltage events with inductive input supplies, such as supplies connected by a long cable. At times the transient overvoltage condition can exceed twice the nominal voltage. Such events can damage external devices and the LTC4417. It is imperative that external back-to-back P-channel MOSFET devices do not exceed their single pulse avalanche energy specification (EAS) in unclamped inductive applications and input voltages to the LTC4417 never exceed the Absolute Maximum Ratings. To minimize inductive voltage spikes, use wider and/or heavier trace plating. Adding a snubber circuit will dampen input voltage spikes as discussed in Linear Application Note 88, and a transient surge suppressor at the input will clamp the voltage. Transient voltage suppressors (TVS) should be placed on any input supply pin, V1, V2 and V3, where input shorts, or reverse voltage connection can be made. If short-circuit of input sources powering VOUT are possible, transient voltage suppressors should also be placed on VOUT, as shown in Figure 9. When selecting transient voltage suppressors, ensure the reverse standoff voltage (VR) is equal to or greater than the application operating voltage, the peak pulse current (IPP) is higher than the peak transient voltage divided by the source impedance, the maximum clamping voltage (VCLAMP) at the rated IPP is less than the absolute maximum ratings of the LTC4417 and BVDSS of all the external back-to-back P-channel MOSFETs. In applications below 20V, transient voltage suppressors may not be required if the voltage spikes are lower than the BVDSS of the external P-channel MOSFETs and the LTC4417 FDD4685 M1 RSN CSN SNUBBER OR D1 SMBJ26CA OUTPUT PARASITIC INDUCTANCE FDD4685 M2 CV1 0.1µF COUT 10µF VS1 G1 LTC4417 OR + D2 SMBJ26A VOUT CL 330µF VOUT 4417 F09 Figure 9. Transient Voltage Suppression 4417f 17 LTC4417 Applications Information Absolute Maximum Ratings. If the BVDSS of the external P-channel MOSFET is momentarily exceeded, ensure the avalanche energy absorbed by the MOSFETs do not exceed the single pulse avalanche energy specification (EAS). Voltage spikes can be dampened further with a snubber. Input Supply and VOUT Shorts Input shorts can cause high current slew rates. Coupled with series parasitic inductances in the input and output paths, potentially destructive transients may appear at the input and output pins. If the short occurs on an input that is not powering VOUT, the impact to the system is benign. Back-to-back P-channel MOSFETs with their common gates connected to their common sources naturally prevent any current flow regardless of the applied voltages on either side of the drain connections, as long as the BVDSS is not exceeded. If the short occurs on an input that is powering VOUT, the issue is compounded by high conduction current and low impedance connection to the output via the back-to-back P-channel MOSFETs. Once the LTC4417 blocks the high input short current, V1, V2 and V3 may experience large negative voltage spikes while the output may experience large positive voltage spikes. To prevent damage to the LTC4417 and associated devices in the event of an input or output short, it may be necessary to protect the input pins and output pins as shown in Figure 9. Protect the input pins, V1, V2 and V3, with either unidirectional or bidirectional TVS and VOUT with a unidirectional TVS. An input and output capacitor between 0.1µF and 10µF with intentional or parasitic series resistance will aid in dampening voltage spikes; see Linear Technology’s Application Note 88 for general consideration. Due to the low impedance connection from V1, V2 and V3 to VOUT, shorts to the output will result in an input supply UV fault. If the UV threshold is high enough and the short resistive enough, the LTC4417 will disconnect the input. The fast change in current may force the output below GND, while the input will increase in voltage. If UV thresholds are set close to the minimum operating voltage of the LTC4417, it may not disconnect the input from the output before the output is dragged below the operating voltage of the LTC4417. The event would cause the LTC4417’s internal VLDO supply voltage to collapse. A 100Ω and 10nF R-C filter on VOUT will allow the LTC4417 to ride through such shorts to the input and output, as shown in Figure 10. Because VOUT is also a sense pin for the REV comparator, care should be taken to ensure the voltage drop across the resistor is low enough to not affect the reverse comparator’s threshold. If the 1µs R-C time constant does not address the issue, increase the capacitance to lengthen the time constant. M3 IRF7324 M4 M5 VS2 G2 IRF7324 VS3 LTC4417 M6 G3 VOUT RF VOUT 100Ω OUTPUT CF 10nF + CL IL 4417 F10 Figure 10. R-C Filter to Ride Through Input Shorts The initial lag due to the R-C filter on the LTC4417’s VOUT sense and supply pin will cause additional delay in sensing when a reverse condition has cleared, resulting in additional droop when transitioning from a higher voltage to a lower voltage. If the reverse voltage duration is longer than the R-C delay, the voltage differential between the output and the filtered VOUT, ∆V, can be calculated with Equation (18). IL is the output load current during the reverse voltage condition and IVOUT is current into VOUT, specified in the electrical table. ⎛I ⎞ ΔV = ⎜ L • CF – IVOUT ⎟ • RF ⎝ CL ⎠ (18) ICC Path Selection Two separate internal power rails ensure the LTC4417 is functional when one or more input supplies are present and above 2.4V as well as limit current draw from lower 4417f 18 LTC4417 priority back up input supplies. An internal diode-OR structure selects the highest voltage input supply as the source for VBLDO. If two supplies are similar in voltage and higher than the remaining input supply, the current will be equally divided between the similar voltage supplies. If all input supplies are equal in voltage, the current is divided evenly between them. To limit current consumption from lower priority backup supplies, the LTC4417 prioritizes the internal VLDO’s source supply. The highest priority source is VOUT, which powers the VLDO when VOUT is above 2.4V. If VOUT is lower than 2.4V, VLDO switches to the highest valid priority input supply, V1, V2 and V3. If no input supply is valid, VLDO is connected to VBLDO, where the diode-OR selects high12V WALL ADAPTER + M1 IRF7324 est input voltage input supply as the source. See Typical Performance Characteristics for more detail. Dual Supply Operation For instances where only two supplies are prioritized and no features of the third channel are used, ground the V3, OV3, UV3, VS3 and G3 pins of the unused channel. Alternatively, the lowest priority OV and UV comparators can be utilized for voltage monitoring when V3 and VS3 are connected to the output and G3 is left open. Figure 11 shows an example of the spare OV and UV comparators used to monitor the 5V output of the LTC3060. VALID3 acts as an open drain OV/UV window comparator output. M2 + CIN 2200µF 14.4V NiCd BATTERY M3 + IRF7324 M4 CS 6.8nF CVS1 0.1µF CVS2 1µF VOUT CL 100µF DS BAT54 LTC3060 LINEAR REGULATOR RS 2.21k 5V OUTPUT CV3 0.1µF CV2 0.1µF CV1 0.1µF VS1 R3 806k R2 39.2k R1 60.4k R6 845k R5 26.1k R4 51.1k R9 340k R8 21.5k R7 78.7k G1 VS2 G2 V1 VS3 G3 R10 1M VOUT UV1 VALID1 VALID2 OV1 VALID3 R11 1M R12 1M V1 INVALID V2 INVALID 5V OUTPUT INVALID V2 UV2 LTC4417 OV2 V3 EN SHDN HYS CAS UV3 OV3 GND 4417 F11 Figure 11. Dual Channel with Output Voltage Monitoring 4417f 19 LTC4417 Applications Information Disabling All Channels with EN and SHDN Driving EN below 1V turns off all external back-to-back P-channel MOSFETs but does not interrupt input supply monitoring or reset the 256ms timers. Driving EN above 1V enables the highest valid priority channel. This feature is essential in cascading applications. For applications where EN could be driven below ground, limit the current from EN with a 10k resistor. Forcing SHDN below 0.8V turns off all external back-to-back P-channel MOSFETs, disables all OV and UV comparators and resets all 256ms timers. VALID1, VALID2 and VALID3 release high to indicate all inputs are invalid, regardless of the input supply condition. The LTC4417 enters into a low current state, consuming only 15µA. When SHDN is released or driven above 0.8V, the LTC4417 is required to revalidate the input supplies before connecting the inputs to VOUT, as described in the Operation section. For applications where SHDN could be driven below ground, limit the current from SHDN with a 10k resistor. Cascading The LTC4417 can be cascaded to prioritize four or more input supplies. To prioritize four to six supplies, use two LTC4417s with their VOUT pins connected together and the master LTC4417’s CAS connected to the slave LTC4417’s EN as shown in Figure 12. The first LTC4417 to validate an input will soft-start the common output. Once the output is above 2.4V, power will be drawn from VOUT by the other LTC4417 regardless of its input supply conditions. When the master LTC4417 wants to connect one of its input supplies to the VOUT, it simultaneously initiates a channel turn on and pulls its CAS pin low to force the slave LTC4417 to disconnect its channels. A small amount of reverse conduction may occur in this case. The amount of cross conduction will depend on the total turn-on delay of the master channel compared with the turn-off delay of the slave channel. Care should be taken to ensure the connection between CAS and EN is as short as possible, to minimize the capacitance and hence the turn-off delay of the slave channel. When all of the inputs to the master LTC4417 are invalid, the master confirms that all its inputs are disconnected IRF7324 M1 M2 CVS1_1 0.1µF VS1 G1 VOUT LTC4417 MASTER DISABLE ALL CHANNELS SHDN MASTER EN SHDN CAS IRF7324 M3 M4 CVS1_2 0.1µF VS1 G1 VOUT LTC4417 SLAVE + VOUT CL 47µF EN SHDN CAS 4417 F12 Figure 12. Cascading Application from VOUT before releasing CAS. CAS is pulled to the internal VLDO rail with a 20µA current source, allowing the slave LTC4417 to connect its highest valid priority channel to VOUT. Confirmation that all channels are off before the slave is allowed to connect its channel to VOUT prevents cross conduction from occurring. Driving the master LTC4417’s EN low forces both master and slave to disconnect all channels from the common output and continue monitoring the input supplies. Driving the master LTC4417’s SHDN low places it in to a low current state. While in the low current state, all of its channels are disconnected and CAS is pulled high with a 20µA current source, allowing the slave LTC4417 to become the 4417f 20 LTC4417 Applications Information master and connect its highest valid priority channel to the common output. If seven, or more, input supplies are prioritized, additional LTC4417s can be added by connecting all individual VOUT pins together and connecting each LTC4417’s CAS to the next lower priority LTC4417’s EN. Design Example A 2A multiple input supply system consisting of a 12V supply with a source resistance of 20mΩ, 7.4V main lithium-ion battery, and a backup 7.4V lithium-ion battery is designed with priority sourcing from the 12V supply, as shown in Figure 13. Power is sourced from the main battery when the 12V supply is absent and the backup battery is only used when the main battery and 12V supply are not available. The ambient conditions of the system will be between 25°C and 85°C. The design limits the output voltage droop to 800mV during switchover. The load capacitor is assumed to have a minimum ESR of 50mΩ at 85°C and 80mΩ at 25°C through paralleling low ESR rated aluminum electrolytic capacitors. The input source is allowed to drop 1V. Selecting External P-Channel MOSFET The design starts with selecting a suitable 2A rated P‑channel MOSFET with desired RDS(ON). Reviewing several MOSFET options, the low 18mΩ RDS(ON), dual P-channel IRF7324 with a –20V BVDSS, is chosen for this application. The low 18mΩ RDS(ON) results in a 72mV combined drop at 25°C and 85mV drop at 85°C. Each P-channel MOSFET dissipates 72mW at 25°C and 85mW at 85°C. Inrush Current Limiting When connecting a higher voltage source to a lower voltage output, significant inrush current can occur. The magnitude of the inrush current can be calculated with Equation (19). IINRUSH = V1– VOUT(INIT) RSRC +ESR(CL )+ 2 • RDS(ON) (19) where VOUT(INIT) is the VOUT voltage when initially powered from a supply voltage less than V1, V1 is the higher voltage source, RSRC is source resistance of V1, ESR(CL) is the ESR of the load capacitor, and RDS(ON) is the on-resistance of the external back-to-back MOSFET. Given a total series resistance from input to output, the worst case inrush current will occur when V1 is running 20% high, at 14.4V, and VOUT is at its undervoltage limit of 5.6V. During this condition, a maximum inrush current of 83A will occur, as shown in Equation (20). IINRUSH = 14.4V – 5.6V = 83A 20mΩ + 50mΩ + 36mΩ (20) Because the 83A of inrush current exceeds the 71A absolute maximum pulsed drain current rating, IDM, of the IRF7324, inrush current limiting is required. Calculating the load capacitance, CL, and inrush current limiting circuitry component, RS, is an iterative process. To start, use Equation (14), with 0.79 • RS • CS initially set to 10µs. To limit the output voltage droop to the desired 800mV, reserve 200mV for initial droop due to the load current flowing in the ESR of the output capacitor. Next, choose CL to set the maximum VOUT droop to 600mV, as shown in Equation (21). 2A • (3µs + 12µs + 10µs) 600mV C = 83.3µF L CL = (21) For margin, choose the initial CL value equal to 100µF and use Equation (16) to determine RS. With an allowable 1V input voltage drop and source resistance, RSRC, of 20mΩ, the input voltage droop of 700mV is used to set the inrush current of 35A. The other terms in the equation come from the external P-channel MOSFET manufacturer’s data sheet. The transfer characteristics curve shows the gate voltage, VGS, is approximately 1.8V when driving the 35A inrush current and the capacitance verses drain-to-source voltage curve shows the maximum CRSS is approximately 600pF. CS is set to be greater than ten times CRSS, or 6.8nF. To ensure the designed inrush current is lower than the absolute maximum pulse drain current rating, IDM, calculate RS using the maximum value for ∆VG(SINK) and CL, and the minimum value for CS. For aluminum 4417f 21 LTC4417 Applications Information IRF7324 12V SUPPLY M1 + M2 CS 6.8nF CIN 2700µF 7.4V Li-Ion BATTERY (2 × 3.7V) IRF7324 M3 M4 + 7.4V Li-Ion BATTERY (2 × 3.7V) DS BAT54 RS 2.21k M5 + CVS1 68nF CV3 0.1µF CV2 0.1µF CV1 0.1µF VS1 R3 806k R2 41.2k R1 60.4k R6 768k CVS3 0.1µF G1 VS2 G2 + VS3 V1 140k G3 R10 1M UV1 OV1 VALID1 VALID2 VALID3 CL 100µF VOUT VOUT V2 R11 1M R12 1M V1 INVALID V2 INVALID V3 INVALID LTC4417 UV2 R5 53.6k OV2 R4 113k R9 768k CVS2 0.1µF IRF7324 M6 V3 140k EN SHDN HYS CAS UV3 R8 53.6k OV3 R7 113k RHYS 255k 1% GND 4417 F13 Figure 13. Industrial Hand Held Computer electrolytic capacitors, add 20% to CL and for ceramic NP0 CS capacitors subtract 5%. (6V – 1.8V) • 120µF • 20mΩ 6.5nF • 700mV RS = 2.22kΩ RS = (22) With RS and CS known, the desired load capacitance with inrush current limiting is checked with Equation (14) as shown in Equation (23). Because the required load capacitance of 90µF is lower than the chosen load capacitor of 100µF, the initial choice of 100µF is suitable. The standard value of 2.21kΩ is chosen for RS and CVS1 is chosen to be ten times CS or 68nF. Although 1.8V is a typical value for VGS, there is sufficient margin – even if VGS = 0V, the resulting IDM is lower than the 71A rating. 2A • (3µs + 12µs + 0.79 • 2.21kΩ • 6.8nF) 600mV CL ≥ 90µF CL ≥ (23) 4417f 22 LTC4417 Applications Information Significant power is dissipated during the channel transition time. The SOA of the P-channel MOSFET should be checked to make sure their SOA is not violated. Worst case slew rate limited channel transition time would occur when the lithium-ion batteries are running low at 5.6V, and the supply connects while running 20% high, at 14.4V. This results in a time of 25µs, as shown in Equation (24). (14.4V – 5.6V) • 100µF 35A dt = 25µs dt = (24) The IRF7324 thermal response curve at 25µs shows ZθJA to be approximately 0.18 for a single pulse. The ZθJA of 0.18 results in a maximum transient power dissipation of 694W at 25°C and 361W at 85°C. The external P-channel MOSFETs will dissipate no more than 8.8V • 37A = 325W during this period, below the available 361W at 85°C. The initial soft-start period will also force the external back-to-back MOSFETs to dissipate significant power. To check the SOA during this period, start with Equation (9). tSTARTUP (ms) = Assuming the 12V source has a tolerance of ±20%, the input source has an operational undervoltage limit of 9.6V and an overvoltage limit of 14.4V. Ideally the UV1, UV2 and UV3 and OV1, OV2 and OV3 thresholds would be set to these limits. However, since the actual threshold varies by 1.5% and resistor tolerances are 1%, OV and UV limits must be adjusted to ±26% or 8.9V and 15.1V. Further, instead of using the internal fixed 30mV, a UV hysteresis of 200mV is set using an external hysteresis current of 250nA. The design process starts with setting RHYS using Equation (1). (25) R3 = Desired Hysteresis 200mV = = 810kΩ IOVUV(HYS) 247nA (29) With R3 set, the remaining resistance can be determined with R1,2 = = (26) The worst case soft-start power dissipation from Equation (11) is: PSS(W) = 6W (28) Now set the UV hysteresis value using R3 IMAXCAP = 100µF • 5[V/ms] PSS(W) = 12V • 500mA 63mV = 252kΩ 250nA The nearest standard value is 255kΩ. IMAXCAP current of 500mA is calculated using Equation (10). IMAXCAP = 500mA RHYS = The nearest standard value is 806kΩ. 12V 5[V/ms] tSTARTUP (ms) = 2.4ms Setting Operational Range (27) The soft-start power dissipation of 6W is well below the calculated transient power dissipation (PDM) of 79.4W at a TC of 25°C. An ambient temperature, TA, of 85°C results in a PDM of 41.3W, indicating it is sufficient to handle the 2.4ms transient 6W power dissipation. A graphical check with the manufacturer’s SOA curves confirms sufficient operating margin. R3 UVTH(FALLING) – VOVUV(THR) 806kΩ = 102kΩ 8.9V – 1V (30) R1 is R1= R1,2+R3 102kΩ + 806kΩ = = 60.1kΩ (31) OVTH(RISING) 15.1V The nearest 1% standard value is: 60.4kΩ. R2 is R2 = R1,2 – R3 = 102kΩ – 60.4kΩ = 41.6kΩ(32) The nearest 1% standard value is 41.2kΩ. 4417f 23 LTC4417 Applications Information Because this is a single resistive string R2, R3, and IOV_UV(HYS) sets the hysteresis voltage with Equation (30) OVHYS = (R2 + R3) • IOVUV(HYS) = (33) (41.2kΩ + 806kΩ) • 247nA = 209mV This results in an OV threshold of 15.0V and UV threshold of 8.9V. With hysteresis, the OVHYS threshold is 14.8V and the UVHYS threshold is 9.1V. For the desired OV and UV 6% accuracy, 1% resistors used in this example are acceptable. Values for R4 to R6 and R7 to R9 for V2 and V3 are similarly calculated. Layout Considerations Sheet resistance of 1oz copper is ~530µΩ per square. Although small, resistances add up quickly in high current applications. Keep high current traces short with minimum trace widths of 0.02" per amp to ensure traces stay at a reasonable temperatures. Using 0.03" per amp or wider is recommended. To improve noise immunity, place OV/ UV resistive dividers as close to the LTC4417 as possible. Transient voltage suppressors should be located as close to the input connector as possible with short wide traces to GND. Figure 14 shows a partial layout that addresses these issues. TO V3 INPUT SUPPLY D FROM V1 INPUT SOURCE D 0.03" PER AMPERE TRANSIENT VOLTAGE SUPPRESSOR R3 R6 R5 R9 R4 R8 R7 GND G S FROM V2 INPUT SOURCE R2 R1 D G S S G G S TO OUTPUT D 1 EN V1 24 CV1 2 SHDN V2 23 CV2 3 HYS V3 22 CV3 4 UV1 VS1 21 5 OV1 G1 20 6 UV2 VS2 19 7 OV2 G2 18 8 UV3 VS3 17 9 OV3 G3 16 10 VALID1 VOUT 15 11 VALID2 CAS 14 12 VALID3 GND 13 TO V3 COMMON SOURCE TO V3 COMMON GATE NOT TO SCALE GND Figure 14. Recommended PCB Layout 4417f 24 LTC4417 Typical Applications 12V System Using Swappable and Backup Batteries 12V WALL ADAPTER + M1 IRF7324 M2 CIN1 2200µF 12V NiCd BATTERY IRF7324 M3 + M4 CS 6.8nF RS 2.21k DS BAT54 11.1V Li-Ion BATTERY (3 × 3.7V) M5 + CVS1 0.1µF CV3 0.1µF CV2 0.1µF CV1 0.1µF R3 1.02M R2 48.7k R1 76.8k R6 1.02M R5 36.5k R4 76.8k R9 1.0M R8 40.2k R7 90.9k + VS2 G2 V1 VS3 G3 VOUT VOUT R10 1M UV1 OV1 VALID1 VALID2 VALID3 V2 UV2 CL 100µF CVS3 0.1µF CVS2 1µF VS1 G1 IRF7324 M6 R11 1M R12 1M V1 INVALID V2 INVALID V3 INVALID LTC4417 OV2 V3 EN SHDN HYS CAS UV3 OV3 RHYS 316k GND 4417 TA02 4417f 25 LTC4417 Typical Applications 18V System with Reverse Voltage Protection 18V WALL ADAPTER FDS4685 M1 FDS4685 M2 CIN1 2200µF D1 SMBJ26CA D4 SMBJ26A CVS1 0.1µF 11.1V Li-Ion BATTERY + VOUT FDS4685 M3 FDS4685 M4 D2 SMBJ26CA CVS2 0.1µF 12V LEAD-ACID BATTERY + FDS4685 M5 FDS4685 M6 CL 100µF D3 SMBJ26CA CVS3 0.1µF CV1 0.1µF VS1 CV3 0.1µF CV2 0.1µF R3 1.02M R2 11.8k R1 54.9k R6 768k R5 90.9k R4 75k R9 698k R8 16.9k R7 49.9k G1 VS2 G2 V1 VS3 G3 VOUT UV1 OV1 VALID1 VALID2 VALID3 V2 UV2 LTC4417 OV2 V3 EN SHDN HYS CAS UV3 OV3 GND 4417 TA03 4417f 26 CV2 35V TANTALUM CV1 470µF 12V SYSTEM SUPPLY + R7 41.2k R8 1.02M R4 33.2k R5 127k R6 806k R1 66.5k R2 15.8k R3 806k VS1 OV3 UV3 V3 OV2 UV2 V2 OV1 UV1 V1 CVS1 1µF FDS4685 M1 DS BAT54 G1 GND LTC4417 VS2 CVS2 0.1µF G2 FDS4685 M4 CS 6.8nF FDS4685 M3 RS 1.43k FDS4685 M2 VOUT G3 4417 TA04 EN SHDN HYS CAS VALID3 VALID2 VALID1 VS3 L1A 33µH C11 10µF C10 10µF R23 1Ω R22 25k R21 536k C8 10nF C7 4.7µF VC ISN ISP PWMOUT FB SW INTVCC GND LT3956 VIN RT SS VREF CTRL PWM VMODE EN/UVLO C3 330pF R20 82.5k R18 100k LTC3851 GND ITH FREQ/PLLFLTR TK/SS RUN SENSE– SENSE+ VFB BG SW BOOST TG PGO0D PLLIN/MODE VIN INTVCC C16 0.22µF C4 0.1µF R9 124k SUPERCAP NOT FULLY CHARGED INVALID SUPERCAP INVALID 12V SYSTEM R24 28.7k R25 14k R26 10k R19 13k Q2 STD30NFL06L Q1 STD30NFL06L LTC3851-1.5V/15A BUCK PLEASE REFER TO THE LTC3851 DATA SHEET FOR SPECIFIC APPLICATION INFORMATION R14 15k C1 2200pF C17 0.1µF C9 0.1µF C5 4.7µF D1 CMDSH2-3 LT3956 SUPERCAP CHARGER WITH INPUT CURRENT LIMIT PLEASE REFER TO THE LT3956 DATA SHEET FOR SPECIFIC APPLICATION INFORMATION L1B 33µH D2 MBRS360 28V Transient Hold-Up Supply for Solid State Drives (SSD) R17 10k R32 1M L2 0.68µH R31 59k D3 MBRS340 R27 30.1k Q3 BC817-25 R28 2k R29 40.2k R30 1M R11 1M C15 47pF CL 100µF VOUT R12 1M R16 48.7k R15 255k + R10 1M R13 100k 5V, 15A OUTPUT C2 330µF ×2 M5 LTC4417 Typical Applications 4417f 27 LTC4417 Typical Applications Selecting from USB, FireWire, and Li-Ion Battery Power Sources 4.35V TO 5.25V USB 8V TO 30V FireWire IEEE1394 FDS4685 FDS4685 M1 M2 VOUT CL 47µF CIN1 10µF FDS4685 M3 FDS4685 M4 CIN2 22µF CS 6.8nF CVS1 0.1µF CVS2 1µF 7.4V Li-Ion BATTERY RS 1k DS BAT54 + CV1 0.1µF CV2 0.1µF R2 24.9k CV3 0.1µF R1 75k R6 576k R5 78.7k R4 20.5k R9 931k R8 63.4k R7 137k FDS4685 M6 CVS3 0.1µF VS1 R3 309k FDS4685 M5 G1 VS2 G2 V1 VS3 G3 VOUT R10 1M UV1 OV1 VALID1 VALID2 VALID3 V2 UV2 R11 1M R12 1M USB INVALID FireWire INVALID Li_Ion INVALID LTC4417 OV2 V3 EN SHDN HYS CAS UV3 OV3 GND 4417 TA05 4417f 28 LTC4417 Typical Applications Wall Adapter and USB Input with Battery Backup 5V WALL ADAPTER + Si4931DY M1 M2 + CIN1 1000µF 4.35V TO 5.25V USB VOUT CL 47µF Si4931DY M3 M4 CIN2 10µF CV1 0.1µF 4 × AA BATTERY Si4931DY M5 M6 + CVS1 0.1µF CV2 0.1µF VS1 R3 412k R2 37.4k CV3 0.1µF R1 95.3k R4 412k R5 33.2k R6 100k R9 432k R11 562k R8 80.6k R7 86.6k CVS2 0.1µF R10 52.3k G1 CVS3 0.1µF VS2 G2 V1 VS3 G3 VOUT R13 1M UV1 OV1 VALID1 VALID2 VALID3 V2 UV2 R12 1M R14 1M WALL ADAPTER INVALID USB INVALID 4 × AA BATTERY INVALID LTC4417 OV2 V3 EN SHDN HYS CAS UV3 OV3 RHYS 249k GND 4417 TA06 4417f 29 LTC4417 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. GN Package 24-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641 Rev B) .337 – .344* (8.560 – 8.738) 24 23 22 21 20 19 18 17 16 15 1413 .045 ±.005 .229 – .244 (5.817 – 6.198) .254 MIN .033 (0.838) REF .150 – .157** (3.810 – 3.988) .150 – .165 1 .0165 ±.0015 2 3 4 5 6 7 8 9 10 11 12 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT .015 ±.004 × 45° (0.38 ±0.10) .0075 – .0098 (0.19 – 0.25) .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN24 REV B 0212 3. DRAWING NOT TO SCALE 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 4417f 30 LTC4417 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697 Rev B) 0.70 ±0.05 4.50 ±0.05 2.45 ±0.05 3.10 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 ±0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 0.75 ±0.05 PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 23 24 PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 1 2 2.45 ±0.10 (4-SIDES) (UF24) QFN 0105 REV B 0.200 REF 0.00 – 0.05 0.25 ±0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4417f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC4417 Typical Application Dual Channel LTC4417 Application with Output Voltage Monitoring Using Third Channel 12V WALL ADAPTER + IRF7324 M1 + CIN 2200µF IRF7324 M3 + CV2 0.1µF CV1 0.1µF R3 806k R2 39.2k R1 60.4k R6 845k R5 26.1k R4 51.1k CVS2 1µF VS1 G1 DS BAT54 VS2 C1 10nF OV1 GND R10 1M R11 1M R12 1M VALID1 V1 INVALID VALID2 V2 INVALID VALID3 5V OUTPUT INVALID V2 LTC4417 UV2 OV2 EN SHDN HYS CAS OV3 R7 84.5k SHDN 5V OUTPUT G3 VOUT UV3 R8 15.4k VS3 V1 UV1 REF/BYP CL 100µF RS 2.21k G2 V3 R9 357k ADJ M4 CS 6.8nF CVS1 0.1µF OUT IN LT3060-5 C2 10nF 10µF 14.4V NiCd BATTERY CV3 0.1µF VOUT M2 GND 4417 TA07 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC4411 2.6A Low Loss Ideal Diode in ThinSOT™ Internal 2.6A P-channel, 2.6V to 5.5V, 40µA IQ, SOT-23 Package LTC4412HV 36V Low Loss PowerPath Controller in ThinSOT 2.5V to 36V, P-channel, 11µA IQ, SOT-23 Package LTC4415 Dual 4A Ideal Diodes with Adjustable Current Limit Dual Internal P-channel, 1.7V to 5.5V, MSOP-16 and DFN-16 Packages LTC4416 36V Low Loss Dual PowerPath Controller for Large PFETs 3.6V to 36V, 35µA IQ per Supply, MSOP-10 Package LTC4355 Positive High Voltage Ideal Diode-OR with Supply and Fuse Monitors Dual N-channel, 9V to 80V, SO-16, MSOP-16 and DFN-14 Packages LTC4359 Ideal Diode Controller with Reverse Input Protection N-channel, 4V to 80V, MSOP-8 and DFN-6 Packages LTC2952 Pushbutton PowerPath Controller with Supervisor 2.7V to 28V, On/Off Timers, ±8kV HBM ESD, TSSOP-20 and QFN-20 Packages 4417f 32 Linear Technology Corporation LT 1112 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2012