MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14051B Analog MC14052B Multiplexers/Demultiplexers The MC14051B, MC14052B, and MC14053B analog multiplexers are digitally–controlled analog switches. The MC14051B effectively implements an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a Triple SPDT. All three devices feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved. • • • • • • • • • MC14053B L SUFFIX CERAMIC CASE 620 Triple Diode Protection on Control Inputs Switch Function is Break Before Make Supply Voltage Range = 3.0 Vdc to 18 Vdc Analog Voltage Range (VDD – VEE) = 3.0 to 18 V Note: VEE must be VSS Linearized Transfer Characteristics Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical Pin–for–Pin Replacement for CD4051, CD4052, and CD4053 For 4PDT Switch, See MC14551B For Lower RON, Use the HC4051, HC4052, or HC4053 High–Speed CMOS Devices P SUFFIX PLASTIC CASE 648 v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* Symbol VDD Vin, Vout Iin Parameter Value Unit – 0.5 to + 18.0 V – 0.5 to VDD + 0.5 V ± 10 mA ± 25 mA 500 mW – 65 to + 150 _C DC Supply Voltage (Referenced to VEE, VSS ≥ VEE) Input or Output Voltage (DC or Transient) (Referenced to VSS for Control Inputs and VEE for Switch I/O) Input Current (DC or Transient), per Control Pin Isw PD Switch Through Current Tstg Storage Temperature Power Dissipation. per Package† D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:“P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C MC14051B 8–Channel Analog Multiplexer/Demultiplexer CONTROLS SWITCHES IN/OUT 6 11 10 9 13 14 15 12 1 5 2 4 INHIBIT A B C X0 X1 X 3 X2 COMMON X3 OUT/IN X4 X5 X6 X7 VDD = PIN 16 VSS = PIN 8 VEE = PIN 7 MC14052B Dual 4–Channel Analog Multiplexer/Demultiplexer CONTROLS SWITCHES IN/OUT 6 10 9 12 14 15 11 1 5 2 4 INHIBIT A X B X0 X1 X2 X3 Y0 Y Y1 Y2 Y3 VDD = PIN 16 VSS = PIN 8 VEE = PIN 7 CONTROLS 13 COMMONS OUT/IN 3 MC14053B Triple 2–Channel Analog Multiplexer/Demultiplexer SWITCHES IN/OUT 6 11 10 9 12 13 2 1 5 3 INHIBIT X A B C X0 Y X1 Y0 Y1 Z Z0 Z1 14 15 COMMONS OUT/IN 4 VDD = PIN 16 VSS = PIN 8 VEE = PIN 7 Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS. REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14051B MC14052B MC14053B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS – 55_C Characteristic Symbol VDD Test Conditions 25_C 125_C Min Max Min Typ # Max Min Max Unit SUPPLY REQUIREMENTS (Voltages Referenced to VEE) Power Supply Voltage Range VDD — VDD – 3.0 ≥ VSS ≥ VEE 3.0 18 3.0 — 18 3.0 18 V Quiescent Current Per Package IDD 5.0 10 15 Control Inputs: Vin = VSS or VDD, Switch I/O: VEE VI/O VDD, and ∆Vswitch 500 mV** — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µA ID(AV) 5.0 10 15 TA = 25_C only (The channel component, (Vin – Vout)/Ron, is not included.) Total Supply Current (Dynamic Plus Quiescent, Per Package µA (0.07 µA/kHz) f + IDD (0.20 µA/kHz) f + IDD (0.36 µA/kHz) f + IDD Typical CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS) Low–Level Input Voltage VIL 5.0 10 15 Ron = per spec, Ioff = per spec — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 V High–Level Input Voltage VIH 5.0 10 15 Ron = per spec, Ioff = per spec 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — V Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — 1.0 µA Input Capacitance Cin — — — — 5.0 7.5 — — pF SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE) Recommended Peak–to–Peak Voltage Into or Out of the Switch VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD VPP Recommended Static or Dynamic Voltage Across the Switch** (Figure 5) ∆Vswitch — Channel On 0 600 0 — 600 0 300 mV Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 — — — µV ON Resistance Ron 5.0 10 15 ∆Vswitch 500 mV**, Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch) — — — 800 400 220 — — — 250 120 80 1050 500 280 — — — 1200 520 300 Ω ∆Ron 5.0 10 15 — — — 70 50 45 — — — 25 10 10 70 50 45 — — — 135 95 65 Ω Ioff 15 Vin = VIL or VIH (Control) Channel to Channel or Any One Channel — ± 100 — ± 0.05 ± 100 — ± 1000 nA Capacitance, Switch I/O CI/O — Inhibit = VDD — — — 10 — — — pF Capacitance, Common O/I CO/I — Inhibit = VDD (MC14051B) (MC14052B) (MC14053B) — — — — — — — — — 60 32 17 — — — — — — — — — Pins Not Adjacent Pins Adjacent — — — — — — 0.15 0.47 — — — — — — ∆ON Resistance Between Any Two Channels in the Same Package Off–Channel Leakage Current (Figure 10) Capacitance, Feedthrough (Channel Off) CI/O — — pF pF #Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance. * For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) MC14051B MC14052B MC14053B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ v ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C) (VEE Characteristic Propagation Delay Times (Figure 6) Switch Input to Switch Output (RL = 10 kΩ) MC14051 tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 11 ns tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns MC14052 tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns VSS unless otherwise indicated) VDD – VEE Typ # Vdc All Types Symbol Unit ns 5.0 10 15 35 15 12 90 40 30 5.0 10 15 30 12 10 75 30 25 5.0 10 15 25 8.0 6.0 65 20 15 ns MC14053 tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns Inhibit to Output (RL = 10 kΩ, VEE = VSS) Output “1” or “0” to High Impedance, or High Impedance to “1” or “0” Level MC14051B Max tPLH, tPHL ns tPHZ, tPLZ, tPZH, tPZL ns 5.0 10 15 350 170 140 700 340 280 MC14052B 5.0 10 15 300 155 125 600 310 250 ns MC14053B 5.0 10 15 275 140 110 550 280 220 ns 5.0 10 15 360 160 120 720 320 240 MC14052B 5.0 10 15 325 130 90 650 260 180 ns MC14053B 5.0 10 15 300 120 80 600 240 160 ns — 10 0.07 — % BW 10 17 — MHz — 10 – 50 — dB Channel Separation (Figure 8) (RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, fin = 3.0 MHz — 10 – 50 — dB Crosstalk, Control Input to Common O/I (Figure 9) (R1 = 1 kΩ, RL = 10 kΩ Control tTLH = tTHL = 20 ns, Inhibit = VSS) — 10 75 — mV Control Input to Output (RL = 10 kΩ, VEE = VSS) MC14051B Second Harmonic Distortion (RL = 10KΩ, f = 1 kHz) Vin = 5 VPP Bandwidth (Figure 7) (RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, CL = 50pF 20 Log (Vout/Vin) = – 3 dB) Off Channel Feedthrough Attenuation (Figure 7) RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p fin = 4.5 MHz — MC14051B fin = 30 MHz — MC14052B fin = 55 MHz — MC14053B tPLH, tPHL ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs must be left open. MOTOROLA CMOS LOGIC DATA MC14051B MC14052B MC14053B 3 VDD VDD V DD OUT/IN IN/OUT VEE VDD LEVEL CONVERTED CONTROL IN/OUT OUT/IN CONTROL VEE Figure 1. Switch Circuit Schematic TRUTH TABLE 16 Control Inputs ON Switches Select Inhibit C* B A MC14051B 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 X0 X1 X2 X3 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 X4 X5 X6 X7 1 x x x None MC14052B Y0 Y1 Y2 Y3 X0 X1 X2 X3 MC14053B Z0 Z0 Z0 Z0 Y0 Y0 Y1 Y1 X0 X1 X0 X1 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 X0 X1 X0 X1 None None * Not applicable for MC14052 x = Don’t Care 16 INH A B C 6 11 10 9 VDD 8 X0 13 X1 14 VSS 7 VEE X2 15 X3 12 3 X X4 1 X5 5 X6 2 X7 4 Figure 2. MC14051B Functional Diagram VDD 16 INH 6 BINARY TO 1–OF–4 DECODER WITH INHIBIT LEVEL CONVERTER A 10 B 9 8 X0 12 X1 14 VSS 7 BINARY TO 1–OF–8 DECODER WITH INHIBIT LEVEL CONVERTER INH A B C VEE X2 15 X3 11 Y0 1 Y1 5 Y2 2 Y3 4 Figure 3. MC14052B Functional Diagram MC14051B MC14052B MC14053B 4 6 11 10 9 BINARY TO 1–OF–2 DECODER WITH INHIBIT LEVEL CONVERTER 8 13 X VDD VSS 7 VEE X0 12 14 X X1 13 Y0 2 3 Y 15 Y Y1 1 Z0 5 4 Z Z1 3 Figure 4. MC14053B Functional Diagram MOTOROLA CMOS LOGIC DATA TEST CIRCUITS ON SWITCH CONTROL SECTION OF IC A B C PULSE GENERATOR Vout LOAD V CL RL INH SOURCE VDD VEE Figure 5. ∆V Across Switch VEE VDD Figure 6. Propagation Delay Times, Control and Inhibit to Output A, B, and C inputs used to turn ON or OFF the switch under test. RL A B C VSS Vout INH RL A B C ON INH OFF CL = 50 pF Vout Vin RL VDD – VEE 2 VDD – VEE 2 Figure 7. Bandwidth and Off–Channel Feedthrough Attenuation CL = 50 pF Vin Figure 8. Channel Separation (Adjacent Channels Used For Setup) OFF CHANNEL UNDER TEST A B C Vout RL INH CONTROL SECTION OF IC VDD VEE OTHER CHANNEL(S) VEE VDD CL = 50 pF R1 COMMON VEE VDD Figure 9. Crosstalk, Control Input to Common O/I Figure 10. Off Channel Leakage NOTE: See also Figures 7 and 8 on Page 6–51. MOTOROLA CMOS LOGIC DATA MC14051B MC14052B MC14053B 5 VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k 1 kΩ RANGE VDD X–Y PLOTTER VEE = VSS Figure 11. Channel Resistance (RON) Test Circuit 300 300 250 200 150 TA = 125°C 100 25°C – 55°C 50 0 – 10 RON , “ON” RESISTANCE (OHMS) R ON , “ON” RESISTANCE (OHMS) 350 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 250 200 150 25°C – 55°C 50 0 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 12. VDD = 7.5 V, VEE = – 7.5 V Figure 13. VDD = 5.0 V, VEE = – 5.0 V 700 350 600 300 500 400 300 TA = 125°C 200 25°C 100 0 – 10 TA = 125°C 100 10 R ON , “ON” RESISTANCE (OHMS) R ON , “ON” RESISTANCE (OHMS) TYPICAL RESISTANCE CHARACTERISTICS 350 – 55°C – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 TA = 25°C 250 VDD = 2.5 V 200 150 5.0 V 100 7.5 V 50 0 – 10 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 14. VDD = 2.5 V, VEE = – 2.5 V Figure 15. Comparison at 25°C, VDD = – VEE 10 PIN ASSIGMENT MC14051B MC14052B MC14053B X4 1 16 VDD Y0 1 16 VDD Y1 1 16 VDD X6 2 15 X2 Y2 2 15 X2 Y0 2 15 Y X 3 14 X1 Y 3 14 X1 Z1 3 14 X X7 4 13 X0 Y3 4 13 X Z 4 13 X1 X5 5 12 X3 Y1 5 12 X0 Z0 5 12 X0 INH 6 11 A INH 6 11 X3 INH 6 11 A VEE 7 10 B VEE 7 10 A VEE 7 10 B VSS 8 9 C VSS 8 9 B VSS 8 9 C MC14051B MC14052B MC14053B 6 MOTOROLA CMOS LOGIC DATA APPLICATIONS INFORMATION above VDD and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between V DD and VEE is 18.0 V. Most parameters are specified up to 15 V which is the recommended maximum difference between V DD and V EE. Balanced supplies are not required. However, V SS must be greater than or equal to V EE. For example, V DD = + 10 V, V SS = + 5 V, and V EE – 3 V is acceptable. See the Table below. Figure A illustrates use of the on–chip level converter detailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control signal is used to directly control a 9 Vp–p analog signal. The digital control logic levels are determined by VDD and V SS. The V DD voltage is the logic high voltage; the V SS voltage is logic low. For the example, V DD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by V DD and V EE. The V DD voltage determines the maximum recommended peak above V SS. The V EE voltage determines the maximum swing below V SS. For the example, V DD – VSS = 5 V maximum swing above V SS ; V SS – V EE = 5 V maximum swing below VSS. The example shows a ± 4.5 V signal which allows a 1/2 volt margin at each peak. If voltage transients +5 V –5 V VDD VSS VEE + 4.5 V 9 Vp–p ANALOG SIGNAL SWITCH I/O MC14051B MC14052B MC14053B +5 V EXTERNAL CMOS DIGITAL CIRCUITRY 0–TO–5 V DIGITAL COMMON O/I 9 Vp–p ANALOG SIGNAL GND – 4.5 V INHIBIT, A, B, C CONTROL SIGNALS Figure A. Application Example VDD VDD DX DX ANALOG I/O COMMON O/I DX DX ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VEE VEE Figure B. External Germanium or Schottky Clipping Diodes POSSIBLE SUPPLY CONNECTIONS VDD In Volts VSS In Volts VEE In Volts Control Inputs Logic High/Logic Low In Volts +8 0 –8 + 8/0 + 8 to – 8 = 16 Vp–p +5 0 – 12 + 5/0 + 5 to – 12 = 17 Vp–p +5 0 0 + 5/0 + 5 to 0 = 5 Vp–p +5 0 –5 + 5/0 + 5 to – 5 = 10 Vp–p + 10 +5 –5 + 10/ + 5 + 10 to – 5 = 15 Vp–p MOTOROLA CMOS LOGIC DATA Maximum Analog Signal Range In Volts MC14051B MC14052B MC14053B 7 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) MC14051B MC14052B MC14053B 8 M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC DATA ◊ *MC14051B/D* MC14051B MC14052B MC14053B MC14051B/D 9