SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 620 The MC14529B analog data selector is a dual 4–channel or single 8–channel device depending on the input coding. The device is suitable for digital as well as analog application, including various one–of–four and one–of–eight data selector functions. Since the device has bidirectional analog characteristics it can also be used as a dual binary to 1–of–4 or a binary to 1–of–8 decoder. • Data Paths Are Bidirectional • 3–State Outputs • Linear “On” Resistance • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load over the Rated Temperature Range. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C 260 _C TL Lead Temperature (8–Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C TRUTH TABLE (X = Don’t Care) STX 1 1 1 1 STY 1 1 1 1 B A Z W 0 0 1 1 0 1 0 1 X0 X1 X2 X3 Y0 Y1 Y2 Y3 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 X0 X1 X2 X3 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 Y0 Y1 Y2 Y3 0 0 X X High Impedance Dual 4–Channel Mode 2 Outputs Single 8–Channel Mode 1 Output (Z and W tied together) P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. BLOCK DIAGRAM 3–STATE OUTPUT ENABLE STROBE X 1 6 7 2 3 4 5 A B X0 X1 X2 X3 14 13 12 11 Y0 Y1 Y2 Y3 Z 9 W 10 STROBE Y 15 VDD = PIN 16 VSS = PIN 8 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14529B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS – 55_C Characteristic Symbol VDD Test Conditions 25_C 125_C Min Max Min Typ # Max Min Max Unit SUPPLY REQUIREMENTS (Voltages Referenced to VEE) Power Supply Voltage Range VDD — VDD – 3.0 ≥ VSS ≥ VEE 3.0 18 3.0 — 18 3.0 18 V Quiescent Current Per Package IDD 5.0 10 15 Control Inputs: Vin = VSS or VDD, Switch I/O: VSS VI/O VDD, and ∆Vswitch 500 mV** — — — 1.0 1.0 2.0 — — — 0.005 0.010 0.015 1.0 1.0 2.0 — — — 60 60 120 µA Total Supply Current (Dynamic Plus Quiescent, Per Package ID(AV) 5.0 10 15 v v v TA = 25_C only (The channel component, (Vin – Vout) / Ron, is not included.) Typical (0.07 µA/kHz) f + IDD (0.20 µA/kHz) f + IDD (0.36 µA/kHz) f + IDD µA CONTROL INPUTS — INHIBIT, A, B (Voltages Referenced to VSS) Low–Level Input Voltage VIL 5.0 10 15 Ron = per spec, Ioff = per spec — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 V High–Level Input Voltage VIH 5.0 10 15 Ron = per spec, Ioff = per spec 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — V Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µA Input Capacitance Cin — — — — 5.0 7.5 — — pF SWITCHES IN/OUT AND COMMONS OUT/IN — W, Z (Voltages Referenced to VEE) Recommended Peak–to– Peak Voltage Into or Out of the Switch VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD Vp–p Recommended Static or Dynamic Voltage Across the Switch** (Figure 5) ∆Vswitch — Channel On 0 600 0 — 600 0 300 mV Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 — — — µV ON Resistance Ron 10 15 ∆Vswitch 500 mV**, Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch) — — 400 240 — — 120 80 480 270 — — 560 350 Ω ∆Ron 10 15 — — — — — — 15 10 — — — — — — Ω Ioff 15 Vin = VIL or VIH (Control) Channel to Channel or Any One Channel ± 100 — ± 0.05 ± 100 — ± 1000 nA Capacitance, Switch I/O CI/O — Inhibit = VDD — — — 8.0 — — — pF Capacitance, Common O/I CO/I — Inhibit = VDD — — — 20 — — — pF Capacitance, Feedthrough (Channel Off) CI/O — — Pins Not Adjacent Pins Adjacent — — — — — — 0.15 0.47 — — — — — — pF ∆ON Resistance Between Any Two Channels in the Same Package Off–Channel Leakage Current (Figure 10) v #Data labelled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance. ** For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) MC14529B 2 MOTOROLA CMOS LOGIC DATA SWTCHING CHARACTERISTICS (TA = 25_C) Characteristic Figure Symbol VSS VDD Min Typ # Max Unit Vin to Vout Propagation Delay Time (CL = 50 pF, RL = 1.0 kΩ) 7 tPLH, tPHL 0.0 5.0 10 15 — — — 20 10 8.0 40 20 15 ns Propagation Delay Time, Control to Output, Vin = VDD or VSS (CL = 50 pF, RL = 1.0 kΩ) 8 tPLZ, tPZL, tPHZ, tPZH 0.0 5.0 10 15 — — — 140 70 50 400 160 120 ns Crosstalk, Control to Output (CL = 50 pF, RL = 1.0 kΩ Rout = 10 kΩ) 9 — 0.0 5.0 10 15 — — — 5.0 5.0 5.0 — mV Control Input Pulse Frequency (CL = 50 pF, RL = 1.0 kΩ) 10 fin 0.0 5.0 10 15 — — — 5.0 10 12 2.5 6.2 8.3 MHz 11, 12 — 0.0 5.0 10 15 — — — 24 25 30 — — — nV/ √cycle 5.0 10 15 — — — 12 12 15 — — — – 5.0 5.0 — 0.36 — – 5.0 – 5.0 – 7.5 – 7.5 5.0 5.0 7.5 7.5 — — — — ± 0.001 ± 0.001 ± 0.0015 ± 0.0015 ± 125 ± 125 ± 250 ± 250 – 5.0 5.0 Noise Voltage (f = 100 Hz) Sine Wave Distortion (Vin = 1.77 Vdc RMS Centered @ 0.0 Vdc, RL = 10 kΩ, f = 1.0 kHz) — — Off–Channel Leakage Current (Vin = + 5.0 Vdc, Vout = – 5.0 Vdc) (Vin = – 5.0 Vdc, Vout = + 5.0 Vdc) (Vin = + 7.5 Vdc, Vout = – 7.5 Vdc) (Vin = – 7.5 Vdc, Vout = + 7.5 Vdc) — Ioff Insertion Loss (Vin = 1.77 Vdc RMS centered @ 0.0 Vdc, f = 1.0 MHz) Iloss = 20 Log10 (Vout / Vin) (RL = 1.0 kΩ) (RL = 10 kΩ) (RL = 100 kΩ) (RL = 1.0 MΩ) 13 Bandwidth (– 3 dB) (Vin = 1.77 Vdc RMS centered @ 0.0 Vdc) (RL = 1.0 kΩ) (RL = 10 kΩ) (RL = 100 kΩ) (RL = 1.0 MΩ) — Feedthrough and Crosstalk 20 Log10 (Vout / Vin) = – 50 dB (RL = 1.0 kΩ) (RL = 10 kΩ) (RL = 100 kΩ) (RL = 1.0 MΩ) — — dB – 5.0 – 5.0 2.0 0.8 0.25 0.01 — — — — 5.0 MHz — — — — — % nA — — — — BW — 35 28 27 26 — — — — 5.0 MHz — — — — 850 100 12 1.5 — — — — #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. MOTOROLA CMOS LOGIC DATA MC14529B 3 VDD STX STY A B VN X3 Y3 IS 1k Z W VSS Pins 2, 3, 4, 12, 13 and 14 are left open. OUT VSS V VDD VSS = 0.0 V VIL: VC is raised from VSS until VC = VIL. VIL: at VC = VIL: IS = ± 10 µA with Vin = VSS, Vout = VDD VIL: Vin = VDD, Vout = VSS. VIH: When VC = VIH to VDD, the switch is ON and the RON VIH: specifications are met. Vin Figure 1. Output Voltage Test Circuit Figure 2. Noise Immunity Test Circuit VDD STX = STY = VDD ID VDD PULSE GENERATOR OUT OUT 10 k fc RL VSS VDD A0, A1 VSS PD = VDD x ID Vin Vin Figure 3. Quiescent Power Dissipation Test Circuit Figure 4. RON Characteristics Test Circuit TYPICAL RON versus INPUT VOLTAGE 250 VDD = 5 V VSS = –5 V 200 150 VDD = 7.5 V VSS = –7.5 V 100 50 0 –10 –5 0 5 Vin, INPUT VOLTAGE (Vdc) Figure 5. MC14529B 4 10 R ON “ON” RESISTANCE (OHMS) R ON “ON” RESISTANCE (OHMS) 250 VDD = 10 V VSS = 0 V 200 VDD = 15 V VSS = 0 V 150 100 50 0 0 5 10 15 20 25 Vin, INPUT VOLTAGE (Vdc) Figure 6. MOTOROLA CMOS LOGIC DATA Vout OUT VSS VDD RL STX, STY CL Vin Vin 20 ns 20 ns 90% 50% Vin STX, STY 20 ns tPLH VDD 10% tPHL 50% Vout Figure 7. Propagation Delay Test Circuit and Waveforms 10% Vout tPZL 90% A OR B V tPHZ SS Vin 90% Vx tPLZ VDD VSS Vin Vx VSS VDD 10% Figure 8. Turn–On Delay Time Test Circuit and Waveforms VFeedthrough 10 k VDD 90% 10% 50% Vout OUT CONTROL LOGIC VX tPZH VSS CL RL 50 pF VSS X, Y INPUT RL VDD OUT RL VSS VDD Vin +2.5 Vdc 1k Vin Figure 9. Crosstalk Test Circuit 0.0 Vdc –2.5 Vdc X, Y INPUT Figure 10. Frequency Response Test Circuit 30 VDD = 15 Vdc 25 p NOISE VOLTAGE (nV/ CYCLE) 35 OUT VSS VDD IN QUAN–TECH MODEL 2283 OR EQUIV 10 Vdc 20 5.0 Vdc 15 10 5.0 0 10 Figure 11. Noise Voltage Test Circuit MOTOROLA CMOS LOGIC DATA 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k Figure 12. Typical Noise Characteristics MC14529B 5 PIN ASSIGNMENT 2.0 RL = 1 MW AND 100 kW TYPICAL INSERTION LOSS (dB) 0 STX 1 16 VDD 10 kW X0 2 15 STY 1.0 kW X1 3 14 Y0 X2 4 13 Y1 X3 5 12 Y2 A 6 11 Y3 B 7 10 W VSS 8 9 Z –2.0 –4.0 –3.0 dB (RL = 1.0 MW) –3.0 dB (RL = 10 kW) –6.0 –3.0 dB (RL = 1.0 kW) –8.0 –10 –12 10 k 100 k 1.0 M 10 M fin, INPUT FREQUENCY (Hz) 100 M Figure 13. Typical Insertion Loss/Bandwidth Characteristics LOGIC DIAGRAM B 7 A 6 STY STX 15 1 2 X0 3 X1 9 Z 4 X2 5 X3 14 Y0 13 Y1 10 W 12 Y2 11 Y3 VDD = PIN 16 VSS = PIN 8 MC14529B 6 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) MOTOROLA CMOS LOGIC DATA M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14529B 7 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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