ANALOG IP BLOCK SCADC12F - CMOS 12-Bit A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 (0.35um) The SCADC12F is a complete analog to digital converter cell which operates from a single supply. It performs sampling, analog-to-digital conversion, generating a true 12 bit value in parallel form. The output word rate can be up to 1.5MS/s. The output data FEATURES ! Small Area < 0.83mm2 ! ! ! ! ! ! ! ! ! ! Size x= 862µm y= 960µm Supply Voltage 2.7-3.6 V Junction Temp. Range -40 - 125°C Resolution 12-Bit Maximum Sampling Rate 1.5MS/s Track and Hold Input Stage Rail-to-Rail Dynamic Range Single Ended and Fully Differential Input Stage Low Power of 8mW at 3.3V Supply Voltage Self Power Down Mode VR EFP2 VR EFN2 format is compatible with most µP and digital signal processors and can be unipolar or bipolar. VREFP1 6 B it L in e a r R e s is to r D A C VREFN 1 6 B it C a p a c ito r D A C V IN P C o m p a r a to r V IN N VDDA S u c c e s iv e a p p ro x im a tio n re g is t e r VSSA O u tp u t la tc h C lo c k 1 2 b it b u s C o n tro l lo g ic C LO C K VDD VSS C O NVERT R ESET SELFPD SM … D A T A<11> D AT A<10 D AT A<9> Revision B, 11.09.02 … D AT A<2> D A T A <1> D A T A<0> BUSY BUSYB Page 1 of 12 Datasheet : SCADC12F - C35 TECHNICAL DATA FOR 3.3V SUPPLY (Tjunction=-40 to 125°C, VDDA=VDD=+2.7V to +3.6V, fclk=30MHz, VREFP and VREFN as specified, pad resistors as specified in the functional block diagram, unless otherwise specified) DC ACCURACY Symbol DNL INL OFF GAINERR Parameter Resolution (missing codes possible) Differential Linearity Error Integral Linearity Error Offset Error Gain Error Conditions Min 12 Typ 12 Max 12 Units Bit -1 -2 -10 -10 ±0.5 ±0.4 0 0 +2 +2 +10 +10 LSB LSB LSB LSB Min Typ Max Units REFERENCE CHARACTERISTICS Symbol VREFP Parameter Pos. Reference Voltage VREFN Neg. Reference Voltage VREF Min. difference between VREFP and VREFN 1) 2) Reference Impedance Rref Cref Conditions 1 VDDA 2 1 VDDA 4 2.475 3 VDDA 4 V 0.825 1 VDDA 2 V VREFP-VREFN 1 1.65 5 12 Min VSSA 100 Typ 1 VDDA 2 V kΩ pF ANALOG INPUT Symbol Vin Rin Cin finmax Parameter Input Voltage Range 3) Input Impedance 1) Conditions Max VDDA 12 Max. Input Signal Frequency 750 Units V MΩ pF kHz AC ACCURACY (VREFP=2.475V, VREFN=0.825V) Symbol THD THD SFDR SFDR SNR SNR SINAD SINAD ENOB ENOB 1) 2) 3) 4) 5) Parameter Total Harmonic Distortion Total Harmonic Distortion Spurious Free Dynamic Range Spurious Free Dynamic Range Signal to Noise Ratio Signal to Noise Ratio Signal to (Noise+Dist.) Ratio Signal to (Noise+Dist.) Ratio Effective Number of Bits Effective Number of Bits Conditions fin=1kHz fin=750kHz fin=1kHz fin=750kHz fin=1kHz fin=750kHz fin=1kHz fin=750kHz fin=1kHz fin=750kHz Min Typ 4) -87 -78 4) 89 4) 80 4) 71.5 4) 71.1 4) 71.4 4) 70.4 4) 11.6 4) 11.4 4) Max 5) -78 -70 5) 80 5) 71 5) 71.5 5) 70.7 5) 70.6 5) 67.5 5) 11.4 5) 10.9 5) Capacitors are switched VREFP to VREFN VINP to VINN Measurements in Fully Differential Mode Measurements in Single Ended Mode Revision B, 11.09.02 Page 2 of 12 Units dB dB dB dB dB dB dB dB Bit Bit Datasheet : SCADC12F - C35 DIGITAL INPUTS AND OUTPUTS Symbol VDD VSS VIL VIH VOL VOH Parameter Pos. digital Supply Voltage Neg. digital Supply Voltage Digital Input Level Conditions VDD=VDDA VSS=VSSA Min 2.7 0 VSS 0.7*VDD Digital Output Level Typ 3.3 0 Max 3.6 0 0.3*VDD VDD Units V V V V V V Typ 3.3 0 320 Max 3.6 0 450 Units V V µΑ 1.8 7 330 2.5 11 600 mA mW µΑ 8 10 12 20 mW µW Max 1.5 30 Units MS/sec MHz VSS VDD POWER REQUIREMENTS Symbol VDDA VSSA 1) IDD Parameter Pos. analog Supply Voltage Neg. analog Supply Voltage Supply Current Digital IDDA 1) Psup 1) IREF 1) Supply Current Analog Supply Power Consumption Reference Current Pdiss_tot 1) 2) Pdiss_pd Total Power Consumption Power Consumption Power Down Mode Conditions VDD=VDDA VSS=VSSA Min 2.7 0 incl. Ref. TIMING CHARACTERISTICS Symbol 1/Tconv fclk Tclk Parameter Conversion Rate Master CLOCK Frequency Master CLOCK Period Tdap Tconv Tpwhclk Tpwlclk Thclk Jclk Aperture Delay Total Conversion Time CLOCK Pulsewidth High CLOCK Pulsewidth Low CLOCK Hold Time CLOCK Jitter 6 20 10 10 10 Tpwhconv Tsuconvclk Thconvclk Tpwhres Tsuresclk Tbusyclk Tbusybclk Tdbusydata Twakeup CONVERT Pulsewidth High Setup Time CONVERT to CLOCK Hold Time CONVERT to CLOCK RESET Pulsewidth High Setup Time RESET to CLOCK Time BUSY to CLOCK Time BUSYB to CLOCK Delay Time BUSY to DATA<11:0> Valid Wakeup Time 16 8 8 20 20 10 10 0 600-Tdap 1) 2) Conditions Min Typ 1 30 109 fclk 6 20 6 1*106 2 * 10 −5 fin Tclk-8 Tclk Tclk 20 In Continuous Conversion Mode at 30MHz clock frequency. After 10us power down. Revision B, 11.09.02 Page 3 of 12 nsec clk cycle clk cycle nsec nsec nsec psec nsec nsec nsec nsec nsec nsec nsec nsec nsec Datasheet : SCADC12F - C35 TYPICAL PERFORMANCE CHARACTERISTICS FOR 3.3V SUPPLY INL [LSB] DNL [LSB] (T=25deg, VDDA=VDD=+3.3V, fclk=30MHz, VREFP=+2.475V, VREFN=0.825V and Fully Differential Mode, unless otherwise specified) Digital Code Digital Code FFT [dBc] INL FFT [dBc] DNL Input Signal Frequency [Hz] Input Signal Frequency [Hz] ENOB [Bit] pg VREFP-VREFN [V] ENOB vs (VREFP-VREFN) @750kHz 2) 1) 2) Spectrum @740kHz 1) ENOB [Bit] Spectrum @10kHz 1) Input Signal Frequency [Hz] ENOB vs Input Signal Frequency 2) The spectrum consists of 16384 pins. Measured with a 1MHz low pass filter for all frequencies. Revision B, 11.09.02 Page 4 of 12 Datasheet : SCADC12F - C35 SYMBOL PINLIST Pin VINP Description Pos. Input Voltage Typ AIN Cap 12pF VINN Neg. Input Voltage AIN 12pF VREFP Pos. Reference Voltage AIN 12pF VREFN Neg. Reference Voltage AIN 12pF CONVERT Start Conversion DIN 0.1pF RESET Reset Signal DIN 0.1pF SELFPD Self power down Signal DIN 0.1pF SM Data Format Control DIN 0.1pF CLOCK Master Clock DIN 0.1pF DATA<11:0> Data Output (DATA<11>=MSB) DOUT BUSY Conversion in Progress DOUT BUSYB Conversion not in Progress DOUT VDDA Pos. Analog Supply S VSSA Neg. Analog Supply S VDD Pos. Digital Supply S VSS Neg. Digital Supply S SHIELD1 Connect to VSSA S SHIELD2 Connect to VSSA S THEORY OF OPERATION The Macro Cell SCADC12F is a 12-Bit SAR analog to digital converter. The architecture is based on a charge redistribution switched capacitor main-DAC for the MSBs and a resistor string sub-DAC for the LSBs. The inherent track-and-hold operation of the input stage avoids the need for separated sample-and-hold stages. At the beginning of the tracking phase the whole main-DAC is recharged. This causes high input current peaks. The power consumption of the cell during a conversion is very low. If the pin SELFPD is set to high the ADC goes in power down mode after the conversion has been completed and the power consumption is nearly cut off. Two reference inputs VREFP and VREFN define the dynamic range of the input signal, which may include the supply voltage. The references are used to reload the capacitors in the DAC. This causes current peaks on the references. Revision B, 11.09.02 The output signal BUSY indicates a conversion in progress when high. The output data becomes valid after it’s falling edge. BUSYB is the inverted signal to BUSY. The three input signals CONVERT, RESET and SELFPD control the operation of the circuit. The input signal SM determines the data format of the output bus. Page 5 of 12 Datasheet : SCADC12F - C35 OPERATING MODES The modes of operation are summarized in the table beside, and described in detail as follows. Description Continuous Conversion SELFPD 0 CONVERT 1 RESET 0 Oneshot mode 0 high pulse 0 Oneshot mode with self power down 1 high pulse 0 Power down 1 0 X Reset X X 1 Continuous conversion Power down mode For ‘continuous conversion’ mode the CONVERT signal is set permanently to high. The converter automatically starts a new conversion immediately after the completion of the previous one. This provides the fastest possible sampling rate. SELFPD must be set to By setting SELFPD to high the converter goes into power down mode, provided that no conversion is in progress. A CONVERT pulse ends low. Reset Oneshot mode This mode is selected by setting SELFPD to low. The conversion starts at the first rising CLOCK edge during the CONVERT pulse. After the conversion has finished the converter remains in active state, and a new conversion may immediately be started by another CONVERT pulse. Oneshot mode with self power down This mode is activated by a high SELFPD input. After a conversion has been completed the circuit turns itself off and cuts down power dissipation. Two cases have to be distinguished, depending on the used CLOCK frequency. Case 1: fclk < 10MHz In this case SELFPD can be maintained statically at high level, and a new conversion is started by the next CONVERT pulse. The circuit powers up and settles within the next 5 clock cycles. Case 2: fclk > 10MHz In this case SELFPD must be set to low level at a time Twakeup before the rising CLOCK edge, which starts the next conversion. This time may be calculated as: Twakeup = max[(600ns − Tdap),0] E.g., at fclk=30MHz the required wakeup time is: Twakeup = 600ns − 200ns = 400ns the power down mode and starts a new conversion. The asynchronous RESET input provides a means to reset the converter to a defined state. All internal registers are cleared. This also aborts a running conversion. In all modes it is necessary to send a RESET pulse once after power on to define a valid state. Track Phase Extension Normally the track phase takes 4.5 clock periods. To extent this track phase it is possible to stop the clock at a specified time. POWER SUPPLIES The converter requires a single +3.3V power supply. The supplies for analog and digital are separated and may be connected together. However, for maximum noise immunity it is recommended to wire them on chip to separated pins, especially when the block is embedded in a large digital circuit. The supplies may then be connected together on PC-board level. The proper use of blocking capacitors in the application is important ! REFERENCE VOLTAGE The positive reference voltage VREFP is split into two lines on the macroblock. The lines are signed on the gdsii-file and on the abstract and must have a pad with 0 Ohm protection resistor. The same is valid for the negative reference voltage VREFN. The proper use of blocking capacitors in the application is important ! SYSTEM REQUIREMENTS All parts of the whole system except the ADC must be quiet during a conversion, especially when the IP-block is integrated on a large mixed signal chip. Revision B, 11.09.02 Page 6 of 12 Datasheet : SCADC12F - C35 CONVERSION MODES The converter can operate as a Single Ended Converter or as a Fully Differential Converter. In both modes the internal structure is based on a fully differential architecture. SINGLE ENDED MODE To use the SCADC12F as a Single Ended Converter the input VINN must be connected to a stable voltage at (VREFP+VREFN)/2. The second input VINP can be in the range of VINN±(VREFP-VREFN). The resulting input difference voltage VINP-VINN between –(VREFP-VREFN) and +(VREFP-VREFN) is converted to a digital code depending on the control signal SM. FULLY DIFFERENTIAL MODE To use this converter as a Fully Differential Converter a difference voltage must be applied to the input VINP and VINN. The resulting input difference voltage VINP-VINN between –(VREFP-VREFN) and +(VREFP-VREFN) is converted to a digital code depending on the control signal SM. CODETABLES The signal SM determines the data format of the output bus. The digital representation of both possible codes is described in the following tables. VREF = VREFP − VREFN , 1LSB = VREFP − VREFN 2048 Offset Binary (SM=0) Output Code (SM=0) 1111 1111 1111 Input Voltage: VINP-VINN 2047LSB … VREF 1111 1111 1110 2046LSB … 2047LSB … … 1000 0000 0001 1LSB … 2LSB 1000 0000 0000 0 … 1LSB 0111 1111 1111 -1LSB … 0 0111 1111 1110 -2LSB … -1LSB … … 0000 0000 0001 -2047LSB … -2046LSB 0000 0000 0000 -VREF … -2047LSB Modified Sign and Magnitude (SM=1) Revision B, 11.09.02 Output Code (SM=1) 0111 1111 1111 Input Voltage: VINP-VINN 2047LSB … VREF 0111 1111 1110 2046LSB … 2047LSB … … 0000 0000 0001 1LSB … 2LSB 0000 0000 0000 0 … 1LSB 1000 0000 0000 -1LSB … 0 1000 0000 0001 -2LSB … -1LSB … … 1111 1111 1110 -2047LSB … -2046LSB 1111 1111 1111 -VREF … -2047LSB Page 7 of 12 Datasheet : SCADC12F - C35 FUNCTIONAL BLOCK DIAGRAM SCADC12F T&H VINP (50 Ohm) SAMPLE VINN (50 Ohm) COMP SAR VDDA VSSA SHIELD1 SHIELD2 12 VDD VSS VREFP1 (0 Ohm) 6 VREFP2 (0 Ohm) MSB DAC VREFN1 (0 Ohm) 6 VREFN2 (0 Ohm) LSB DAC 12 LATCH CONVERT 12 DATA<11:0> RESET ENCODER SELFPD CONTROLLER SM BUSY BUSYB CLOCK TIMING DIAGRAM OF SCADC12F Tconv = 20 clock cycles Tdap new conversion successive approximation 1 0 CLOCK Tsuconvclk 1 0 CONVERT track phase 1 0 SELFPD Tpwhres RESET 1 0 Tsuresclk Tbusyclk Tdclkb 1 0 BUSY Tdclkbb Tbusybclk 1 0 BUSYB Tdbusydata DATA <11:0> 0000 0000 0000 (reset) Sample N 1 0 power down Diagram 1: Continuous conversion Revision B, 11.09.02 1 0 Page 8 of 12 Datasheet : SCADC12F - C35 new conversion Tconv = 20 clock cycles Tdap successive approximation 1 0 CLOCK Tpwhconv track phase CONVERT 1 0 Tsuconvclk Thconvclk 1 0 SELFPD Tpwhres RESET 1 0 Tsuresclk Tdclkb Tbusyclk Tdclkbb Tbusybclk 1 0 BUSY BUSYB DATA <11:0> 1 0 Tdbusydata 0000 0000 0000 (reset) 1 0 Sample N 1 0 power down Diagram 2: Oneshot mode Tconv = 20 clock cycles Tdap new conversion successive approximation 1 0 CLOCK Tpwhconv track phase 1 0 CONVERT Tsuconvclk 1 0 Thconvclk SELFPD Tpwhres RESET 1 0 Tsuresclk Tdclkb Tbusyclk Tdclkbb Tbusybclk 1 0 BUSY BUSYB DATA <11:0> Tdbusydata 0000 0000 0000 (reset) Sample N 1 0 1 0 power down Diagram 3: Oneshot mode with self power down: fclk<10MHz Revision B, 11.09.02 1 0 Page 9 of 12 Datasheet : SCADC12F - C35 new conversion Tconv = 20 clock cycles Tdap successive approximation 1 0 CLOCK Tpwhconv track phase CONVERT 1 0 Tsuconvclk Thconvclk SELFPD 1 0 Twakeup RESET 1 0 Tpwhres Tsuresclk Tbusyclk Tdclkb 1 0 BUSY Tdclkbb Tbusybclk BUSYB 1 0 Tdbusydata 0000 0000 0000 (reset) DATA <11:0> 1 0 Sample N 1 0 power down Diagram 4: Oneshot mode with self power down: fclk>10MHz new conversion Tconv = 20 clock cycles (one clock period is longer) Tdap + stop time of clock successive approximation Thclk 1 0 CLOCK Tpwhconv track phase CONVERT 1 0 Tsuconvclk Thconvclk 1 0 SELFPD Tpwhres RESET 1 0 Tsuresclk Tdclkb Tbusyclk Tdclkbb Tbusybclk 1 0 BUSY BUSYB DATA <11:0> Tdbusydata 0000 0000 0000 (reset) Sample N 1 0 1 0 power down Diagram 5: Track Phase Extension Revision B, 11.09.02 1 0 Page 10 of 12 Datasheet : SCADC12F - C35 TYPICAL APPLICATION APPLICATION The SCADC12F is targeted for general purpose sampling ADC functions where linearity and high precision at medium sampling speed are of critical importance. ! ! ! ! ! Data acquisition systems Core cell for instrumentation applications Audio sampling applications Industrial control applications Servo loops and control systems. 1)2)3) +3.3V +3.3V VDDA 10uF VDD 100nF 10uF VSSA 1) 100nF 1) 2.2nF 1) 12 VIN 2.475V 2) 1.5uF 1) 0.825V 2) 1.5uF VDD VSS 1) 1.65V 3) 3) 1nF 1) 1nF Reset at power on 2uF VDDA 100nF 1) DATA<11:0> 30MHz GROUND Configuration: Continuous conversion at 1.5MS/sec, fully differential +3.3V +3.3V VDDA 10uF VDD 100nF 10uF VSSA 1) 100nF 1) 2.2nF 1) 12 VIN 2.475V 2) 1.5uF 1) 0.825V 2) 1.5uF 1) VDD VSS 1.65V 3) 3) 1nF 1) 1nF 1) 300kHz Reset at power on 2uF VDDA 100nF DATA<11:0> 10MHz GROUND Configuration: Oneshot mode at 300kS/sec, single ended 1) 2) 3) The optimal value of the capacitor depends on the input frequency. For SMD capacitors use the type NPO and for normal capacitors use the type MKT for best performance. The accuracy of both reference voltages must be higher than the resolution of the ADC. In typical applications both voltages are filtered by a second order low pass filter (fc=5Hz) and buffered with an AD711. The accuracy of both input voltages must be higher than the resolution of the ADC. In typical applications both voltages are filtered by a third order low pass filter (fc=1MHz) and buffered with a THS3001. Revision B, 11.09.02 Page 11 of 12 Datasheet : SCADC12F - C35 Contact Copyright austriamicrosystems AG A 8141 Schloss Premstätten, Austria T. +43 (0) 3136 500 5333 F. +43 (0) 3136 500 5755 [email protected] Copyright © 2002 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. Revision B, 11.09.02 Page 12 of 12