ANALOG IP BLOCK ADC1020 - CMOS 10-Bit Pipelined A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 (0.35um) The AD1020 is a high-speed pipeline ADC core cell achieving sampling rates up to 20 MS/s. A S/H circuit is built-in to provide low jitter noise and an optional singleended to fully differential conversion. The reference voltages are internally generated from a bandgap reference that must be supplied to the cell or must be supplied externally to the cell. A power down capability is included for very low power dissipation in stand-by mode. FEATURES ! Small Area: 1.57mm2 ! ! Size x= 2189.7µm y= 717.4µm Supply Voltage 2.7-3.6 V ! ! ! ! ! ! ! ! Junction Temp. Range −40 to +85°C Resolution 10-Bit Maximum Sampling Rate 20 MS/s Sample and Hold Input Stage 2 Vpp or 4 Vpp Input Signal Range Single Ended or Fully Differential Input Power Consumption of 200 mW Power Down Mode SWIB VDDA1 ONADC VDDA2 VDDD1 IBIAS Bias Current Generation ONREF VREFP VBG REF GEN VREFN VCMU VCM B ONCM DGT DOUT VINP VINN S/H Pipeline ADC CLK B9 Output Register B0 Timing Generation VSSA1 Revision C, 07.09.02 Digital Error Correction VSSAD VSSD1 Page 1 of 11 Datasheet : ADC1020 – C35 TECHNICAL DATA (Tjunction=-40 to 85°C, VDDA=VDD=+2.7V to +3.6V, fclk=20MHz, VREFP and VREFN as specified, unless otherwise specified) DC ACCURACY Symbol Parameter Resolution (No missing Code) Conditions Min 10 Typ 10 Max 10 Units Bit DNL Differential Linearity Error -0.9 ±0.4 +1 LSB INL Integral Linearity Error -1 ±0.6 +1 LSB OFF Offset Error GAINERR Gain Error for Internal Ref. GAINERR Gain Error for External Ref. 1) 2) -10 0 10 LSB Op. Mode 1 -5 0 +5 LSB Op. Mode 3,6 +23 +28 +33 LSB REFERENCE CHARACTERISTICS Symbol VBG Parameter ext. Bandgap Reference Voltage VCMU Unbuffered C. Mode Voltage VCM Buffered C. Mode Voltage Conditions Min 1.35 Typ 1.25 Max 3) 2.5 VDDA/2 1.8 V VCMU V V VREFP Pos. Reference Voltage VCM+0.4VBG VREFN Neg. Reference Voltage VCM-0.4VBG 1 Units V V 1 2 3) VREF Difference between VREFP and VREFN Rbg ext. Bandgap Ref. Impedance 10 V Ibg ext. Bandgap Ref. Input Current 5.6 Ccmu Unbuff. Comm. Mode Imped. 2.2 pF Ccm Comm. Mode Impedance (Op. Modes 2, 3, 5 and 6) 22.5 pF Rrefp Pos. Reference Impedance 18 kΩ Crefp (Op. Modes 3 and 6) 7.1 pF Rrefn Neg. Reference Impedance 18 kΩ Crefn (Op. Modes 3 and 6) 7.1 pF kΩ 4) 103 5) µA ANALOG INPUT Symbol Vind Parameter Diff. Input Voltage Range, related to VCMU Rin Input Impedance Cin Finmax 1) 2) 3) 4) 5) Conditions Min -VREF Typ Max VREF 100 MΩ 1 Max. Input Signal Frequency pF 10 MHz Offset and Gain Error correspond to measured reference voltages. This measured reference voltage VREF has a value of 960mV instead of 1000mV and 1950mV instead of 2000mV for VREF=1V and VREF=2V, respectively. This is because of an additional trop of the bandgap voltage caused by it’s pad-resistor. Offset and Gain Error correspond to measured reference voltages outside the chip. The real voltage reference VREF at the macro cell has the value 972mV instead of 1000mV and 1945mV instead of 2000mV for VREF=1V and VREF=2V, respectively. This is because of the voltage trop caused by the pad-resistors. Only for fully differential mode. For VBG=1.25V and VDDA=3.3V For VBG=2.5V and VDDA=3.3V Revision C, 07.09.02 Units V Page 2 of 11 Datasheet : ADC1020 – C35 AC ACCURACY (VREF=1V) Symbol Parameter Conditions THD THD THD SFDR SFDR SFDR SNR SNR SNR SINAD SINAD SINAD ENOB ENOB ENOB TT-IMD Total Harmonic Distortion Total Harmonic Distortion Total Harmonic Distortion Spurious Free Dynamic Range Spurious Free Dynamic Range Spurious Free Dynamic Range Signal to Noise Ratio Signal to Noise Ratio Signal to Noise Ratio Signal to (Noise+Dist.) Ratio Signal to (Noise+Dist.) Ratio Signal to (Noise+Dist.) Ratio Effective Number of Bits Effective Number of Bits Effective Number of Bits Two-Tone third order Intermodulation Distortion Two-Tone Spurious Free Dynamic Range Full Power Bandwidth fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz 3) fin1=4MHz fin2=4.5MHz fin1=4MHz 3) fin2=4.5MHz TT-SFDR FPBW Min Typ 1) Max 2) Units -69 -69 1) -66 1) 70 1) 70 1) 68 1) 57 1) 57 1) 56 1) 57 1) 57 1) 56 1) 9.2 1) 9.2 1) 9.0 1) 74 1) -68 -61 2) -58 2) 69 2) 59 2) 59 2) 57 2) 57 2) 56 2) 57 2) 56 2) 54 2) 9.2 2) 9.0 2) 8.7 2) - dB dB dB dB dB dB dB dB dB dB dB dB Bit Bit Bit dBc 70 1) - dBc 50 MHz AC ACCURACY (VREF=2V) Symbol THD THD THD SFDR SFDR SFDR SNR SNR SNR SINAD SINAD SINAD ENOB ENOB ENOB TT-IMD TT-SFDR FPBW 1) 2) 3) Parameter Total Harmonic Distortion Total Harmonic Distortion Total Harmonic Distortion Spurious Free Dynamic Range Spurious Free Dynamic Range Spurious Free Dynamic Range Signal to Noise Ratio Signal to Noise Ratio Signal to Noise Ratio Signal to (Noise+Dist.) Ratio Signal to (Noise+Dist.) Ratio Signal to (Noise+Dist.) Ratio Effective Number of Bits Effective Number of Bits Effective Number of Bits Two-Tone third order Intermodulation Distortion Two-Tone Spurious Free Dynamic Range Full Power Bandwidth Conditions fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin=180kHz fin=4.5MHz fin=10MHz fin1=4MHz 3) fin2=4.5MHz fin1=4MHz 3) fin2=4.5MHz Min Typ 1) Max -68 -68 1) -63 1) 68 1) 68 1) 64 1) 59 1) 59 1) 58 1) 58 1) 58 1) 56 1) 9.4 1) 9.4 1) 9.1 1) 70 1) - dB dB dB dB dB dB dB dB dB dB dB dB Bit Bit Bit dBc 65 1) - dBc 50 MHz Measurements in Fully Differential Mode Measurements in Single Ended Mode Both signals, fin1 and fin2, have an amplitude of -7dB full scale. Revision C, 07.09.02 Units Page 3 of 11 Datasheet : ADC1020 – C35 DIGITAL INPUTS AND OUTPUTS Symbol VDD Parameter Pos. digital Supply Voltage Conditions VDD=VDDA Min 2.7 Typ 3.3 Max 3.6 Units V VSS Neg. digital Supply Voltage GND=GNDA 0 0 0 V VIL Digital Input Level 0.3VDD V GND VIH 0.7VDD VOL Digital Output Level VOH B[9:0] Output Code VDD GND V V VDD V Vind=-VREF 000 HEX Vind=VREF 3FF HEX POWER REQUIREMENTS Symbol VDDA Parameter Pos. analog Supply Voltage Conditions VDD=VDDA Min 2.7 Typ 3.3 Max 3.6 Units V VSSA Neg. analog Supply Voltage GND=GNDA 0 0 0 V Supply Current Digital Op. Mode 1 1.5 3 mA Supply Current Analog Op. Mode 1 59 108 mA Supply Power Consumption Op. Mode 1 200 400 mW Total Power Dissipation Powerup Mode Op. Mode 1 200 400 mW IDD 1) IDDA 1) Psup 1) Pdiss_tot IDD 1) 2) Supply Current Digital Op. Mode 6 1.5 3 mA IDDA 2) Supply Current Analog Op. Mode 6 38 69 mA Psup 2) Supply Power Consumption Op. Mode 6 130 260 mW IREF 2) Reference Current Op. Mode 6 170 340 µA Pdiss_tot 2) Total Power Dissipation Powerup Mode Op. Mode 6 131 261 mW Pdiss_pd 3) Power Consumption Power Down Mode Op. Mode 0 100 200 µW Typ Max 20 Units MHz 16 * 10 −5 fin psec TIMING CHARACTERISTICS Symbol fclk Parameter CLK Frequency Conditions Min 1 1/Ts Sampling Rate Jclk CLOCK Jitter fclk MS/sec Tsd Clock falling edge to sampling instant delay 1.1 nsec Tod Clock falling edge to data out delay 5 nsec Clock duty cycle 45 50 55 % Data Latency 5 5 5 CLK cycle Power Up Delay 4) 20 CLK cycle 1) In Op. Mode 1 (internal references) with VREF=1V at 20MHz clock frequency. In Op. Mode 6 (external references) with VREF=1V at 20MHz clock frequency. 3) After 10us power down. 4) The digital output codes of the ADC are not valid during the first few clock cycles after a power up. 2) Revision C, 07.09.02 Page 4 of 11 Datasheet : ADC1020 – C35 TYPICAL PERFORMANCE CHARACTERISTICS INL [LSB] DNL [LSB] (T=25deg, VDDA=VDD=+3.3V, fclk=20MHz, VREFP=2V, VREFN=1V, Op. Mode 1 and Fully Differential Mode, unless otherwise specified) Digital Code Digital Code FFT [dBc] INL @180kHz FFT [dBc] DNL @180kHz Input Signal Frequency [Hz] Spectrum @9.8MHz 1) FFT [dBc] ENOB [Bit] Spectrum @180kHz Input Signal Frequency [Hz] 1) Input Signal Frequency [Hz] Two-Tone IMD @4.0MHz and 4.5MHz 2) 1) 2) Input Signal Frequency [Hz] ENOB vs Input Signal Frequency 2) The spectrum consists of 16384 pins. Measured with a 12MHz low pass filter for all frequencies. Revision C, 07.09.02 Page 5 of 11 Datasheet : ADC1020 – C35 SYMBOL PINLIST Pin VINP Description Pos. Input Voltage I/O I Type Analog VINN Neg. Input Voltage I Analog VBG Input for Bandgap Reference Voltage I Analog VREFP Output or bypass of Internal Pos. Reference Voltage I/O Analog VREFN Output or bypass of Internal Neg. Reference Voltage I/O Analog VCMU Input for Unbuffered Common Mode Voltage for Analog Signals I Analog VCM Output or bypass of internally buffered VCM I/O Analog CLK Clock Input I Digital B[9:0] Digital Output Bits (B9 = MSB, B0 = LSB) O Digital ONADC Power Down Input for ADC (ONADC = 1 ⇔ normal operation) I Digital ONREF Power Down Input for Reference Generator I Digital ONCM Power Down Input for VCM buffer I Digital DGT Input for digital test mode; must be tied to VSSD1 I Digital DOUT Input for ADC flash output data test mode; must be tied to VDDD1 I Digital SWIB Bias current control pin; if High, the ADC uses internal bias current; otherwise it enables the external current input. I Digital IBIAS Output for monitoring internal bias current generation when SWIB="1" or input for I/O Analog (ONREF=1⇔ normal operation) (ONCM=1⇔ normal operation) injection of external bias current (10µA) when SWIB="0" VDDA1 Top Analog Power Supply I Supply VDDA2 Top Analog Power Supply I Supply VDDD1 Top Digital Power Supply I Supply VSSA1 Bottom Analog Power Supply I Supply VSSA2 Biasing voltage for an N-Well shielding a bus from the substrate I Supply VSSD1 Bottom Digital Power Supply I Supply VSSD2 Bottom Digital Power Supply for Shielding I Supply THEORY OF OPERATION The AD1020 is a 10-bit ADC capable of sampling at 20 MS/s. It uses a fully differential pipelined architecture with 1.5-bit per stage and digital error correction to achieve improved linearity performance. A dedicated wide-band input sample-and-hold amplifier (S/H) is built-in to provide low-jitter, sub-sampling capability with inherent frequency down-conversion and, optionally, Revision C, 07.09.02 single-ended to fully differential signal conversion. The raw digital words are synchronized by a chain of delay stages and overlapped and processed by the digital error correction logic to produce the 10-bit digital output code. Page 6 of 11 Datasheet : ADC1020 – C35 OPERATING MODES The modes of operation are summarized in the table bellow, and described in detail as follows. Mode 0 Description Complete Power Down ONADC 0 ONREF X ONCM X SWIB X 1 Normal conversion with internally buffered VCM, VREF and Ibias generation 1 1 1 1 2 Normal conversion with internal VREF and Ibias generation, externally buffered VCM 1 1 0 1 3 Normal conversion with internal Ibias generation, external VCM and VREF 1 0 0 1 4 Normal conversion with internally buffered VCM, VREF and external Ibias 1 1 1 0 5 Normal conversion with internal VREF generation, external VCM and Ibias 1 1 0 0 6 Normal conversion with external VCM, VREF and Ibias 1 0 0 0 Mode 0 - Power Down In this mode all the circuitry is in power-down. The power dissipation is reduced to a minimum value. Mode 1 - Normal Conversion This is the normal conversion mode of the converter. The bias current is internally generated and the reference and the common mode voltages are internally buffered. The external bandgap reference voltage VBG determines the values of the reference voltages. Mode 2 through Mode 6 - Conversion Mode with different Bypassing options These conversion modes allow different bypassing options for the bias current generator, the reference generation and the buffer of the common mode voltages. POWER SUPPLIES The converter requires a single +3.3V power supply. The supplies for analog and digital are separated and may be connected together. However, for maximum noise immunity it is recommended to wire them on chip to separated pins, especially when the block is embedded in a large digital circuit. The supplies may then be connected together on PC-board level. The proper use of blocking capacitors in the application is important! REFERENCE VOLTAGES If ONREF is set to high the converter needs a external bandgap reference VBG which defines the dynamic range of the input signal as described in the technical data section. If ONREF is set to low the external voltage references VREFP and VREFN define the dynamic range of the input signal. A additional series resistor in the pad cell of VBG causes a wrong reference voltage generation in all modes with internal reference generation – see footnotes in the technical data section. For external reference generation an additional resistor in the pad cells of VREFP and VREFN causes a voltage drop. This results in a smaller reference difference VREF. The proper use of blocking capacitors in the application is important! Revision C, 07.09.02 Page 7 of 11 Datasheet : ADC1020 – C35 SYSTEM REQUIREMENTS The ADC is sensitive to ground noise. So all parts of the whole system except the ADC should be quiet during the conversions. To minimize ground noise coming from digital output pads the connection of a series resistor should be used to limit the switching current. In the test circuit a series resistor of 1kΩ is used for the digital output bus. CONVERSION MODES The converter operates with fully-differential or single-ended inputs. The best performance of this ADC is reached for fully-differential inputs. Single Ended Mode To use the ADC1020 as a Single Ended Converter the input VINN must be connected to VCM. In this case the ADC performs a single-ended to fully-differential conversion. The second input VINP should be balanced around VCM. Fully Differential Mode To use the ADC1020 as a Fully Differential Converter both inputs VINP and VINN should be balanced around VCM. CODE TABLES The digital representation of the data bus in both conversion modes is described in the following table. VREF = VREFP − VREFN , 1LSB = VREFP − VREFN 512 Offset Binary Output Code 11 1111 1111 Revision C, 07.09.02 Input Voltage: VIN-VINB 511LSB … VREF 11 1111 1110 510LSB … 511LSB … … 10 0000 0001 1LSB … 2LSB 10 0000 0000 0 … 1LSB 01 1111 1111 -1LSB … 0 01 1111 1110 -2LSB … -1LSB … … 00 0000 0001 -511LSB … -510LSB 00 0000 0000 -VREF … -511LSB Page 8 of 11 Datasheet : ADC1020 – C35 FUNCTIONAL BLOCK DIAGRAM In x0 x1 MDAC 1 S/H x2 MDAC 2 FLASH 1 FLASH 2 2b 2b x3 MDAC 7 x8 MDAC 8 FLASH 7 2b x9 FLASH 8 2b FLASH 9 2b D1 D2 D1 D7 D6 D1 D8 D7 D2 Clk D1 10b Out Digital Error Correction Logic TIMING DIAGRAM The sampling rate of the AD1020 is defined by the frequency of the CLK signal. The input signal voltage of the ADC is sampled in the falling edge of CLK. As the conversion stages operate in a staggered fashion in alternate phases of CLK, the duty-cycle of this signal must be 50%. The results are latched in the output register on the falling edge of CLK, with a latency of 5 CLK periods. The conversion timing is shown in Diagram 1. 1 Cycle 2 5 6 CLK Stage 0 S/H Sample of x 0(1) Stage 1 Hold of x 1(1) Sa mple & Quant. of x 1(1) Stage 2 Sa mple of x 0(2) Hold of x 1(2) Sample of x 0(8) Hold of x 1(8) Amplific ation of x 2(1) Sa mple & Quant. of x 1(2) Amplification of x 2(7) Sa mple & Quant. of x 1(8) Sa mple & Quant. of x 2(1) Amplific ation of x 3 (1) Sa mple & Quant. of x 2(7) Amplific ation of x 3(7) Sample & Quant. of x 9 (1) Stage 9 Sa mple of x 0(9) Amplific ation of x 2(8) Hold of x 1(9) Sa mple & Quant. of x 1(9) Sample & Quant. Amplific ation of x 2(8) of x 3 (8) Sa mple & Quant. of x 9(2) Digital Output q[x(1)] Tsd Tod Ts Latency of 5 CLKcycles Diagram 1: Timing of the pipelining operation Revision C, 07.09.02 Page 9 of 11 Datasheet : ADC1020 – C35 TYPICAL APPLICATION APPLICATION ! ! ! ! 1)2)3)4) ! The ADC1020 is targeted for general purpose sampling ADC functions where high-speed conversion rates and medium precision are of critical importance. +3.3V CPK 10uF 2) 100nF 2) 100pF Video Imaging Data acquisition systems High-speed data transmission Communications +3.3V VDDA 2) VDDA VDDD VDDD CPK CPK VSSD VSSA B<9:0> 4) VIN VDDD 1.65V 4) CPK 200pF 1) 200pF 1) 1.25V 3) CPK 20MHz GROUND Configuration: Op. Mode 1 at 20MS/sec, fully differential with VREF=1V +3.3V CPK 10uF 2) 100nF 2) 100pF +3.3V VDDA 2) VDDA VDDD VDDD CPK VDDA CPK VSSA VSSD 10uA CPK B<9:0> 4) VIN VDDD 2.65V 3) CPK 0.65V 3) CPK 1.65V 4) CPK 200pF 1) 200pF 1) CPK 20MHz GROUND Configuration: Op. Mode 6 at 20MS/sec, fully differential with VREF=2V 1) 2) 3) 4) The value of the capacitor depends on the input frequency. For SMD capacitors use the type NPO and for normal capacitors use the type MKT for best performance. For SMD capacitors use the type NPO and for normal capacitors use the type MKT for best performance. The accuracy of both reference voltages must be higher than the resolution of the ADC. In typical applications both voltages are filtered by a second order low pass filter (fc=5Hz) and buffered with an AD711. The accuracy of both input voltages must be higher than the resolution of the ADC. In typical applications both voltages are filtered by a third order low pass filter (fc=12MHz) and buffered with a THS3001. Revision C, 07.09.02 Page 10 of 11 Datasheet : ADC1020 – C35 Contact Copyright austriamicrosystems AG A 8141 Schloss Premstätten, Austria T. +43 (0) 3136 500 5333 F. +43 (0) 3136 500 5755 [email protected] Copyright © 2002 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. 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