V6213607 VID

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
YY MM DD
CHECKED BY
13-04-15
Phu H. Nguyen
APPROVED BY
Thomas M. Hess
SIZE
A
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AMSC N/A
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CODE IDENT. NO.
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DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
TITLE
MICROCIRCUIT, LINEAR, 4.5-V TO 60-V WIDE
INPUT SYNCHRONOUS PWM BUCK
CONTROLLER, MONOLITHIC SILICON
DWG NO.
V62/13607
16236
PAGE
1
OF
13
5962-V062-13
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance 4.5-V to 60-V wide input synchronous PWM
buck controller microcircuit, with an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/13607
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
01
Circuit function
TPS40170 -EP
4.5-V to 60-V wide input synchronous PWM buck controller
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
X
20
JEDEC PUB 95
Package style
JEDEC MO-241
Plastic Quad Flatpack No-Lead
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
DLA LAND AND MARITIME
COLUMBUS, OHIO
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/13607
PAGE
2
1.3 Absolute maximum ratings.
1/
Input voltage:
VIN ................................................................................................................................
M/S ...............................................................................................................................
UVLO ............................................................................................................................
SW ................................................................................................................................
BOOT ............................................................................................................................
Output voltage:
HDRV .............................................................................................................................
BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW) .................................
VBP, LDRV, COMP, RT, ENABLE, PGOOD, SYNC ....................................................
VDD, FB, TRK, SS, ILIM ...............................................................................................
Grounding:
AGND-PGND, PGND-AGND ........................................................................................
Power PAD to AGND (must be electrically connected external to device) ....................
Electrostatic discharge (ESD):
Human body model (HBM) ............................................................................................
Charged device model (CDM) ......................................................................................
Junction temperature range, (TJ) .........................................................................................
Storage temperature range, (Tstg) ........................................................................................
-0.3 V to 62 V
-0.3 V to VIN
-0.3 V to 16 V
-5 V to VIN
VSM + 8.8 V maximum
VSM to BOOT
-0.3 V- to 8.8 V
-0.3 V to 8.8 V
-0.3 V to 3.6 V
-200 mV to 200 mV
0 mV
1.0 kV
1.0 kV
-55°C to +125°C
-55°C to 150°C
1.4 Thermal characteristics.
Thermal metric
2/
Case outline X
Units
35.4
38.1
10.8
0.5
10.9
4.3
°C/W
Junction to ambient thermal resistance, θJA 3/
Junction to case (top) thermal resistance, θJCtop 4/
Junction to board thermal resistance, θJB 5/
Junction to top characterization parameter, ΨJT 6/
Junction to board characterization parameter, ΨJB 7/
Junction to case (bottom) thermal resistance, θJCbot 8/
1/
2/
3/
4/
5/
6/
7/
8/
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
For more information about traditional and new thermal metrics, see manufacturer data.
The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K-board,
as specified in JESD51-7, in an environment described in JESD51-2a.
The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction to top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction to board characterization parameter, ΨJB, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No
specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/13607
PAGE
3
1.4 Recommended operating conditions.
Input voltage ............................................................................................................... 4.5 V to 60 V
2. APPLICABLE DOCUMENTS
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JEP95
JESD51
JESD51-2a
JESD51-7
JESD51-8
–
–
–
–
–
Registered and Standard Outlines for Semiconductor Devices
Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device).
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air)
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-board
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103
North 10th Street, Suite 240–S, Arlington, VA 22201-2107).
AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD
ANSI SEMI STANDARD G30-88
– Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic
Packages
(Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials
International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http://www.ansi.org)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1
Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2
Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3
Terminal function. The terminal function shall be as shown in figure 3.
3.5.4
Block diagram. The block diagram shall be as shown in figure 4.
3.5.5
Simplified application. The simplified application shall be as shown in figure 5.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/13607
PAGE
4
TABLE I. Electrical performance characteristics. 1/
Test
Input supply
Input voltage range
Shutdown current
Operating current, drives not switching
ENABLE
ENABLE pin voltage to disable the device
ENABLE pin voltage to enable the device
ENABLE pin source current
8-V and 3.3-V regulators
Symbol
VVIN
ISD
IQQ
Limits
Typ
4.5
1
8-V regulator dropout voltage, VVIN-VVBP
VDO
VVDD
VUVLO
IUVLO
VBPON
VBPOFF
VBPHYS
VREF
Unit
Max
60
2.5
4.5
V
µA
mA
100
mV
410
nA
600
IENABLE
VVBP
Fixed and programmable UVLO
Programmable UVLO ON voltage (at UVLO
pin)
Hysteresis current out of UVLO pin
VBP turnon voltage
VBP turnoff voltage
VBP UVLO Hysteresis voltage
Reference
Reference voltage (+ input of the error
amplifier)
Min
VENABLE < 100 mV
VENABLE ≥ 2 V, fSW = 300 kHz
VDIS
VEN
8-V regulator output voltage
3.3-V regulator output voltage
Test conditions
2/
VENABLE ≥ 2 V, 8.2 V < VVIN ≤ 60 V,
0 mA < IIN < 20 mA
4.5 V < VVIN ≤ 8.2 V, VEN ≥ 2 V, IIN = 10 mA
VENABLE ≥ 2 V, 8.2 V < VVIN ≤ 60 V,
0 mA < IIN < 5 mA
7.8
8.0
8.35
V
3.2
110
3.3
210
3.42
mV
V
VENABLE ≥ 2 V
878
900
920
mV
VENABLE ≥ 2 V, UVLO pin > VUVLO
4.0
3.8
3.55
175
5
6.2
4.4
4.1
400
µA
V
mV
TJ = 25°C, 4.5 V < VVIN ≤ 60 V
594
600
606
mV
-55°C ≤ TJ ≤ 125°C, .4.5 V < VVIN ≤ 60 V
585
600
610
Range (typical)
RRT = 100 kΩ,, 4.5 V < VVIN ≤ 60 V
RRT = 31.6 kΩ,, 4.5 V < VVIN ≤ 60 V
RRT = 14.3 kΩ,, 4.5 V < VVIN ≤ 60 V
100
85
270
540
0.7
14
600
115
335
670
1.25
16
kHz
100
300
600
1
15
100
75
50
170
160
130
80
250
ns
VENABLE ≥ 2 V, UVLO pin > VUVLO
Oscillator
Switching frequency
fSW
Valley voltage
PWM gain (VVIN/VRAMP)
PWM and duty cycle
VVALLEY
KPWM
Minimum controlled pulse
tON(min)
Minimum OFF time
tOFF(max)
Maximum duty cycle
DMAX
4.5 V < VVIN ≤ 60 V
VVIN ≤ 4.5 V, fSW = 300 kHz
VVIN ≤ 12 V, fSW = 300 kHz
VVIN ≤ 60 V, fSW = 300 kHz
VVIN ≤ 12 V, fSW = 300 kHz
fSW = 100 kHz, 4.5 V < VVIN ≤ 60 V
fSW = 300 kHz, 4.5 V < VVIN ≤ 60 V
fSW = 600 kHz, 4.5 V < VVIN ≤ 60 V
V
V/V
95%
90%
82%
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/13607
PAGE
5
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Error amplifier
Gain bandwidth product 4/
GBWP
Open loop gain 4/
AOL
Input bias current
IIB
Output source current
IEAOP
Output sink current
IEAOM
Programmable soft start
Soft start source current at VSS < 0.5 V
ISS(source,start)
Soft start source current at VSS > 0.5 V
ISS(source,normal)
Soft start sink current
ISS(sink)
SS pin HIGH voltage during fault (OC or
VSS(fltH)
thermal) reset timing
SS pin LOW voltage during fault (OC or
VSS(fltL)
thermal) reset timing
SS pin voltage during steady state
VSS(steady_state)
Initial offset voltage from SS pin to error
VSS(offst)
amplifier input
Tracking
Range of TRK which overrides VREF
VTRK(ctrl)
Synchronization (Master/Slave)
M/S pin voltage in master mode
VMSTR
VSLV(0)
M/S pin voltage in slave 0° mode
VSLV(180)
M/S pin voltage in slave 180° mode
SYNC pin pulldown current
ISYNC(in)
SYNC pin input high voltage level
VSYNC(in_high)
SYNC pin input low voltage level
VSYNC(in_low)
Minimum SYNC high pulse duration
tSYNC(high_min)
Minimum SYNC low pulse duration
tSYNC(low_min)
Gate drivers
High side driver pullup resistance
RHDHI
High side driver pulldown resistance
RHDLO
Low side driver pullup resistance
RLDHI
Low side driver pulldown resistance
RLDLO
Time delay between HDRV fall and LDRV rise
tNON-OVERLAP1
Time delay between HDRV rise and LDRV fall
tNON-OVERLAP2
Overcurrent protection (Low-side MOSFET sensing)
ILIM pin source current
ILIM pin source current during soft start
Temperature coefficient of ILIM current
ILIM pin voltage operating range
Overcurrent protection threshold (voltage
across low-side FET for detecting overcurrent)
IILIM
IILIM,(ss)
IILIM, Tc
VILIM
OCPTH
Test conditions
2/
Limits
Unit
Min
Typ
Max
7
80
10
90
13
95
135
MHz
dB
nA
mA
mA
VVFB = 0 V
VVFB = 1 V
1.8
1.9
VSS = 0.25 V
VSS = 1.5 V
VSS = 1.5 V
42
9.2
0.7
2.38
52
11.6
1.05
2.5
62
13.9
1.36
2.65
µA
235
300
375
mV
3.2
525
3.3
650
3.55
790
V
mV
0
600
mV
3.9
1.24
0
8
2
VIN
1.74
0.74
14.5
V
V
V
µA
V
V
ns
ns
M/S configured as slave- 0° or
slave- 180°
CLOAD = 2.2 nF, IDRV = 300 mA,
TJ = -55°C to 125°C
0.8
40
40
1.37
1
1.25
0.44
CLOAD = 2.2 nF
VHDRV = 2 V, VLDRV = 2 V
4.5 V < VVIN ≤ 60 V, TJ = 25°C
4.5 V < VVIN ≤ 60 V, TJ = -55°C to 125°C
4.5 V < VVIN ≤ 60 V, TJ = 25°C
4.5 V < VVIN ≤ 60 V
4.5 V < VVIN ≤ 60 V
RILIM = 10 kΩ, IILIM = 10 µA
(VILIM = 100 mV)
11
V
9
6.9
2.64
2.4
2.4
1.1
50
60
4
4
4
1.7
9.75
11
12
Ω
ns
µA
15
1400
50
-110
-100
ppm
mV
300
-84
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/13607
PAGE
6
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Short circuit protection (High side MOSFET sensing)
LDRV pin maximum voltage during calibration
Multiplier factor to set the SCP based on OCP level
setting at the ILIM pin
Thermal shutdown
Thermal shutdown set threshold 3/
Thermal shutdown reset threshold 3/
Thermal shutdown hysteresis
Power Good
FB pin voltage upper limit for power good
FB pin voltage lower limit for power good
Power good hysteresis voltage at FB pin
PGOOD pin voltage when FB pin voltage > VOV or < VUV,
IPGD = 2 mA
PGOOD pin voltage when device power is removed
Boot diode
Bootstrap diode forward voltage
Discharge resistor from BOOT to SW
1/
2/
3/
4/
Symbol
VLDRV(max)
AOC3
AOC7
AOC15
TSD,set
TSD,reset
Thyst
Test conditions
2/
VPG(np)
VDFWD
RBOOT-SW
Unit
Min
Typ
Max
RLDRV = open
RLDRV = 10 kΩ
RLDRV = open
RLDRV = 20 kΩ
2.75
6.3
13.5
300
3.2
7.25
16.4
360
3.6
7.91
18
mV
V/V
155
125
165
135
30
175
145
°C
4.5 V < VVIN ≤ 60 V
647
552
20
675
575
33
100
mV
4.5 V < VVIN ≤ 60 V
620
520
8.4
1
1.5
V
0.7
1
1
V
MΩ
VOV
VUV
VPG,HYST
VPG(out)
Limits
VVIN is open, 10-kΩ to VEXT = 5 V
I = 20 mA
0.5
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not
necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
These specifications apply for -55°C ≤ TJ ≤ +125°C, VIN = 12 V, unless otherwise noted.
Ensured by design, not production tested.
Ensured by design at -40°C ≤ TJ ≤ +125°C, not production test.
DLA LAND AND MARITIME
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SIZE
A
CODE IDENT NO.
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PAGE
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Case X
19
D
12
11
20
E
10
1
9
2
PIN 1
INDEX AREA
A
A2 SEATING
PLANE
A1
e2
2
9
1
10
e1
11
20
THERMAL PAD
12
19
e
Symbol
A
A1
A2
b
D
L
b
20 PLS
Dimensions
Millimeters
Symbol
Min
Max
Millimeters
Min
Max
0.80
1.00
0.00
0.05
0.20 TYP
0.18
0.30
4.35
4.65
3.35
3.65
0.50 BSC
1.50 BSC
3.50 BSC
0.30
0.50
E
e
e1
e2
L
NOTES:
1. All linear dimensions are in millimeters.
2. his drawing is subject to change without notice.
3. QFN (Quad Flatpack No-Lead) package configuration .
4. The package thermal pad must be soldered to the board for thermal and mechanical performance.
5. See additional figure in the manufacturer’s data for details regarding the exposed thermal pad features and dimensions.
6. Pin 1 identifiers are located on both top and bottom of the package and within the zone indicated.
7. Falls within JEDEC MO-241 variation AB.
FIGURE 1. Case outline.
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Case outline X
Terminal
Terminal
symbol
number
ENABLE
20
SYNC
19
M/S
18
Terminal
number
1
2
3
Terminal
symbol
UVLO
VIN
BOOT
4
5
RT
SS
17
16
HDRV
6
7
8
9
10
TRK
FB
COMP
AGND
VDD
15
14
13
12
11
VBP
LDRV
PGND
ILIM
PGOOD
SW
FIGURE 2. Terminal connections.
Terminal
Symbol number
AGND
9
BOOT
18
COMP
8
I/O
O
O
ENABLE
1
I
FB
7
I
HDRV
ILIM
17
12
O
O
LDRV
14
O
M/S
3
I
PGND
PGOOD
13
11
O
RT
4
I
SS
5
I
Description
Analog signal ground. This pin must be electrically connected to power ground PGND externally.
Boot-capacitor node for high-side FET gate driver. The boot capacitor is connected from this pin to SW.
Output of the internal error amplifier. The feedback loop compensation network is connected from this pin
to the FB pin.
This pin must be high for the device to be enabled. If this pin is pulled low, the device is put in a lowpower- consumption shutdown mode.
Negative input to the error amplifier. The output voltage is fed back to this pin through a resistor-divider
network.
Gate-driver output for the high-side FET.
A resistor from this pin to PGND sets the overcurrent limit. This pin provides source current used for the
overcurrent-protection threshold setting.
Gate driver output for the low-side FET. Also, a resistor from this pin to PGND sets the multiplier factor to
determine the short-circuit current limit. If no resistor is present, the multiplier defaults to 7 times the ILIM
pin voltage
Master- or slave-mode selector pin for frequency synchronization. This pin must be tied to VIN for master
mode. In the slave mode, this pin must be tied to AGND or left floating. If the pin is tied to AGND, the
device synchronizes with a 180° phase shift. If the pin is left floating, the device synchronizes with a 0°
phase shift
Power ground. This pin must externally connect to the AGND at a single point.
Power-good indicator. This pin is an open-drain output pin, and a 10-kΩ pullup resistor is recommended to
be connected between this pin and VDD.
A resistor from this pin to AGND sets the oscillator frequency. Even if operating in slave mode, it is
required to have a resistor at this pin to set the free-running switching frequency.
Soft-start. A capacitor must be connected from this pin to AGND. The capacitor value sets the soft-start
time.
FIGURE 3. Terminal function.
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Terminal
Symbol number
SW
16
I/O
I
SYNC
2
I/O
TRK
6
I
UVLO
20
I
VBP
15
O
VDD
10
O
VIN
19
I
Description – Continued.
This pin must connect to the switching node of the synchronous buck converter. The high-side and lowside FET current sensing are also done from this node.
Synchronization. This is a bidirectional pin used for frequency synchronization. In the master mode, it is
the SYNC output pin. In the slave mode, it is a SYNC input pin. If unused, this pin can be left open.
Tracking. External signal at this pin is used for output voltage tracking. This pin goes directly to the
internal error amplifier as a positive reference. The lesser of the voltages between VTRK and the internal
600-mVreference sets the output voltage. If not used, this pin should be pulled up to VDD.
Undervoltage lockout. A resistor divider on this pin from VIN to AGND can be used to set the UVLO
threshold
8-V regulated output for gate driver. A ceramic capacitor with a value between 1 μF and 10 μF must be
connected from this pin to PGND
3.3-V regulated output. A ceramic bypass capacitor with a value between 0.1 μF and 1 μF must be
connected between this pin and the AGND pin and placed closely to this pin.
Input voltage for the controller, which is also the input voltage for the dc-dc converter. A 1-μF bypass
capacitor from this pin to AGND must be added and placed closed to VIN.
FIGURE 3. Terminal function – Continued.
DLA LAND AND MARITIME
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ENABLE
VIN
UVLO
8-V
REGULATOR
VBP
INPUT AND
REGULATORS OK
RUN
3.3-V
REGULATOR
GATE DRIVERS
V
VDD
BOOT
BP
V
IN
OSCILLATOR
AND
SYNCHRONIZATION
SYNC
M/S
RAMP
PWM LOGIC
ANTI-CROSS
CONDUCTION
-
SW
VBP
+
RUN
TRK
HDRV
CLK
RT
SS
V
+
+
+
-
EAMP
REF
FB
ERROR
AMPLIFIER
PWM
COMPARATOR
LDRV
RUN
PGND
FAULT
RUN
RUN
COMP
AGND
T
FB
T_FAULT
J
V
OVEN-TEMPERATURE
FAULT CONTROLLER
CLK
POWER GOOD
CONTROLLER
REF
PGOOD
FAULT
V
IN
SW
ILIM
LDRV
RUN
RUN
OVERCURRENT
FAULT CONTROLLER
CLK
FAULT
RESET
SOFT-START
AND
FAULT LOGIC
OC_FAULT
SS
SS EAMP
RUN
RUN
FIGURE 4. Block diagram.
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VIN
1
20
ENABLE
UVLO
2 SYNC
VIN 19
3 M/S
BOOT 18
4
RT
HDRV 17
5
SS
SW 16
6 TRK
V OUT
VBP 15
7 FB
LDRV 14
8 COMP
PGND 13
9 AGND
ILIM 12
VDD
PGOOD
10
11
FIGURE 5. Simplified application.
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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of
present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Ordering
Quantity
Vendor part number
Top side
marking
V62/13607-01XE
01295
250
TPS40170MRGYTEP
PZYM
1/ The vendor item drawing establishes an administrative control number for identifying
the item on the engineering documentation.
CAGE code
01295
DLA LAND AND MARITIME
COLUMBUS, OHIO
Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/13607
PAGE
13