TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 4.5-V TO 20-V SYNCHRONOUS BUCK CONTROLLER WITH SYNCHRONIZATION AND POWER GOOD FEATURES • • • • • • • • • • • CONTENTS Input Operating Voltage Range: 4.5 V to 20 V Output Voltage as Low as 0.591 V ±0.5% 180° Bi-Directional Out-of-Phase Synchronization Internal 5-V Regulator High and Low MOSFET Sense Overcurrent 100 kHz to 600 kHz Switching Frequency Enable and Power Good Programmable UVLO and Hysteresis Thermal Shutdown at 150°C Selectable Soft-Start Pre-Bias Output Safe Device Ratings Electrical Characteristics Typical Characteristics Terminal Information Application Information Design Example Additional References DESCRIPTION The TPS40195 is a flexible synchronous buck controller that operates from a nominal 4.5 V to 20 V supply. This controller implements voltage mode control with the switching frequency adjustable from 100 kHz to 600 kHz. Flexible features found on this device include selectable soft-start time, programmable short circuit limit, programmable undervoltage lockout (UVLO) and synchronization capability. An adaptive anti-cross conduction scheme is used to prevent shoot through current in the power FETs. Short-circuit detection is done by sensing the voltage drop across the low-side MOSFET when it is on, and comparing it with a user programmable threshold. APPLICATIONS • • • • 2 3 5 9 11 20 33 Digital TV Entry-Level and Midrange Servers Networking Equipment Non-Isolated DC-DC modules SIMPLIFIED APPLICATION DIAGRAM TPS40195 1 EN HDRV 16 2 FB SW 15 3 COMP BOOT 14 4 VDD LDRV 13 5 ULVO 6 RT SS_SEL 11 7 ILIM PGOOD 10 8 GND VOUT BP 12 SYNC Power Good 9 UDG-06066 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The threshold is set with a single external resistor connected from ILIM to GND. Pulse-by-pulse limiting (to prevent current runaway) is provided by sensing the voltage across the high-side MOSFET when it is on and terminating the cycle when the voltage drop rises above a fixed threshold of 550 mV. When the controller senses an output short circuit, both MOSFETs are turned off and a timeout period is observed before attempting to restart. This provides limited power dissipation in the event of a sustained fault. Synchronization on this device is bi-directional. Devices can be synchronized 180° out of phase to a chosen master TPS40195 running at a fixed 250 kHz or 500 kHz, or can be synchronized to an outside clock source anywhere in the 100 kHz to 600 kHz range. ORDERING INFORMATION PACKAGE QUANTITY PACKAGING (1) Plastic 16-Pin TSSOP (PW) 90 Tube TPS40195PW 2000 Reel TPS40195PWR TJ -40°C to 85°C (1) PART NUMBER For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. DEVICE RATINGS ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPS40195 VDD –0.3 to 22 SW –5 to 25 BOOT –0.3 to 30 Input voltage range HDRV -5 to 30 V BOOT–SW, HDRV–SW (Differential from BOOT or HDRV to SW) –0.3 to 6 EN, FB, BP, LDRV, PGOOD, ILIM, SYNC, UVLO, SS_SEL, RT –0.3 to 6 COMP –0.3 to 3 TJ Operating junction temperature range –40 to 150 Tstg Storage temperature –55 to 150 (1) UNIT °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VVDD Input voltage 4.5 20 V TJ Operating junction temperature -40 125 °C PACKAGE DISSIPATION RATINGS (1) 2 PACKAGE AIRFLOW (LFM) RθJA High-K Board (1) (°C/W) Power Rating (W) TA = 25°C Power Rating (W) TA = 85°C PW 0 (Natural Convection) 110 0.90 0.36 Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI Technical Brief SZZA017. Submit Documentation Feedback TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN TYP Human Body Model (HBM) 2500 Charged Device Model (CDM) 1500 MAX UNIT V ELECTRICAL CHARACTERISTICS TJ = –40°C to 85°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0°C ≤ TJ≤ 85°C 588 591 594 -40°C ≤ TJ≤ 85°C 585 591 594 UNIT REFERENCE VFB Feedback voltage range mV INPUT SUPPLY VVDD Input voltage range IVDD Operating current 4.5 20.0 VEN = 3 V 4 VEN < 0.6 V, VVDD = 12 V 165 250 VEN < 0.6 V, VVDD = 20 V 230 330 V mA µA ON BOARD REGULATOR VBP Output voltage VVDD > 6 V, IBP≤ 10 mA VDO Regulator dropout voltage, VVDD - VBP VVDD = 5 V, IBP≤ 25 mA ISC Regulator current limit threshold IBP Average current 5.1 5.3 5.5 V 350 550 mV 75 75 mA OSCILLATOR fSW Switching frequency VRT = VBP 400 500 580 VRT = 0 V 200 250 290 RRT = 100 kΩ VRMP kHz 250 Ramp amplitude (1) 1 V SYNCHRONIZATION VINH High-level input voltage VINL Low-level input voltage TF(max) Maximum input fall time (1) VOH High-level output voltage ISYNC = 100 µA, sourcing VOL Low-level output voltage ISYNC = 100 µA, sinking TF Output rise time (1) TR Output fall 2.5 0.5 100 3.5 0.3 CSYNC =25 pF time (1) 10 25 100 300 V ns V ns PWM DMAX tON(min) tDEAD Maximum duty cycle (1) Minimum controlled 85% pulse (1) Output driver dead time 130 HDRV off to LDRV on 50 LDRV off to HDRV on 25 VSS_SEL = 0 V, fSW = 250 kHz 4.8 VSS_SEL = 0 V, fSW = 500 kHz 2.4 VSS_SEL = Floating, fSW = 250 kHz 2.4 VSS_SEL = Floating, fSW = 500 kHz 1.2 VSS_SEL = VBP, fSW = 250 kHz 1.2 VSS_SEL = VBP, fSW = 500 kHz 0.6 ns SOFT-START tSS (1) Soft-start time ms Specified by design. Not production tested. Submit Documentation Feedback 3 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 85°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 7 10 MAX UNIT ERROR AMPLIFIER GBWP Gain bandwidth product (2) AOL DC gain (2) IIB Input bias current (current out of FB pin) IEAOP Output source current VFB = 0 V 1 IEAOM Output sink current VFB = 2 V 1 MHz 60 dB 100 nA mA SHORT CIRCUIT PROTECTION tPSS(min) Minimum pulse during short circuit (2) tBLNK Blanking time (2) tOFF Off-time between restart attempts IILIM ILIM pin bias current VILIMOFST Low side comparator offset voltage VILIMH Short circuit threshold voltage on high-side MOSFET 250 60 90 120 40 TJ = 25°C TJ = 25°C ns ms 7 9 11 µA -20 0 20 mV 400 550 650 mV 3 6 OUTPUT DRIVERS RHDHI High-side driver pull-up resistance VBOOT - VSW = 4.5 V, IHDRV = -100 mA RHDLO High-side driver pull-down resistance VBOOT - VSW = 4.5 V, IHDRV = 100 mA 1.5 3.0 RLDHI Low-side driver pull-up resistance ILDRV = -100 mA 2.5 5.0 RLDLO Low-side driver pull-down resistance ILDRV = 100 mA 0.8 1.5 15 35 10 25 15 35 10 25 4.1 4.3 time (2) tHRISE High-side driver rise tHFALL High-side driver fall time (2) tLRISE Low-side driver rise time (2) tLFALL Low-side driver fall time (2) CLOAD = 1 nF Ω ns UVLO VUVLOBP BP5 UVLO threshold voltage VUVLOBPH BP5 UVLO hysteresis voltage VUVLO Turn-on voltage IUVLO UVLO pin hysteresis current 3.9 800 1.125 VUVLO = 1.375 V 1.26 V mV 1.375 V µA 5.2 SHUTDOWN VIH High-level input voltage, EN VIL Low-level input voltage, EN 1.9 3 0.6 V POWER GOOD VOV Feedback voltage limit for power good 650 VUV Feedback voltage limit for power good 530 VPG_HYST Powergood hysteresis voltage at FB pin RPGD Pulldown resistance of PGD pin VFB < 530 mV or VFB > 650 mV 7 20 Ω IPDGLK Leakage current 530 mV ≤ VFB≤ 650 mV VPGOOD = 5V 7 12 µA 0.8 1.2 V mV 30 BOOT DIODE VDFWD Bootstrap diode forward voltage IBOOT = 5 mA 0.5 THERMAL SHUTDOWN TJSD Junction shutdown temperature (2) TJSDH Hysteresis (2) (2) 4 150 20 Specified by design. Not production tested. Submit Documentation Feedback °C TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 TYPICAL CHARACTERISTICS INPUT CURRENT vs JUNCTION TEMPERATURE OPERATING CURRENT IN SHUTDOWN vs JUNCTION TEMPERATURE 3.0 400 IDD - Input Current - mA 2.5 2.0 VVDD = 12 V 1.5 1.0 0.5 VVDD = 12V IDD - Operating Current in Shutdown - mA VVDD = 20 V VVDD = 20 V VVDD = 20V 0 -40 -25 -10 5 20 35 50 65 80 250 200 VVDD = 12 V 150 100 50 VVDD = 12V 95 110 125 VEN = 0 V 35 50 65 80 95 110 125 TJ - Junction Temperature - °C TJ - Junction Temperature - °C Figure 1. Figure 2. POWERGOOD LEAKAGE CURRENT vs JUNCTION TEMPERATURE CURRENT LIMIT OFFSET VOLTAGE vs JUNCTION TEMPERATURE 0 VPGOOD = 5 V VILIMOFST - Current Limit Offset Voltage - mV IPGDLK - Powergood Leakage Current - mA 8 300 VVDD = 20V 0 -40 -25 -10 5 20 10 9 350 VFB = 590 mV 7 6 5 4 3 2 1 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -40 -25 -10 TJ - Junction Temperature - °C Figure 3. 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C Figure 4. Submit Documentation Feedback 5 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) RELATIVE OVERCURRENT TRIP POINT vs FREEWHEEL TIME EN THRESHOLD VOLTAGES vs JUNCTION TEMPERATURE 3.0 4.5 VIN, VIL - Enable Thresholds Voltage - V IOC - Relative Overcurrent Trip Point - A 5.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.4 0.6 0.8 1.0 1.2 1-D - Freewheel Time - ms 1.4 2.0 1.5 1.0 Off 0.5 On Off 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C Figure 5. Figure 6. SWITCHING FREQUENCY CHANGE vs JUNCTION TEMPERATURE BP SHORT CIRCUIT CURRENT vs JUNCTION TEMPERATURE 100 GND 99 4 2 0 BP 100 kW -4 -6 BP GND -8 IBP - Short Circuit Current - mA fSW - Switching Frequency Change - % On 0 -40 -25 -10 1.6 6 -2 2.5 98 97 96 95 94 93 92 91 100 kW -10 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C 90 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C Figure 7. 6 Figure 8. Submit Documentation Feedback TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) BP DROPOUT VOLTAGE vs JUNCTION TEMPERATURE UNDERVOLTAGE LOCKOUT THRESHOLD vs JUNCTION TEMPERATURE 1.30 450 VDO - Dropout Voltage - V 400 350 300 250 200 150 100 VVDD = 5 V ILOAD = 25 mA 50 0 -40 -25 -10 5 20 35 50 65 80 VUVLO - Undervoltage Lockout Threshold - V 500 1.29 1.28 1.27 1.26 1.25 -40 -25 -10 95 110 125 TJ - Junction Temperature - °C 20 35 50 65 80 95 110 125 Figure 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs JUNCTION TEMPERATURE BP UNDERVOLTAGE LOCKOUT VOLTAGE vs JUNCTION TEMPERATURE 5.8 VUVLO = 1.375 V 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C VUVLOBP - Bypass Undervoltage Lockout Voltage - V Figure 9. 6.0 IUVLO - Hysteresis Current - mA 5 TJ - Junction Temperature - °C 4.2 4.1 4.0 Turn On 3.9 3.8 3.7 3.6 3.5 Turn Off 3.4 3.3 3.2 -40 -25 -10 Figure 11. 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C Figure 12. Submit Documentation Feedback 7 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) FEEDBACK BIAS CURRENT vs JUNCTION TEMPERATURE RELATIVE FEEDBACK VOLTAGE CHANGE vs JUNCTION TEMPERATURE 25 VFB - Feedback Voltage Reference Change - % 0.5 IFB - Feedback Bias Current - nA 20 15 10 5 0 -5 -10 -15 0.4 VFB = 591 mV (typ) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -40 -25 -10 -20 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C 5 20 Figure 13. 900 800 fOSC - Oscillator Frequency - kHz 50 Figure 14. OSCILLATOR FREQUENCY vs TIMING RESISTANCE 700 600 500 400 300 200 100 0 0 50 100 150 200 RRT - TIming Resistance - kW Figure 15. 8 35 Submit Documentation Feedback 250 65 80 95 110 125 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. BOOT 14 I Gate drive voltage for the high-side N-channel MOSFET. A 100-nF capacitor (typical) must be connected between this pin and SW. BP 12 O Output bypass for the internal regulator. Connect a capacitor of 1-µF (or greater) from this pin to GND. Larger capacitors, up to 4.7µF will improve noise performance with a low side FET Qg over 25nC. Do not connect to VDD or drive externally. COMP 3 O Output of the error amplifier. EN 1 I Logic level input which starts or stops the controller from an external user command. A high-level turns the controller on. A weak internal pull-up holds this pin high so that the pin may be left floating if this function is not used. Observe interface cautions in applications information. FB 2 I Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference voltage (591 mV typical) GND 8 - Common reference for the device HDRV 16 O Gate drive output to the high-side N-channel FET. ILIM 7 I Current limit. Sets short circuit protection threshold for low-side MOSFET sensing. Connect a resistor to GND to set the threshold LDRV 13 O Gate drive output for the low side N-channel FET. PGOOD 10 O Open drain power good output. Pulls low under any fault condition, soft start is active or if the FB pin voltage is outside the specified voltage window. RT 6 I Switching frequency programming pin. Also determines function of SYNC pin. Connected to GND for 250 kHz operation and using SYNC as an output. Connect to BP for 500-kHz operation and using SYNC as an output. Connect a resistor to GND to program a frequency and allow SYNC to accept synchronization pulses. If RT is used to program a switching frequency and SYNC is not to be used to synchronize the converter to an external clock, connect SYNC to GND. SS_SEL 11 I Soft-start timing selection. Can be connected to GND, BP or left floating to select a soft start time that is proportional to the switching frequency. SW 15 I Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high-side MOSFET driver Bidirectional synchronization I/O pin. SYNC is an output when the RT pin is connected to BP or GND. The output is a falling edge signal 180° out-of-phase with the rising edge of HDRV. In this mode SYNC can be used to drive the SYNC pin of an additional TPS40195 device whose RT pin is tied to GND through a resistor, providing two converters that operate 180° out-of-phase to one another. SYNC may be used as an input to synchronize to an external system clock if RT is connected to GND through a resistor as well. The device synchronizes to the falling edge of the external clock signal. If RT is used to program a switching frequency and SYNC is not to be used to synchronize the converter to an external clock, connect SYNC to GND. SYNC 9 I/O UVLO 5 I Programmable UVLO pin for the controller. A resistor divider on this pin to VDD sets the converter turn on voltage and the hysteresis for turn-off. VDD 4 I Power input to the controller. A 100 nF bypass capacitor should be connected closely from this pin to GND. PW PACKAGE (TOP VIEW) EN FB COMP VDD UVLO RT ILIM GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Submit Documentation Feedback HDRV SW BOOT LDRV BP SS_SEL PGOOD SYNC 9 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 BLOCK DIAGRAM SS_SEL 11 VDD 1.5 MW EN BP Overtemperature CLK Fault Controller SD 1 Soft Start Ramp Generator SD UVLO 9 mA 7 SS SC_LOW ILIM BUF + 550 mV 5V Regulator 4 BP 12 + VDD + SC_HIGH VDD BP BP, 5 V 14 BOOT 5.2 mA UVLO 5 RT 5 16 HDRV + 1.26 V FAULT 6 COMP 3 2 GND 8 SS + BP 15 SW 13 LDRV + 591 mV FB UVLO CLK Oscillator SYNC PWM Logic and Anti-Cross Conduction Error Amplifier SD 10 PGOOD 0.65 V + FAULT SD 750 kW Powergood SS Control + 0.53 V SS ACTIVE UDG-06065 10 Submit Documentation Feedback TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 APPLICATION INFORMATION Introduction The TPS40195 is a flexible controller providing all the necessary features to construct a high performance DC-DC converter while keeping costs to a minimum. Support for pre-biased outputs eliminates concerns about damaging sensitive loads during startup. Strong gate drivers for the high side and rectifier N channel FETs decrease switching losses for increased efficiency. Adaptive gate drive timing minimizes body diode conduction in the rectifier FET, also increasing efficiency. Selectable short circuit protection thresholds and hiccup recovery from a short circuit increase design flexibility and minimize power dissipation in the event of a prolonged output fault. A dedicated enable pin (EN) allows the converter to be placed in a low quiescent current shutdown mode. Enable Functionality The TPS40195 has a dedicated device enable (EN) pin. This simplifies user level interface design since no multiplexed functions exist. Another benefit is a true low power shutdown mode of operation. When the EN pin is pulled to GND, the TPS40195 consumes a typical 165-µA of current. A functionally equivalent circuit to the enable circuitry on the TPS40195 is shown in Figure 16. VDD 4 1.5 MW 200 kW 1 kW EN 1 To Enable Chip 200 W 1 kW 300 kW GND 8 UDG-07005 Figure 16. TPS40195 EN Pin Internal Circuitry If the EN pin is left floating, the chip starts automatically. The pin must be pulled to less than 600 mV for the TPS40195 to be in shutdown mode. Note that the EN pin is relatively high impedance. In some situations, there could be enough noise nearby to cause the EN pin to swing below the 600 mV threshold and give erroneous shutdown commands to the rest of the device. There are two solutions to this problem should it arise. 1. Place a capacitor from EN to GND. A side effect of this is to delay the start of the converter while the capacitor charges past the enable threshold 2. Place a resistor from VDD to EN. This causes more current to flow in the shutdown mode, but does not delay converter startup. If a resistor is used, the total current into the EN pin should be limited to no more than 500 µA. Submit Documentation Feedback 11 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 APPLICATION INFORMATION (continued) EN (1 V /div) VOUT (1 V /div) PGOOD (2 V /div) HDRV (2 V /div) T - Time - 500 ms/div Figure 17. TPS40195 EN Pin Startup Voltage Reference The band gap cell is designed with a trimmed 0.591-V output. The 0.5% tolerance on the reference voltage allows the user to design a very accurate power supply. Oscillator and Synchronization The TPS40195 has a programmable switching frequency of 100 kHz to 600 kHz using a resistor connected from the RT pin to GND. The relationship between switching frequency and the resistor from RT to GND is given in Equation 1. 4 fSW = 2.5 ´ (10 ) RRT (1) where • • fSW is the switching frequency in kHz RRT is the resistor connected from RT to GND in kΩ When the oscillator is programmed using this method, the SYNC pin is configured as an input. The device may be synchronized to a higher frequency than the free running frequency by applying a pulse train to the SYNC pin. For best results, limit the frequency of the pulse train applied to SYNC to 20% more than the free running frequency. The TPS40195 will synchronize to the falling edge of the pulse train applied to the SYNC pin. 12 Submit Documentation Feedback TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 APPLICATION INFORMATION (continued) The SYNC pin can also function as an output. To get this functionality, the RT pin must be connected to either GND or to BP. When this is done the oscillator will run at either 250 kHz or 500 kHz. SYNC can then be connected to other TPS40195 controllers (with their SYNC pins configured as an input) and the two or more controllers will synchronize to the same switching frequency. The output waveform on SYNC will be approximately a 50% duty cycle pulse train. The pull up is relatively weak, but the pull down is strong to insure that a good clean signal is presented to any devices that are to be synchronized. A summary is shown in Table 1. Table 1. RT Connection and SYNC Pin Function RT Connection SYNC Pin Function Switching Frequency Resistor to GND Input See Equation 1 GND Output 250 kHz BP Output 500 kHz Using the TPS40195 with its RT pin connected to BP or to GND as a master clock source for another TPS40195 with a resistor connected from its RT pin to GND will result in the two controllers operating at the same frequency but 180° out of phase. External SYNC (5 V /div) SW Master (10 V /div) SW (2 V /div) SW Slave (10 V /div) SYNC Out-of-Phase from Master LDRV (5 V/div) T - Time - 1 ms/div T - Time - 1 ms/div Figure 18. TPS40195 Synchronized to External SYNC Pin Pulse (Negative Edge Triggered) Figure 19. TPS40195 SYNC Pin Master/Slave Configuration. 180° Out-of-Phase Operation Undervoltage Lockout (UVLO) There are two separate UVLO circuits in the TPS40195. Both must be satisfied before the controller starts. One circuit detects the BP voltage and the other circuit detects voltage on the UVLO pin. The voltage on the BP pin (VBP) must be above 4.3 V in order for the device to start up. The UVLO pin is generally used to provide a higher UVLO voltage than that which the BP UVLO circuit provides. This level is programmed using a resistor divider from VIN to GND with the tap connected to the UVLO pin of the TPS40195. Hysteresis is provided by a 5.2-µA current source that is turned on when the UVLO pin reaches the 1.26 V turn on threshold. The turn on level is determined by the divider ratio, and the hysteresis level is determined by the divider equivalent impedance. To determine the resistor values for the UVLO circuit, a turn on voltage and turn off voltage must be known. Once these are known the resistors can be calculated in Equation 2 and Equation 3. The functional schematic is shown in Figure 20. Submit Documentation Feedback 13 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 V - VOFF R1 = ON IUVLO R2 = R1 ´ (2) VUVLO VON - VUVLO (3) where • • • • VON is the desired turn on voltage of the converter VOFF is the desired turn off voltage for the converter, must be less than VON IUVLO is the hysteresis current generated by the device, 5.2 µA (typ) VUVLO is the UVLO pin threshold voltage, 1.26 V (typ) VIN BP IUVLO 5.2 mA (typ) R1 + 5 UVLO 1.26 V R2 UDG-07002 Figure 20. Undervoltage Lockout Soft Start The TPS40195 uses a digital closed loop soft start system. The soft start ramp is generated internally by a counter and digital-to-analog converter (DAC) that ramps up the effective reference voltage to the error amplifier. The DAC supplies a voltage to the error amp that is used as the reference until that supplied voltage becomes greater than the 591-mV reference voltage. At that point soft-start is complete and the 591-mV reference controls the output voltage. The ramp rate is dependent on the oscillator frequency as each step in the DAC takes one clock cycle from the oscillator. The user can choose from three ramp rates, or DAC counter widths depending on viewpoint, for any given switching frequency by connecting the SS_SEL pin to GND, BP pin or letting the pin float. The possibilities are summarized in Table 2. Table 2. Soft Start Clock Cycles 14 SS_SEL Connection Clock Cycles in 1-V Ramp (NDAC) GND 2048 Floating 1024 BP 512 Submit Documentation Feedback TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 The ramp output from the soft start DAC is 1 V in amplitude. Since the soft start is closed loop and reference voltage of the device is actually 591 mV, the actual ramp time is less than the time it takes for the SS ramp to finish and reach 1 V. The actual soft-start time is the amount of time that it takes for the internal soft-start ramp to reach the 591-mV reference level. The soft-start time can be found using Equation 4. N tSS = 0.591´ DAC fSW (4) where • • NDAC is the number of 1-V DAC ramp cycles from table fSW is the switching frequency in Hz Selecting the Short Circuit Threshold A short circuit in the TPS40195 is detected by sensing a voltage drop across the low-side FET when it is on, and across the high-side FET when it is on. If the voltage drop across either FET exceeds the short circuit threshold in any given switching cycle, a counter increments one count. If the voltage across the high-side FET was higher that the short circuit threshold, that FET is turned off early. If the voltage drop across either FET does not exceed the short circuit threshold during a cycle, the counter is decremented for that cycle. If the counter fills up (a count of 7) a fault condition is declared and the drivers turn off both MOSFETs. After a timeout of approximately 40 ms, the controller attempts to restart. If a short circuit remains present at the output, the current quickly ramps up to the short circuit threshold and another fault condition is declared and the process of waiting for the 40 ms and attempting to restart repeats. The current limit threshold for the low-side FET is programmable by the user. To set the threshold a resistor is connected from the ILIM pin to GND. A current source inside the IC connected to the ILIM pin and this resistor set a voltage that is the threshold used for the overcurrent detection threshold. The low side threshold will increase as the low side on time decreases due to blanking time and comparator response time. See Figure 5 for changes in the threshold as the low-side FET conduction time decreases. Refer to Figure 21 for details on the functional equivalent schematic. BP IILIM 9 mA ILIM + tBLNK 7 LDRV On RILIM R VDD + 3-Bit Counter UP/DN Q R S SW Q0 Q R 15 CLK + Q1 Fault HDRV + Q2 550 mV tBLNK HDRV On VDD LDRV UDG-07001 Figure 21. Overcurrent ISCP(min ) = IILIM(min ) ´ RILIM(min ) + VILIMOFST(min ) RDS(on )(max ) (5) Submit Documentation Feedback 15 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 ISCP(max ) = IILIM(max )´ RILIM(max ) + VILIMOFST(max ) RDS(on)(min ) (6) where • • • • • IS.P. is the short circuit current IILIM is ILIM pin bias current, 9.0µA (typ) RILIM is the resistance connected from ILIM to GND VILIMOFST is the offset voltage of the low side current sense comparator, ±20 mV RDS(on) is the channel resistance of the low-side MOSFET The short circuit protection threshold for the high-side MOSFET is fixed at 550-mV typical, 400-mV minimum with a 4000 ppm/°C temperature coefficient to help compensate for changes in the high side FET channel resistance as temperature increases. This threshold is in place to provide a maximum current output in the case of a fault. The maximum amount of current that can be sourced from a converter can be found by Equation 7. IOUT(max ) = VILIMH(min ) RDS(on)(max ) (7) where • • • IOUT(max) is the maximum current that the converter is specified to source VILIMH(min) is the short circuit threshold for the high-side MOSFET (400 mV) RDS(on)max is the maximum resistance of the high-side MOSFET If the required current from the converter is greater than the calculated IOUT(max) , a lower resistance high-side MOSFET must be chosen. 5-V Regulator This device has an on board 5-V regulator that allows the parts to operate from a single voltage feed. No separate 5-V feed to the part is required. This regulator requires a minimum of 1 µF of capacitance on the BP pin for stability. A ceramic capacitor is suggested for this purpose. Noise performance can be improved by increasing this capacitance to 4.7 µF when driving FETs with more than 25nC gate charge requirements. This regulator can also be used to supply power to nearby circuitry, eliminating the need for a separate LDO in some cases. If this pin is used for external loads, be aware that this is the power supply for the internals of the TPS40195. While efforts have been made to reduce sensitivity, any noise induced on this line has an adverse effect on the overall performance of the internal circuitry and shows up as increased pulse jitter, or skewed reference voltage. The amount of power available from this pin varies with the size of the power MOSFETs that the drivers must operate. Larger MOSFETs require more gate drive current and reduces the amount of power available on this pin for other tasks. Pre-Bias Startup The TPS40195 contains a unique circuit to prevent current from being pulled from the output during startup in the condition the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft-start becomes greater than feedback voltage [VFB]), the controller slowly activates synchronous rectification by starting the first LDRV pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensures that the out voltage (VOUT) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased startup to normal mode operation with minimal disturbance to the output voltage. The amount of time from the start of switching until the low-side MOSFET is turned on for the full 1-D interval is defined by 32 clock cycles. 16 Submit Documentation Feedback TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 Drivers The drivers for the external HDRV and LDRV MOSFETs are capable of driving a gate-to-source voltage of 5 V. The LDRV driver switches between VDD and GND, while HDRV driver is referenced to SW and switches between BOOT and SW. The drivers have non-overlapping timing that is governed by an adaptive delay circuit to minimize body diode conduction in the synchronous rectifier. The drivers are capable of driving MOSFETS that are appropriate for a 15-A converter if power dissipation requirements are met. See Package Dissipation Ratings Table. Power Good The TPS40195 provides an indication that output power is good for the converter. This is an open drain signal and pulls low when any condition exists that would indicate that the output of the supply might be out of regulation. These conditions include: • VFB > ±10% from nominal • soft-start is active • a undervoltage condition exists for the device • a short circuit condition has been detected • die temperature is over (150°C) NOTE: When there is no power to the device, PGOOD is not able to pull close to GND if an auxiliary supply is used for the power good indication. In this case, a built in resistor connected from drain to gate on the PGOOD pull down device makes the PGOOD pin look approximately like a diode to GND. Thermal Shutdown Thermal shutdown If the junction temperature of the device reaches the thermal shutdown limit of 150°C, the PWM and the oscillator is turned off and HDRV and LDRV are driven low, turning off both FETs. When the junction cools to the required level (130°C nominal), the PWM initiates soft start as during a normal power up cycle. Submit Documentation Feedback 17 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 Layout Suggestions VIN CIN TPS40195 1 EN HDRV 16 2 FB SW 15 3 COMP 4 VDD 5 UVLO 6 RT 7 ILIM PGOOD 8 10 GND SYNC 9 High-Side Drive Current Input Current Loop VIN to GND BOOT 14 VOUT BP 12 SS_SEL 11 Low-Side Drive Current LDRV 13 Output Current Loop VOUT to GND PWR GND UDG-07004 Signal Ground Figure 22. Layout Suggestion • • • • • • • 18 Keep the input switching current loop as small as possible. Place the input capacitor (CIN) close to the top switching FET The output loop current loop should also be kept as small as possible. Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize radiated emissions Kelvin connections should be brought from the output to the feedback pin (FB) of the device. Keep analog and non-switching components away from switching components. The gate drive trace should be as close to the power FET’s gate as possible. Make a single point connection from the signal ground to power ground. Do not allow switching current to flow under the device. Submit Documentation Feedback TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 Input capacitors near Drain of top FET Small switch node area Analog components away from Power Switching elements Kelvin Feed back connection Figure 23. Board Layout Submit Documentation Feedback 19 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 DESIGN EXAMPLES Design Example 1 Table 3. Design Example Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 10.8 12.0 13.2 V 1.7 1.8 A INPUT VIN IIN Input voltage VIN = 12 V, IOUT= 10 A Input current No load, VIN = 12 V, IOUT= 0 A 5 VIN_ Undervoltage lockout turn off threshold UVLO_OFF 0 A ≤ IOUT≤ 10 A 5.4 6.0 6.6 VIN_UVLO _ON Undervoltage lockout turn on threshold 0 A ≤ IOUT≤ 10 A 6.6 7.0 7.6 Input voltage range VIN = 12 V, IOUT= 5 1.75 1.80 1.85 Line regulation 10.8 ≤ VIN≤ 13.2 V 0.5% Load regulation 0 A ≤ IOUT≤ 10 A 0.5% VOUT(ripple) Output voltage ripple VIN = 12 V, IOUT= 10 A IOUT Output current 10.8 ≤ VIN≤ 13.2 V IOCP Output overcurrent inception point VIN = 12 V, VOUT= (VOUT- 5) ∆I Transient response load step 10 A ≤ IOUT(max) ≤ 0.2 × ( IOUT(max) ) mA V OUTPUT VOUT 100 0 5 10 14 20 43 Transient response load slew rate Transient response overshoot Transient response settling time V mVP-P A 8 A 5 A/µs 200 mV 1 ms SYSTEM fSW Switching frequency ηPK Peak efficiency VIN = 12 V, 0 A ≤ IOUT≤ 10 A 240 90% η Efficiency at full load VIN = 12 V, IOUT = 10 A 87% TOP Operating temperature range 10.8 ≤ VIN≤ 13.2 V, 0 A ≤ IOUT≤ 10 A -40 300 25 360 kHz 85 °C MECHANICAL W Width 1.6 L Length 3.5 h Height 0.26 20 Submit Documentation Feedback in TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 Schematic This section discusses basic buck converter design. Designers already familiar with the design of buck converters can skip to the next section Component Selection of this design example. Figure 24. TPS40195 Design Example Schematic Output Inductor, LOUT Equation 8 can be used to calculate LOUT. LOUT = (VIN(max) - VOUT ) 1.8 V VOUT (13.2 V - 1.8 V) ´ = ´ = 2.59 mH fSW ´ IRIPPLE VIN(max) 13.2 V 300kHz ´ 2.0 (8) where • IRIPPLE = the allowable ripple current in the inductor, 20% of maximum IOUT For this design a 2.5-µH inductor from Coilcraft is used. IRIPPLE is recalculated using Equation 9 and a 2.5-µH inductor value to give a new estimate of IRIPPLE of 2.1 A . IRIPPLE = (VIN(max) - VOUT ) VOUT ´ fSW ´ LOUT VIN(max) 1.83 V (13.2 V - 1.83 V) ´ = 2.10 A 13.2 V 300kHz ´ 2.5 mH = (9) With this IRIPPLE value, the RMS and peak current flowing in LOUTcan be calculated. ILOUT _RMS = IPK = IOUT + 2 (IOUT ) + (IRIPPLE )2 12 = 2 (10 ) + (2.10 )2 12 = 10.02 A IRIPPLE 2.10 = 10 + = 11.05 A 2 2 Submit Documentation Feedback (10) (11) 21 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 Output Capacitor, COUT The capacitance value is selected to be greater than the largest value calculated from Equation 12 and Equation 13. 2 COUT = = 2 ´ VUNDER ´ DMAX ´ VIN(min) - VOUT ( 2 COUT = 2 LOUT ´ (ISTEP ) LOUT ´ (ISTEP ) 2 ´ VOVER ´ VOUT = ) 2.5 mH ´ (8 ) 2 ´ 200mV ´ 90% ´ (10.8 V - 1.8 V ) = 71.68 mF 2.5 mH ´ 82 = 222.2 mF 2 ´ 200mV ´ 1.8 V V 100mV ESR = RIPPLE = = 47mW IRIPPLE 2.1A (12) (13) (14) From Equation 12, Equation 13 and Equation 14, the capacitance for COUT should be greater than 223 µF and its ESR should be less than 47 mΩ. Three 100-µF, 6.3-V, X5R ceramic capacitors are chosen. Each capacitor has an ESR of 5 mΩ . Input Capacitor, CIN The input capacitor is selected to handle the ripple current of the buck stage. A relatively large capacitance is used to keep the ripple voltage on the supply line low. This is especially important were the supply line has a high impedance. It is recommended that the supply line impedance be kept low. The input capacitor RMS current can be calculated using Equation 15. 2 2 éæ ö ö æ ö (IRIPPLE )2 ùú VOUT æ VOUT V V ´ +ç ´ IOUT ÷ ´ ç 1 - OUT ÷ ICAP(RMS) = êç IOUT - OUT ´ IOUT ÷ + êè ú VIN 12 VIN VIN ø ø è VIN ø è ë û (15) The RMS current in the input capacitor is 3.56 A. Two 22-µF, size 1206 capacitors using X7R material has a typical dissipation factor of 5%. For a 22-µF capacitor at 300 kHz the ESR is approximately 5 mΩ. Two of these capacitors are used in parallel. The power dissipation in each capacitor is less than 16 mW. A 470-µF, 25-V electrolytic is added to maintain the voltage on the input rail. Switching MOSFET, QSW The following key parameters must be met by the selected MOSFET. • Drain-to-source voltage, VDS, must be able to withstand the input voltage plus spikes that may be on the switching node. For this design a VDS rating of between 25 V and 30 V is recommended. IQSW(rms) = • 2 æ 2 (IRIPPLE ) VOUT ç ´ IOUT(max) + VIN(min) ç 12 è ( ) ö ÷ ÷ ø (16) For this design IDD should be greater than 4.1 A Gate source voltage, Vgs, must be able to withstand the gate voltage from the control device. For the TPS40195 this is 5 V. Target efficiency for this design is 90%. Based on 1.8-V output and 10-A operating current this equates to a power loss in the module of 1.8 W. The design allocates this power budget equally between the two power FETS and the inductor The equations below are used to calculate the power loss, PQSW, in the switching MOSFET. PGATE = Qg(TOT) ´ Vg ´ fSW (17) PQSW = PCON + PSW + PGATE 22 (18) Submit Documentation Feedback TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 ( PCON = RDS(on) ´ IQSW(rms) 2 ) = RDS(on) ´ 2 VOUT æç 2 (IRIPPLE ) ´ (IOUT ) + ç VIN 12 è éæ IRIPPLE ö ´ Qgs1 + Q gd ê ç IOUT + 2 ÷ø è ê = VIN ´ fS ´ ê Ig ê ë ( PSW ö ÷ ÷ ø (19) ù )ú ú ú ú û (20) where • • • • • • • • PCON is conduction losses PSW is switching losses PGATE is gate drive losses Qgd is drain source charge or miller charge Qgs1 is gate source post threshold charge Ig is gate drive current Qg(TOT) is total gate charge from 0 V to the gate voltage Vg is gate voltage Equation 21 and Equation 22 describe the preliminary values for RDS(on) and (Qgs1 + Qgd). Note output losses due to QOSS and gate losses have been ignored here. Once a MOSFET is selected these parameters can be added. The switching MOSFET for this design should have an RDS (on) of less than 20 mΩ . The sum of Qgd and Qgs1 should be approximately 14.8 nC. . The Vishay SI7860ADP was selected for this design. This device has an RDS(on) of 9 mΩ and a (Qgs1+Qgd) of 13 nC. The estimated conduction losses are 0.135 W and the switching losses are 0.297 W. This gives a total estimated power loss of 0.432 W versus 0.6 W for our initial boundary condition. Note this does not include gate losses of approximately 10 mW. Rectifier MOSFET, QSR Similar criteria as used above apply to the rectifier MOSFET. One significant difference however, is that the rectifier MOSFET switches with nearly zero voltage across its drain and source so its switching losses are nearly zero. There are losses from the source to drain body diode that occur as it conducts during the delay before the FET turns on. The equations used to calculate the losses in the rectifier MOSFET are shown below. PQSR = PCON + PBD + PGATE ( PCON = RDS(on) ´ IQSW(rms) (21) 2 ) = RDS(on) ´ 2 VOUT æç 2 (IRIPPLE ) ´ (IOUT ) + ç VIN 12 è ö ÷ ÷ ø (22) PGATE = Qg(TOT) ´ Vg ´ fSW PBD = Vf ´ IOUT ´ (t1 + t 2 )´ fS (23) where • • • • PBD is the body diode loss t1 is the body diode conduction prior to turn-on of channel (57nS) t2 is the body diode conduction after turn-off of channel (14nS) Vf is the body diode forward voltage Estimating the body diode losses based on a forward voltage of 1.0 V yields 0.162 W. The gate losses are unknown at this time so assume 0.1 W gate losses. This leaves 0.338 W for conduction losses. Using this figure a target RDS(on) of 4.0 mΩ was calculated. The SI7886ADP has an RDS(on) maximum of 4.8 mΩ and was used for this design. Submit Documentation Feedback 23 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 Using the parameters from its data sheet the actual expected power losses were calculated. Conduction loss is 0.394 W, body diode loss is 0.210 W and the gate loss was 0.063 W. This totals 0.667 W associated with the rectifier MOSFET. The ratio between Cgs and Cgd should be greater than one. The Si7886 capacitor meets this criterion and helps reduce the risk of dv/dt induced turn on of the rectifier MOSFET. If this is likely to be a problem a small resistor may be added in series with the boost capacitor, CBOOST. to slow the turn on speed of QSW at the expense of increased switching losses in that device. Component Selection for the TPS40195 Timing Resistor, RT The timing resistor is calculated using the following equation. 7 RT = 2.5 ´ (10 ) fS 7 = 2.5 ´ (10 ) 300 = 83.3kW (24) A standard value resistor of 82.5 kΩ is used. Setting UVLO The equations below are used to set the UVLO voltages. RUVLO1 = VON - VOFF 7-6 = = 192.3kW -6 IUVLO 5.2 ´ (10 ) RUVLO2 = RUVLO1 ´ VUVLO 1.26 = 192.3kW ´ = 42.2kW - 1.26 7 V V ( ON UVLO ) (25) (26) The UVLO threshold voltage ( VUVLO) is 1.26 V. The module has a turn on voltage of 7 V and a turn off voltage of 6 V. This sets RUVLO1to 191 kΩ, the nearest standard value. The second resistor RUVLO2 is 42.2 kΩ. Setting the Soft-Start Time The selection of the soft start time should be greater than the time constant of the output filter, LOUT and COUT. This time is given in Equation 27 and Equation 28. tSTART ³ 2p ´ LOUT ´ COUT -6 tSTART ³ 6.28 ´ 2.5 ´ (10 ) (27) -6 ´ 300 ´ (10 ) = 0.172ms (28) The soft-start time is determined using Equation 29 . The TPS40195 uses a counter operating at the clock frequency that increments an internal DAC until it reaches the turn on threshold voltage of 0.591 V. The number of counts required to reach this threshold is determined by one of three settings on the SS pin. In this case, the pin is floating (with a small bypass capacitor) which sets the clock count (NDAC) to 1024 and the soft-start time is 2.0 ms t SS = 0.591 ´ 24 NDAC 1024 = 0.591 ´ = 2.0 ms 300 fSW Submit Documentation Feedback (29) TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 Short Circuit Protection, RILIM Short circuit protection is programmed using the RILIM resistor. Selection of this resistor depends on the RDS(on) of the switching MOSFET and the required short circuit current trip point, ISCP. The minimum ISCP must exceed the sum of the output current, the peak ripple current, and the output capacitor charging current during start up. Equation 30 gives this minimum. -6 300 ´ (10 ) ´ 1.8 ´ VOUT C + IPK = + 11.05 = 11.32 A ISCP ³ OUT -3 t START 2 ´ (10 ) (30) The minimum short circuit current trip point for this design is set to 14 A. Equation 31 is then used to calculate the minimum RILIM value. RILIM(min ) = RDS(on )(max) ´ ISCP(min ) - VILIMOFSET(min ) I LIM(min) -3 = (4.88 ´ (10 ) ´ 14) + 20mV -6 7.0 ´ (10 ) = 12.6kW (31) RILIM is calculated to be 12.6 kΩ . The closest standard value of 12.7 kΩ is used. The minimum and maximum short circuit current can be calculated using Equation 32 and Equation 33 . IILIM(min ) ´ RILIM(min ) + VILIMOFST(min ) ISCP(min ) = RDS(on )(max ) ISCP(max ) = (32) IILIM(max )´ RILIM(max ) + VILIMOFST(max ) RDS(on)(min ) (33) The minimum ISCP is 14 A and the maximum is 46 A. Voltage Decoupling Capacitors, CBP, and CVDD Two pins on the TPS40195 have DC voltages. It is recommended to add small decoupling capacitors to these pins. Below are the recommended values. • CBP = 4.7 µF • CVDD = 0.1 µF Boost Voltage, CBOOST and DBOOST (optional) Selection of the boost capacitor is based on the total gate charge of the switching MOSFET and the allowable ripple on the boost voltage, VBOOST. A ripple of 0.2 V is assumed for this design. Using these two parameter and equation (26) the minimum value for CBOOST can be calculated. CBOOST > Qg(TOT ) ΔVBOOST (34) The total gate charge of the switching MOSFET is 13.3 nC. A minimum CBOOST of 0.066-µF is required. A 0.1-µF capacitor was chosen. This capacitor must be able to withstand the maximum input voltage plus the maximum voltage on BP. This is 16 V plus 5.4 V which is 21.4 V. A 50-V capacitor is used. To reduce losses in the TPS40195 and to increase the available gate voltage for the switching MOSFET an external diode can be added between the BP pin and the BOOST pin of the device. A small signal schottky should be used here, such as the BAT54. Closing the Feedback Loop RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2 AND CPZ1 A graphical method is used to select the compensation components. This is a standard feedforward buck converter. Its PWM gain is given by the following equation. K PW M @ VIN VRAMP (35) Submit Documentation Feedback 25 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 The gain of the output LC filter is given in Equation 36. KLC = (1 + s´ ESR´ COUT ) æL ö 2 1 + s ´ ç OUT ÷ + (s ) ´ LOUT ´ COUT è ROUT ø (36) The equation for the PWM and LC gain is: Ge (s) = KPWM ´ KLC = VIN VRAMP ´ (1 + s´ ESR´ COUT ) æL ö 2 1 + s´ ç OUT ÷ + (s ) ´ LOUT ´ COUT R è OUT ø (37) To plot this on a Bode plot the DC gain must be expressed in dB. The DC gain is equal to KPWM. To express this in dB we take its LOG and multiple by 20. For this converter the DC gain is: æ VIN ö DC gain = 20 ´ LOG ç ÷ = 20 ´ LOG(12) = 21.6 dB è VRAMP ø (38) Also the pole and zero frequencies should be calculated. A double pole is associated with the LC and a zero is associated with the ESR of the output capacitance. The frequency at where these occur can be calculated using Equation 39. fLC_Pole = 1 2p ´ LOUT ´ COUT fESR_Zero = = 5.8k Hz (39) 1 = 990k Hz 2p ´ ESR´ COUT (40) A Bode plot of the PWM and LC filter is shown in Figure 25. 30 Double Pole 20 10 Gain − dB 0 −10 L−C Slope 40 dB/decade −20 −30 −40 −50 −60 100 1k 10 k 100 k 1M f − Frequency − Hz Figure 25. PWM and L-C Filter Gain A Type-III compensation network, shown in Figure 26, is used for this design. A typical bode plot of a Type-III compensation network is shown below in Figure 27. 26 Submit Documentation Feedback TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 RP1 40 CPZ TPS40195 RZ1 2 30 FB CZ2 RPZ2 3 COMP Gain − dB 20 CPZ 10 High−Frequency Gain RSET 0 −10 −20 100 1 k fZ1 fZ2 fP1 fP2 1M f − Frequency − Hz Figure 26. Type III Compensation Schematic Figure 27. Type-III Compensation Network Typical Bode Plot The output voltage, the high-frequency gain and the break (pole and zero) frequencies are calculated using the following equations. RSET = R SET = (VREGF ´ RZ1 ) (VOUT - VREF ) (41) 0.591 ´ 51k W = 24.9 k W 1.8 - 0.591 (42) æ æ öö 1 RPZ2 ´ ç R Z1 + RP1 + ç ÷÷ ÷ ç è 2pfc ´ CPZ1 ø ø è Gain = æ ö 1 R Z1 ç RP1 + ÷ 2pfC ´ CPZ1 ø è fP1 = fP 2 = fZ1 = fZ 2 = (43) 1 2p ´ RP1´ CPZ1 (44) CP 2 + CZ 2 1 » 2p ´ RPZ 2 ´ CP 2 ´ CZ 2 2p ´ RPZ 2 ´ CP 2 (45) 1 2p ´ R Z1´ CPZ1 (46) 1 1 » 2 p ´ (R PZ 2 + R P1 ) ´ C Z 2 2 p ´ R PZ 2 ´ C Z 2 (47) Steps in closing the feedback loop. 1. Place one zero well below the L-C double pole at 5.8 kHz (fZ1=2.1 kHz) 2. Place the second zero near the double pole fZ2 at 5.8 kHz. 3. Place one pole well above the desired cross over frequency, selected as one sixth the switching frequency, fCO1 = 50 kHz, fP1 = 300 kHz Submit Documentation Feedback 27 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 4. Place the second pole near the ESR pole of the output capacitors of 338 kHz. fP2 = 338 kHz 5. The high frequency gain must be such that the over all system has 0 dB at the required crossover frequency. This gain is -1 times the sum of the modulator gain and the gain of the output stage at the crossover frequency of 50 kHz. Using these values and the above equations calculate the set point and the Rs and Cs around the compensation network using the following procedure. 1. Set RZ1 = 51 kΩ 2. Calculate RSET using Equation 41. For this module RSET = a standard 1% value = 24.9 kΩ. 3. Using Equation 46 and fZ1 = 1.8 kHz, CPZ1 can be calculated to be 1500 pF, FP1 and Equation 44 yields RP1 to be 363 Ω and the standard value 357 Ω is used. 4. From Figure 25, the required gain is calculated at 15.8 dB. Equation 43 sets the value for RPZ2. A resistor for RPZ2 with value of 12.7 kΩ is used. CZ2 is calculated using Equation 47 and the desired frequency for the second zero, CZ2 = 1475 pF. A 2200 pF capacitor is used. 5. CP2 is calculated using the second pole frequency and Equation 45, CP2 = 37 pF. A 33-pf capacitor is used. 200 30 180 25 160 140 120 PHASE GAIN 15 100 80 10 60 40 5 20 0 100 1k 10 k fSW - Switching Frequency - kHz Figure 28. Final Bode Plot 28 Submit Documentation Feedback 0 100 k Phase - ° Gain - dB 20 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 Design Example 2 This example demonstrates the performance of the TPS40195 in a design that produces 5 A of output current at a user selectable voltage of 3.3 V. The input for this design is 12 V ±10%. + Figure 29. Design Example 2 Schematic EFFICIENCY vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 3.316 VIN 3.315 13.2 V 12.0 V 10.8 V h - Efficiency - % VOUT - Output Voltage - V 3.314 VIN 3.313 3.312 3.311 3.310 3.309 3.308 3.307 10.8 V 12.0 V 13.2 V 3.306 3.305 0 2 4 6 IOUT - Load Current - A 8 10 0 Figure 30. 2 4 6 IOUT - Load Current - A 8 10 Figure 31. Submit Documentation Feedback 29 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 Table 4. Design Example 2 Bill of Materials QTY RefDes Value Description Size Part Number MFR 1 C1 25 µF Capacitor, Aluminun, 25V, SM ±20% 0.406 in × 0.457 in EEVFK1E471P Panasonic 2 C2 22 µF Capacitor, Ceramic, 16V, XR5, 20% 0603 Std Std 1 C4 8.2 nF Capacitor, Ceramic, 16V, X7R, 10% 0603 Std Std 1 C5 220 pF Capacitor, Ceramic, 16V, X7R, 10% 0603 Std Std 3 C6, C7, C13 100 nF Capacitor, Ceramic, 16V, X7R, 10% 0603 Std Std 1 C8 1 nF Capacitor, Ceramic, 50V, X7R,10% 0805 Std Std 1 C9 47 µF Capacitor, Ceramic, 6.3V, X5R, 20% 1210 C3225X5R0J476M TDK 1 C12 4.7 µF Capacitor, Ceramic, 10V, X5R, 10% 1 C14 1 nF Capacitor, Ceramic, 16V, X7R, 10% 1 L1 800 nH Inductor, SMT, 31A 1- Q1 Si7860DP 1 Q2 3 Std Std 0603 Std Std 0.512 × 0.571 inch PG0077.801 Pulse MOSFET, N-Ch, 30V, 15A, 11mΩ SOT-8 PWRPAK Si7860DP Vishay Si7868DP MOSFET, N-Ch, 20V, 2.75 mΩ, 25 A SOT-8 PWRPAK Si7868DP Vishay R2, R3, R6 2.32 kΩ Resistor, Chip, 1/16W, 5% 0603 Std Std 1 R5 2.2 kΩ Resistor, Chip, 1/16W, 5% 0603 Std Std 1 R7 7.5 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R9 100 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R10 49.9 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R11 10 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std 1 U1 TPS40195PW 4.5-V to 20-V Synchronous Buck Controller TSSOP-16 TPS40195PW TI 30 Submit Documentation Feedback TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 Design Example 3 This design delivers 1 A to 3 A from a 10 V supply. The output voltage may be adjusted from 1 V to 5 V with a single resistor. The part has 57° of phase margin at a crossover frequency of 59 kHz. The design is built on a double sided PC board with an active area of 1.5 cm × 3 cm. Figure 32. Design Example 3 Schematic GAIN AND PHASE vs FREQUENCY 30 60 120 25 50 100 15 PHASE GAIN 30 60 20 40 Phase - ° 80 40 20 Gain - dB h - Efficiency - % EFFICIENCY vs LOAD CURRENT 10 5 9V 10 V 11 V 0 100 0 0 0.5 1.0 1.5 2.0 2.5 IOUT - Load Current - A 3.0 20 10 VIN 3.5 Figure 33. 1k 10 k 100 k 0 100 k fSW - Switching Frequency - Hz Figure 34. Submit Documentation Feedback 31 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 Table 5. Example 3 Bill of Materials QTY RefDes Value Description Size Part Number MFR 1 C1 22 µF Capacitor, Aluminun, 16V, X7R, 20% 1210 Std TDK 2 C2 22 µF Capacitor, Ceramic, 16V, XR5, 20% 1210 Std TDK 1 C4 4700 pF Capacitor, Ceramic, 25V, X7R, 20% 0402 Std Std 1 C5 10 pF Capacitor, Ceramic, 25V, X7R, 20% 0402 Std Std 2 C6, C7 100 nF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std 1 C8 2.2 nF Capacitor, Ceramic, 25V, X7R, 20% 0402 Std Std 1 C12 4.7 µF Capacitor, Ceramic, 6.3V, X5R, 20% 0603 Std Std 1 C13 10 pF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std 1 C14 470 pF Capacitor, Ceramic, 25V, X7R, 20% 0402 Std Std 4 C15 10 µF Capacitor, Ceramic, 6.3V, X5R, 20% 0805 C2012X5R0J106M TDK 1 L2 15 µH Inductor, SMT, 4.2A, 24 mΩ, 0.394 × 0.3941 inch SLF120565T-150M4R2-PF TDK 1 Q1 SP8K4 XSTR, MOSFET, Dual N-Ch,30V, 9A SOP-8 SP8K4 Rohm 1 Q2 2N7002DICT MOSFET, N-Ch, 60V, 115mA, 1.2Ω SOT-23 2N7002DICT Vishay 1 R2 24.3 kΩ Resistor, Chip, 1/16W, x% 0402 Std Std 1 R3 178 kΩ Resistor, Chip, 1/16W, x% 0402 Std Std 1 R5 11 kΩ Resistor, Chip, 1/16W, x% 0402 Std Std 1 R7 10.1 kΩ Resistor, Chip, 1/16W, x% 0402 Std Std 1 R9 39 kΩ Resistor, Chip, 1/16W, x% 0402 Std Std 1 R10 2.2 kΩ Resistor, Chip, 1/16W, x% 0402 Std Std 2 R11, R13 51 kΩ Resistor, Chip, 1/16W, x% 0402 Std Std 1 R14 20 kΩ Resistor, Chip, 1/16W, x% 0402 Std Std 1 U1 TPS40195PW 4.5-V to 20-V Synchronous Buck Controller TSSOP-16 TPS40195PW TI 32 Submit Documentation Feedback TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 ADDITIONAL REFERENCES Related Parts The following parts have characteristics similar to the TPS40195 and may be of interest. Related Parts DEVICE DESCRIPTION TPS40100 Midrange Input Synchronous Controller with Advanced Sequencing and Output Margining TPS40075 Wide Input Synchronous Controller with Voltage Feed Forward TPS40190 Low Pin Count Synchronous Buck Controller References These references may be found on the web at www.power.ti.com under Technical Documents. Many design tools and links to additional references, including design software, may also be found at www.power.ti.com 1. Under The Hood Of Low Voltage DC/DC Converters, SEM 1500 Topdevice 5, 2002 Seminar Series 2. Understanding Buck Power Stages in Switchmode Power Supplies, SLVA057, March 1999 3. Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar Series 4. Designing Stable Control Loops, SEM 1400, 2001 Seminar Series 5. Additional PowerPADTM information may be found in Applications Briefs SLMA002 and SLMA004 6. QFN/SON PCB Attachment, Texas Instruments Literature Number SLUA271, June 2002 Submit Documentation Feedback 33 TPS40195 www.ti.com SLUS720 – FEBRUARY 2007 EXAMPLE LAND PATTERN 34 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS40195PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS40195PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS40195PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS40195PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device TPS40195PWR 17-May-2007 Package Pins PW 16 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) MLA 330 12 7.0 5.6 1.6 8 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) TPS40195PWR PW 16 MLA 342.9 336.6 20.6 Pack Materials-Page 2 W Pin1 (mm) Quadrant 12 PKGORN T1TR-MS P MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. 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