LTC4235 Dual 12V Ideal Diode-OR and Single Hot Swap Controller with Current Monitor Description Features Ideal Diode-OR and Inrush Current Control for Redundant Supplies nn Low Loss Replacement for Power Schottky Diodes nn Enables Safe Board Insertion into a Live Backplane nn 9V to 14V Operation nn Current Monitor Output nn Controls N-Channel MOSFETs nn Limits Peak Fault Current in ≤ 1µs nn Adjustable Current Limit with Foldback nn Adjustable Current Limit Fault Delay nn 0.5µs Ideal Diode Turn-On and Turn-Off Time nn Smooth Switchover without Oscillation nn Fault and Power Good Outputs nn LTC4235-1: Latch Off After Fault nn LTC4235-2: Automatic Retry After Fault nn 20-Pin 4mm x 5mm QFN Package The LTC®4235 offers ideal diode-OR and Hot SwapTM functions for two 12V power rails by controlling external N-channel MOSFETs. MOSFETs acting as ideal diodes replace two high power Schottky diodes and the associated heat sinks, saving power and board area. A Hot Swap control MOSFET allows a board to be safely inserted and removed from a live backplane by limiting inrush current. The supply output is also protected against short-circuit faults with a foldback current limit and circuit breaker. nn The LTC4235 regulates the forward voltage drop across the MOSFETs to ensure smooth current transfer from one supply to the other without oscillation. The ideal diodes turn on quickly to reduce the load voltage droop during supply switchover. If the input supply fails or is shorted, a fast turn-off minimizes reverse-current transients. A current sense amplifier translates the voltage across the sense resistor to a ground referenced signal. The LTC4235 allows turn-on/off control, and reports fault and power good status for the supply. Applications Redundant Power Supplies High Availability Systems and Servers nn Telecom and Network Infrastructure nn L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7920013, 8022679. nn Typical Application Ideal Diode-OR with Hot Swap Application Smooth Supply Switchover SiR158DP 12V IN2 0.1µF SiR158DP 12V 0.003Ω 0.1µF 13.7k CPO1 IN1 DGATE1 CPO2 SiR158DP + 0.1µF IN2 DGATE2 REG SENSE+ IN1 1V/DIV CLOAD IN2 1V/DIV IIN1 2A/DIV SENSE– HGATE OUT ON FAULT 2k LTC4235 INTVCC 0.1µF GND D2OFF IN1 IIN2 2A/DIV PWRGD IMON EN 12V 7A ADC 200ms/DIV 4235 TA01b FTMR 0.1µF 4235 TA01a 4235f For more information www.linear.com/LTC4235 1 LTC4235 Absolute Maximum Ratings (Notes 1, 2) Supply Voltages IN1, IN2................................................... –0.3V to 24V INTVCC...................................................... –0.3V to 7V REG............................SENSE+ – 5V to SENSE+ + 0.3V Input Voltages ON, D2OFF, EN ....................................... –0.3V to 24V FTMR......................................–0.3V to INTVCC + 0.3V SENSE+, SENSE–.................................... –0.3V to 24V Output Voltages IMON........................................................ –0.3V to 7V FAULT, PWRGD....................................... –0.3V to 24V CPO1, CPO2 (Note 3).............................. –0.3V to 35V DGATE1, DGATE2 (Note 3)...................... –0.3V to 35V HGATE (Note 4)...................................... –0.3V to 35V OUT........................................................ –0.3V to 24V Average Currents FAULT, PWRGD.....................................................5mA INTVCC................................................................10mA Operating Ambient Temperature Range LTC4235C................................................. 0°C to 70°C LTC4235I..............................................–40°C to 85°C Storage Temperature Range................... –65°C to 150°C Pin Configuration OUT HGATE CPO1 DGATE1 TOP VIEW 20 19 18 17 SENSE– 1 16 PWRGD SENSE+ 15 FAULT 2 IN1 3 14 ON 21 INTVCC 4 13 D2OFF 11 IMON 9 10 EN 8 FTMR 7 CPO2 12 REG IN2 6 DGATE2 GND 5 UFD PACKAGE 20-LEAD (4mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 43°C/W (NOTE 5) EXPOSED PAD (PIN 21) PCB GND CONNECTION OPTIONAL Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4235CUFD-1#PBF LTC4235CUFD-1#TRPBF 42351 20-Lead (4mm x 5mm) Plastic QFN 0°C to 70°C LTC4235CUFD-2#PBF LTC4235CUFD-2#TRPBF 42352 20-Lead (4mm x 5mm) Plastic QFN 0°C to 70°C LTC4235IUFD-1#PBF LTC4235IUFD-1#TRPBF 42351 20-Lead (4mm x 5mm) Plastic QFN –40°C to 85°C LTC4235IUFD-2#PBF LTC4235IUFD-2#TRPBF 42352 20-Lead (4mm x 5mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 4235f For more information www.linear.com/LTC4235 LTC4235 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies VIN Input Supply Range l IIN Input Supply Current l VINTVCC Internal Regulator Voltage VINTVCC(UVL) Internal VCC Undervoltage Lockout 9 14 V 2.7 4 mA I = 0, –500µA l 4.5 5 5.5 V INTVCC Rising l 2.1 2.2 2.3 V l 30 60 90 mV l 2 15 28 mV 12 14 V –90 –120 µA ∆VINTVCC(HYST) Internal VCC Undervoltage Lockout Hysteresis Ideal Diode Control ΔVFWD(REG) Forward Regulation Voltage (VINn – VSENSE+) ΔVDGATE External N-Channel Gate Drive (VDGATEn – VINn) ΔVFWD = 0.15V; I = 0, –1µA l 10 l –50 ICPO(UP) CPOn Pull-Up Current CPO = IN = 12V IDGATE(FPU) DGATEn Fast Pull-Up Current ΔVFWD = 0.2V, ΔVDGATE = 0V, CPO = 17V IDGATE(FPD) DGATEn Fast Pull-Down Current ΔVFWD = –0.2V, ΔVDGATE = 5V IDGATE2(DN) DGATE2 Off Pull-Down Current D2OFF = 2V, ΔVDGATE2 = 2.5V l 100 200 µA tON(DGATE) DGATEn Turn-On Delay ΔVFWD = 0.2V , CDGATE = 10nF l 0.25 0.5 µs tOFF(DGATE) DGATEn Turn-Off Delay ΔVFWD = –0.2V, CDGATE = 10nF l 0.2 0.5 µs tPLH(DGATE2) D2OFF Low to DGATE2 High l 50 100 µs 27.5 10.8 mV mV 50 –1.5 A 1.5 A Hot Swap Control ΔVSENSE(TH) Current Limit Sense Voltage Threshold (VSENSE+ – VSENSE–) OUT = 11V OUT = 0V l l 22.5 5.8 25 8.3 VSENSE+(UVL) SENSE+ Undervoltage Lockout SENSE+ Rising l 1.8 1.9 2 V l 10 50 90 mV ∆VSENSE+(HYST) SENSE+ Undervoltage Lockout Hysteresis ISENSE+ SENSE+ Pin Current SENSE+ = 12V l 0.3 0.8 1.3 mA ISENSE – SENSE– Pin Current SENSE– = 12V l 10 40 100 µA ΔVHGATE External N-Channel Gate Drive (VHGATE – VOUT) I = 0, –1µA l 10 12 14 V ΔVHGATE(H) Gate High Threshold (VHGATE – VOUT) l 3.6 4.2 4.8 V IHGATE(UP) External N-Channel Gate Pull-Up Current Gate Drive On, HGATE = 0V l –7 –10 –13 µA IHGATE(DN) External N-Channel Gate Pull-Down Current Gate Drive Off, OUT = 12V, HGATE = OUT + 5V l 1 2 4 mA IHGATE(FPD) External N-Channel Gate Fast Pull-Down Current Fast Turn-Off, OUT = 12V, HGATE = OUT + 5V l 100 200 350 mA VOUT(PGTH) OUT Power Good Threshold OUT Rising l 10.2 10.5 10.8 V ΔVOUT(PGHYST) OUT Power Good Hysteresis l 110 tPHL(SENSE) Sense Voltage (SENSE+ – SENSE–) tOFF(HGATE) High to HGATE Low ON Low to HGATE Low EN High to HGATE Low SENSE+ Low to HGATE Low tD(HGATE) ON High, EN Low to HGATE Turn-On Delay tP(HGATE) ON to HGATE Propagation Delay 170 240 mV ∆VSENSE = 200mV, CHGATE = 10nF l 0.5 1 µs SENSE+ UVLO l l l 10 20 10 20 40 20 µs µs µs 100 150 ms 10 20 µs l ON = Step 0.8V to 2V l 50 4235f For more information www.linear.com/LTC4235 3 LTC4235 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VD2OFF(H,TH) D2OFF Pin High Threshold D2OFF Rising l 1.21 1.235 1.26 V VD2OFF(L,TH) D2OFF Pin Low Threshold D2OFF Falling ΔVD2OFF(HYST) D2OFF Pin Hysteresis l 1.19 1.215 1.24 l 10 20 30 VON(TH) ON Pin Threshold Voltage ON Rising l 1.21 1.235 1.26 VON(RESET) ON Pin Fault Reset Threshold Voltage ΔVON(HYST) ON Pin Hysteresis ON Falling l 0.57 0.6 0.63 V l 40 80 120 mV IIN(LEAK) Input Leakage Current (ON, D2OFF) V = 5V l VEN(TH) EN Pin Threshold Voltage EN Rising l 0 ±1 µA ΔVEN(HYST) EN Pin Hysteresis l 1.185 1.235 1.284 60 110 200 mV IEN(UP) EN Pull-Up Current l –7 VFTMR(H) FTMR Pin High Threshold l 1.198 –10 –13 µA 1.235 1.272 V VFTMR(L) FTMR Pin Low Threshold l 0.15 0.2 0.25 V Inputs EN = 1V V mV V V IFTMR(UP) FTMR Pull-Up Current FTMR = 1V, In Fault Mode l –80 –100 –120 µA IFTMR(DN) FTMR Pull-Down Current FTMR = 2V, No Faults l 1.3 2 2.7 µA DRETRY Auto-Retry Duty Cycle l 0.07 0.15 0.23 % tRST(ON) ON Low to FAULT High l 20 40 µs 100 2.5 170 4 µA mA 0.15 0.4 0.4 1.2 V V Outputs IOUT OUT Pin Current OUT = 11V, IN = 12V, ON = 2V OUT = 13V, IN = 12V, ON = 2V l l VOL Output Low Voltage (FAULT, PWRGD) I = 1mA I = 3mA l l VOH Output High Voltage (FAULT, PWRGD) I = –1µA l IOH Input Leakage Current (FAULT, PWRGD) V = 18V l IPU Output Pull-Up Current (FAULT, PWRGD) V = 1.5V l ΔVREG Floating Regulator Voltage (VSENSE+ – VREG) IREG = ±1µA ΔVSENSE(FS) Input Sense Voltage Full Scale (VSENSE+ – VSENSE–) VIMON(OS) 30 INTVCC –1 INTVCC – 0.5 V 0 ±1 µA –7 –10 –13 µA l 3.6 4.1 4.6 V SENSE+ = 12V l 25 IMON Input Offset Voltage ΔVSENSE = 0V l GIMON IMON Voltage Gain ΔVSENSE = 20mV and 5mV l 99 VIMON(MAX) IMON Maximum Output Voltage ΔVSENSE = 70mV l 3.5 VIMON(MIN) IMON Minimum Output Voltage ΔVSENSE = 200µV l RIMON(OUT) IMON Output Resistance ΔVSENSE = 200µV l Current Monitor Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of the device pins are negative. All voltages are referenced to GND unless otherwise specified. 4 15 mV 100 20 ±150 µV 101 V/V 5.5 V 40 mV 27 kΩ Note 3: An internal clamp limits the DGATE and CPO pins to a minimum of 10V above and a diode below IN. Driving these pins to voltages beyond the clamp may damage the device. Note 4: An internal clamp limits the HGATE pin to a minimum of 10V above and a diode below OUT. Driving this pin to voltages beyond the clamp may damage the device. Note 5: Thermal resistance is specified when the exposed pad is soldered to a 3" x 5", four layer, FR4 board. 4235f For more information www.linear.com/LTC4235 LTC4235 Typical Performance Characteristics SENSE+ Current vs Voltage IN Supply Current vs Voltage OUT Current vs Voltage 1.4 3.5 3 1.2 3 2.5 1 2 VOUT = 0V ISENSE+ (mA) VSENSE+ = VIN – 0.5V VOUT = 12V 1.5 0.8 0.6 1 0.4 0.5 0.2 0 0 3 6 9 VIN (V) 12 15 0 18 14 0 3 6 9 12 15 4235 G01 VIN = 12V 12 9 VOUT (V) 15 18 4235 G03 CPO Voltage vs Current VOUT = VIN 10 12 6 VCPO – VIN (V) 8 ∆VHGATE (V) ∆VHGATE (V) 6 3 12 10 8 4 6 4 2 6 2 0 –2 –4 –6 IHGATE (µA) –8 –10 4 –12 12 0 0 3 6 4235 G04 Diode Gate Voltage vs Current 9 VIN (V) 12 15 14 VSENSE+ = VIN – 0.15V 4 0.6 VSENSE+ = VIN – 0.15V 0.5 10 8 6 0 –20 –40 –60 –80 –100 –120 –140 IDGATE (µA) 4235 G07 4 –60 –80 –100 –120 –140 ICPO (µA) FAULT, PWRGD Output Low Voltage vs Current 2 0 –40 –20 4235 G06 OUTPUT LOW VOLTAGE (V) ∆VDGATE (V) VIN = 12V 6 0 4235 G05 12 8 –2 18 Diode Gate Voltage vs IN Voltage 10 ∆VDGATE (V) 0 4235 G02 Hot Swap Gate Voltage vs IN Voltage VOUT = VIN 8 –2 1 –0.5 18 10 0 1.5 0 14 12 2 0.5 VSENSE+ (V) Hot Swap Gate Voltage vs Current VIN = 12V, VSENSE+ = 11.5V 2.5 IOUT (mA) 3.5 IIN (mA) TA = 25°C, VIN = 12V, unless otherwise noted. 0.4 0.3 0.2 0.1 0 3 6 9 VIN (V) 12 15 18 4235 G08 0 0 1 2 3 CURRENT (mA) 4 5 4235 G09 4235f For more information www.linear.com/LTC4235 5 LTC4235 Typical Performance Characteristics Current Limit Delay vs Sense Voltage Current Limit Threshold Foldback 100 15 10 5 10 1 0 2 4 6 8 10 0.1 12 4235 G10 25 20 15 10 0 0 –50 80 120 40 160 200 SENSE VOLTAGE (VSENSE+ – VSENSE –) (mV) 101 IMON VOLTAGE GAIN (V/V) 1 0 10 30 50 20 40 SENSE VOLTAGE (VSENSE+ – VSENSE–) (mV) 100 99.5 99 –50 100 120 100.5 2 75 IMON Propagation Delay vs Sense Voltage IMON PROPAGATION DELAY (µs) 5 3 0 50 25 TEMPERATURE (°C) 4235 G12 IMON Voltage Gain vs Temperature 4 –25 4235 G11 IMON Voltage vs Sense Voltage –25 25 0 50 TEMPERATURE (°C) 75 4235 G13 100 4235 G14 Ideal Diode Start-Up Waveform on IN Power-Up ON 5V/DIV SENSE+ 10V/DIV HGATE 10V/DIV OUT 10V/DIV CPO 10V/DIV 100 80 60 40 20 0 0 1 3 5 2 4 SENSE VOLTAGE (VSENSE+ – VSENSE–) (mV) 4235 G15 HGATE Start-Up Waveform on ON Toggling High IN 10V/DIV DGATE PWRGD 10V/DIV 10ms/DIV 6 30 5 VOUT (V) IMON VOLTAGE (V) 40 CHGATE = 10nF INPUT OFFSET VOLTAGE (µV) 20 0 Current Sense Amplifier Input Offset Voltage vs Temperature 35 25 CURRENT LIMIT DELAY (µs) CURRENT LIMIT SENSE VOLTAGE VSENSE+ – VSENSE– (mV) 30 0 TA = 25°C, VIN = 12V, unless otherwise noted. 4235 G16 20ms/DIV 4235 G17 4235f For more information www.linear.com/LTC4235 LTC4235 Pin Functions CPO1, CPO2: Charge Pump Output. Connect a capacitor from CPO1 or CPO2 to the corresponding IN1 or IN2 pin. The value of this capacitor is approximately 10x the gate capacitance (CISS) of the external MOSFET for ideal diode control. The charge stored on this capacitor is used to pull up the ideal diode MOSFET gate during a fast turn-on. Leave this pin open if fast ideal diode turn-on is not needed. DGATE1, DGATE2: Ideal Diode MOSFET Gate Drive Output. Connect this pin to the gate of an external N-channel MOSFET for ideal diode control. An internal clamp limits the gate voltage to 12V above and a diode voltage below IN. During fast turn-on, a 1.5A pull-up charges DGATE from CPO. During fast turn-off, a 1.5A pull-down discharges DGATE to IN. D2OFF: Control Input. A rising edge above 1.235V turns off the external ideal diode MOSFET in the IN2 supply path and a falling edge below 1.215V allows the MOSFET to be turned on. Connect this pin to an external resistive divider from IN1 to make IN1 the higher priority input supply when IN1 and IN2 are equal. EN: Enable Input. Ground this pin to enable Hot Swap control. If this pin is pulled high, the Hot Swap MOSFET is not allowed to turn on. A 10µA current source pulls this pin up to a diode below INTVCC. Upon EN going low when ON is high, there is a start-up delay of 100ms for debounce, after which the fault is cleared. FAULT: Overcurrent Fault Status Output. Output that pulls low when the fault timer expires during an overcurrent fault. Otherwise it is pulled high by a 10µA current source to a diode below INTVCC. It may be pulled above INTVCC using an external pull-up. Leave open if unused. FTMR: Fault Timer Capacitor Terminal. Connect a capacitor between this pin and ground to set a 12ms/µF duration for current limit before the external Hot Swap MOSFET is turned off. The duration of the off time is 8s/µF, resulting in a 0.15% duty cycle. GND: Device Ground. HGATE: Hot Swap MOSFET Gate Drive Output. Connect this pin to the gate of the external N-channel MOSFET for Hot Swap control. An internal 10µA current source charges the MOSFET gate. An internal clamp limits the gate voltage to 12V above and a diode voltage below OUT. During an undervoltage generated turn-off, a 2mA pull-down discharges HGATE to ground. During an output short or INTVCC undervoltage lockout, a fast 200mA pull-down discharges HGATE to OUT. IN1, IN2: Positive Supply Input and Ideal Diode MOSFET Gate Drive Return. Connect this pin to the power input side of the external ideal diode MOSFET. The 5V INTVCC supply is generated from IN1, IN2 and OUT via an internal diode-OR. The voltage sensed at this pin is used to control DGATE. The gate fast pull-down current returns through this pin when DGATE is discharged. INTVCC: Internal 5V Supply Decoupling Output. This pin must have a 0.1µF or larger capacitor to GND. An external load of less than 500µA can be connected at this pin. An undervoltage lockout threshold of 2.2V will turn off both MOSFETs. IMON: Current Sense Monitoring Output. This pin voltage is proportional to the sense voltage across the current sense resistor with a voltage gain of 100. An internal 20k resistor is connected from this pin to ground. ON: ON Control Input. A rising edge above 1.235V turns on the external Hot Swap MOSFET and a falling edge below 1.155V turns it off. Connect this pin to an external resistive divider from SENSE+ to monitor the supply undervoltage condition. Pulling the ON pin below 0.6V resets the fault latch after an overcurrent fault. Tie to INTVCC if unused. OUT: Hot Swap MOSFET Gate Drive Return. Connect this pin to the output side of the external MOSFET. The gate fast pull-down current returns through this pin when HGATE is discharged. An internal resistive divider connected between this pin and GND is used for current limit foldback and power good monitor for 12V operation. If the OUT voltage falls below 10.33V, the PWRGD pin pulls high to indicate the power is bad. If the voltage falls below 7.65V, the output current limit is reduced. 4235f For more information www.linear.com/LTC4235 7 LTC4235 Pin Functions PWRGD: Power Status Output. Output that pulls low when the OUT pin rises above 10.5V and the MOSFET gate drive between HGATE and OUT exceeds 4.2V. Otherwise it is pulled high by a 10µA current source to a diode below INTVCC. It may be pulled above INTVCC using an external pull-up. Leave open if unused. REG: Internal Regulated Supply for Current Sense Amplifier. A 0.1µF or larger capacitor should be tied from REG to SENSE+. This pin is not designed to drive external circuits. 8 SENSE+: Positive Current Sense Input. Connect this pin to the diode-OR output of the external ideal diode MOSFETs and input of the current sense resistor. The voltage sensed at this pin is used for monitoring the current limit and also to control DGATE for forward voltage regulation and reverse turn-off. This pin has an undervoltage lockout threshold of 1.9V that will turn off the Hot Swap MOSFET. SENSE–: Negative Current Sense Input. Connect this pin to the output of the current sense resistor. The current limit circuit controls HGATE to limit the voltage between SENSE+ and SENSE– to 25mV or less depending on the voltage at the OUT pin. 4235f For more information www.linear.com/LTC4235 LTC4235 Block Diagram IN1 SENSE+ OUT 150k 20k SENSE– IN2 4.1V FOLDBACK 0.9V HGATE 200Ω + CL – GATE DRIVER 12V REG + CM – IMON OUT 20k 10µA CHARGE PUMP 2 f = 2MHz CHARGE PUMP 1 f = 2MHz CPO1 100µA CPO2 100µA DGATE1 + – + GD2 – GD1 12V 15mV DGATE2 12V 15mV INTVCC 5V LDO INTVCC 10µA 0.6V 1.235V RST HGATE ON PG1 FAULT RESET + – EN – + TM1 – + TM2 100µA 1.235V FTMR 0.2V GND UVLO2 PG2 EN INTVCC – + ON LOGIC – + ON – + UVLO1 – + 1.235V DOFF DGATE2 OFF – + 1.235V + – – + D2OFF INTVCC 10µA 2.2V SENSE+ 1.9V 4.2V HGATE OUT 10.5V INTVCC 10µA PWRGD FAULT 2µA EXPOSED PAD 4235 BD 4235f For more information www.linear.com/LTC4235 9 LTC4235 Operation The LTC4235 functions as an input supply diode-OR with inrush current limiting and overcurrent protection by controlling the external N-channel MOSFETs (MD1, MD2 and MH) on a supply path. This allows boards to be safely inserted and removed in systems with a backplane powered by redundant supplies. The LTC4235 has a single Hot Swap controller and two separate ideal diode controllers, each providing independent control for the two input supplies. When the LTC4235 is first powered up, the gates of the external MOSFETs are held low, keeping them off. As the DGATE2 pull-up can be disabled by the D2OFF pin, DGATE2 will pull high only when the D2OFF pin is pulled low. The gate drive amplifier (GD1, GD2) monitors the voltage between the IN and SENSE+ pins and drives the respective DGATE pin. The amplifier quickly pulls up the DGATE pin, turning on the MOSFET for ideal diode control, when it senses a large forward voltage drop. With the ideal diode MOSFETs acting as input supply diode-OR, the SENSE+ pin voltage rises to the highest of the supplies at the IN1 and IN2 pins. An external capacitor connected at the CPO pin provides the charge needed to quickly turn on the ideal diode MOSFET. An internal charge pump charges up this capacitor at device power-up. The DGATE pin sources current from the CPO pin and sinks current into the IN and GND pins. Pulling the ON pin high and EN pin low initiates a 100ms debounce timing cycle. After this timing cycle, a 10µA current source from the charge pump ramps up the HGATE pin. When the Hot Swap MOSFET turns on, the inrush current is limited at a level set by an external sense resistor (RS) connected between the SENSE+ and SENSE– pins. An active current limit amplifier (CL) servos the gate of the MOSFET to 25mV or less across the current sense resistor depending on the voltage at the OUT pin. Inrush current can be further reduced, if desired, by adding a capacitor from HGATE to GND. When OUT voltage rises above 10.5V and the MOSFET’s gate drive (HGATE to OUT voltage) exceeds 4.2V, the PWRGD pin pulls low. 10 The high side current sense amplifier (CM) provides accurate monitoring of current through the current sense resistor. The sense voltage is amplified by 100 times and level shifted from the positive rail to a ground-referred output at the IMON pin. The output signal is analog and may be used as is or measured with an ADC. When the ideal diode MOSFET is turned on, the gate drive amplifier controls DGATE to servo the forward voltage drop (VIN – VSENSE+) across the MOSFET to 15mV. If the load current causes more than 15mV of voltage drop, the gate voltage rises to enhance the MOSFET. For large output currents, the MOSFET’s gate is driven fully on and the voltage drop is equal to ILOAD•RDS(ON) of the MOSFET. In the case of an input supply short-circuit when the MOSFETs are conducting, a large reverse current starts flowing from the load towards the input. The gate drive amplifier detects this failure condition and turns off the ideal diode MOSFET by pulling down the DGATE pin. In the case where an overcurrent fault occurs on the supply output, the current is limited with foldback. After a delay set by 100µA charging the FTMR pin capacitor, the fault timer expires and pulls the HGATE pin low, turning off the Hot Swap MOSFET. The FAULT pin is also latched low. At this point, the DGATE pin continues to pull high and keeps the ideal diode MOSFET on. Internal clamps limit both the DGATE to IN and CPO to IN voltages to 12V. The same clamp also limits the DGATE and CPO pins to a diode voltage below the IN pin. Another internal clamp limits the HGATE to OUT voltage to 12V and also clamps the HGATE pin to a diode voltage below the OUT pin. Power to the LTC4235 is supplied from either the IN or OUT pins, through an internal diode-OR circuit to a low dropout regulator (LDO). That LDO generates a 5V supply at the INTVCC pin and powers the LTC4235’s internal low voltage circuitry. 4235f For more information www.linear.com/LTC4235 LTC4235 Applications Information High availability systems often employ parallel-connected power supplies or battery feeds to achieve redundancy and enhance system reliability. Power ORing diodes are commonly used to connect these supplies at the point of load at the expense of power loss due to significant diode forward voltage drop. The LTC4235 minimizes this power loss by using external N-channel MOSFETs as the pass elements, allowing for a low voltage drop from the supply to the load when the MOSFETs are turned on. When an input source voltage drops below the output common supply voltage, the appropriate MOSFET is turned off, thereby matching the function and performance of an ideal diode. By adding a current sense resistor and a Hot Swap MOSFET after the parallel-connected ideal diode MOSFETs, the LTC4235 enhances the ideal diode performance with inrush current limiting and overcurrent protection (see Figure 1). This allows the board to be safely inserted and removed from a live backplane without damaging the connector. highest of the supplies at the IN and OUT pins to power the device through the LDO. The diode-OR scheme permits the device’s power to be kept alive by the OUT voltage when the IN supplies have collapsed or shut off. An undervoltage lockout circuit prevents all of the MOSFETs from turning on until the INTVCC voltage exceeds 2.2V. A 0.1µF capacitor is recommended between the INTVCC and GND pins, close to the device for bypassing. No external supply should be connected at the INTVCC pin so as not to affect the LDO’s operation. A small external load of less than 500µA can be connected at the INTVCC pin. Turn-On Sequence The board power supply at the OUT pin is controlled with external N-channel MOSFETs (MD1, MD2 and MH) in Figure 1. The ideal diode MOSFETs connected in parallel on the supply side function as a diode-OR, while MH on the load side acts as a Hot Swap MOSFET controlling the power supplied to the output load. The sense resistor RS monitors the load current for overcurrent detection. The HGATE capacitor CHG controls the gate slew rate to limit the inrush current. Resistor RHG with CHG compensates the current control loop, while RH prevents high frequency oscillations in the Hot Swap MOSFET. Internal VCC Supply The LTC4235 operates with an input supply from 9V to 14V. The power supply to the device is internally regulated at 5V by a low dropout regulator (LDO) with an output at the INTVCC pin. An internal diode-OR circuit selects the Figure 1. Card Resident Diode-OR with Hot Swap Application MD1 SiR158DP VIN1 12V Z1 SMAJ15A VIN2 12V C2 0.1µF RS 0.003Ω MD2 SiR158DP MH SiR158DP + Z2 SMAJ15A RH 10Ω C3 0.1µF RHG 1k CHG 10nF C4 0.1µF R2 13.7k R1 2k C5 0.1µF CPO1 ON CARD CONNECTOR IN2 DGATE2 REG SENSE+ SENSE– HGATE INTVCC GND D2OFF C1 0.1µF OUT R3 100k R4 100k FAULT PWRGD LTC4235 EN BACKPLANE CONNECTOR IN1 DGATE1 CPO2 CL 680µF 12V 7A IMON FTMR CFT 0.1µF ADC 4235 F01 4235f For more information www.linear.com/LTC4235 11 LTC4235 Applications Information During a normal power-up, the ideal diode MOSFETs turn on first. As soon as the internally generated supply, INTVCC, rises above its 2.2V undervoltage lockout threshold, the internal charge pump is allowed to charge up the CPO pins. Because the ideal diode MOSFETs are connected in parallel as a diode-OR, the SENSE+ pin voltage approaches the highest of the supplies at the IN1 and IN2 pins. The MOSFET associated with the lower input supply voltage will be turned off by the corresponding gate drive amplifier. Before the Hot Swap MOSFET can be turned on, EN must remain low and ON must remain high for a 100ms debounce timing cycle to ensure that any contact bounces during the insertion have ceased. At the end of the debounce cycle, the internal fault latch is cleared. The Hot Swap MOSFET is then allowed to turn on by charging up HGATE with a 10µA current source from the charge pump. The voltage at the HGATE pin rises with a slope equal to 10µA/CHG and the supply inrush current flowing into the load capacitor CL is limited to: I INRUSH = CL •10µA CHG The OUT voltage follows the HGATE voltage when the Hot Swap MOSFET turns on. If the voltage across the current sense resistor RS becomes too high based on the OUT pin voltage, the inrush current will be limited by the internal current limiting circuitry. Once the MOSFET gate overdrive exceeds 4.2V and the OUT pin voltage is above 10.5V, the PWRGD pin pulls low to indicate that the power is good. Once OUT reaches the input supply voltage, HGATE continues to ramp up. An internal 12V clamp limits the HGATE voltage above OUT. When the ideal diode MOSFET is turned on, the gate drive amplifier controls the gate of the MOSFET to servo the forward voltage drop across the MOSFET to 15mV. If the load current causes more than 15mV of drop, the MOSFET gate is driven fully on and the voltage drop is equal to ILOAD•RDS(ON). 12 Turn-Off Sequence The external MOSFETs can be turned off by a variety of conditions. A normal turn-off for the Hot Swap MOSFET is initiated by pulling the ON pin below its 1.155V threshold (80mV ON pin hysteresis), or pulling the EN pin above its 1.235V threshold. Additionally, an overcurrent fault that exceeds the fault timer period also turns off the Hot Swap MOSFET. Normally, the LTC4235 turns off the MOSFET by pulling the HGATE pin to ground with a 2mA current sink. All of the MOSFETs turn off when INTVCC falls below its undervoltage lockout threshold (2.2V). The DGATE pin is pulled down with a 100µA current to one diode voltage below the IN pin, while the HGATE pin is pulled down to the OUT pin by a 200mA current. When D2OFF is pulled high above 1.235V, the ideal diode MOSFET in the IN2 power path is turned off with DGATE2 pulled low by a 100µA current. The gate drive amplifier controls the ideal diode MOSFET to prevent reverse current when the input supply falls below SENSE+. If the input supply collapses quickly, the gate drive amplifier turns off the ideal diode MOSFET with a fast pull-down circuit. If the input supply falls at a more modest rate, the gate drive amplifier controls the MOSFET to maintain SENSE+ at 15mV below IN. Board Presence Detect with EN If ON is high when the EN pin goes low, indicating a board presence, the LTC4235 initiates a debounce timing cycle for contact debounce. Upon board insertion, any bounces on the EN pin restart the timing cycle. When the debounce timing cycle is done, the internal fault latch is cleared. If the EN pin remains low at the end of the timing cycle, HGATE is charged up with a 10µA current source to turn on the Hot Swap MOSFET. If the EN pin goes high, indicating a board removal, the HGATE pin is pulled low with a 2mA current sink after a 20µs delay, turning off the Hot Swap MOSFET without clearing any latched fault. 4235f For more information www.linear.com/LTC4235 LTC4235 Applications Information Overcurrent Fault The LTC4235 features an adjustable current limit with foldback that protects the external MOSFET against short circuits or excessive load current. The voltage across the external sense resistor RS is monitored by an active current limit amplifier. The amplifier controls the gate of the Hot Swap MOSFET to reduce the load current as a function of the output voltage sensed by the OUT pin during active current limit. A graph in the Typical Performance Characteristics shows the current limit sense voltage versus OUT voltage. An overcurrent fault occurs when the output has been in current limit for longer than the fault timer period configured at the FTMR pin. Current limiting begins when the sense voltage between the SENSE+ and SENSE – pins reaches 8.3mV to 25mV depending on the OUT pin voltage. The gate of the Hot Swap MOSFET is brought under control by the current limit amplifier and the output current is regulated to limit the sense voltage to less than 25mV. At this point, the fault timer starts with a 100µA current charging the FTMR pin capacitor. If the FTMR pin voltage exceeds its 1.235V threshold, the external MOSFET turns off with HGATE pulled to ground by 2mA and FAULT pulls low. After the Hot Swap MOSFET turns off, the FTMR pin capacitor is discharged with a 2µA pull-down current until its threshold reaches 0.2V. This is followed by a cool-off period of 14 timing cycles as described in the FTMR Pin Functions. Figure 2 shows an overcurrent fault on the 12V output. OUT 10V/DIV HGATE 10V/DIV ILOAD 20A/DIV OUT 10V/DIV HGATE 10V/DIV ILOAD 20A/DIV 5µs/DIV 4235 F03 Figure 3. Severe Short-Circuit on 12V Output In the event of a severe short-circuit fault on the 12V output as shown in Figure 3, the output current can surge to tens of amperes. The LTC4235 responds within 1µs to bring the current under control by pulling the HGATE to OUT voltage down to zero volts. Almost immediately, the gate of the Hot Swap MOSFET recovers rapidly due to the charge stored in the RHG and CHG network and current is actively limited until the fault timer expires. Due to parasitic supply lead inductance, an input supply without any bypass capacitor may collapse during the high current surge and then spike upwards when the current is interrupted. Figure 10 shows the input supply transient suppressors comprising of Z1, RSNUB1, CSNUB1 and Z2, RSNUB2, CSNUB2 for the two supplies if there is no input capacitance. FTMR Pin Functions An external capacitor CFT connected from the FTMR pin to GND serves as fault timing when the supply output is in active current limit. When the voltage across the sense resistor exceeds the foldback current limit threshold (from 25mV to 8.3mV), FTMR pulls up with 100µA. Otherwise, it pulls down with 2µA. The fault timer expires when the 1.235V FTMR threshold is exceeded, causing the FAULT pin to pull low. For a given fault timer period, the equation for setting the external capacitor CFT value is: CFT = tFT • 0.083 [µF/ms] 200µs/DIV 4235 F02 Figure 2. Overcurrent Fault on 12V Output After the fault timer expires, the FTMR pin capacitor pulls down with 2µA from the 1.235V FTMR threshold until it reaches 0.2V. Then, it completes 14 cooling cycles consisting of the FTMR pin capacitor charging to 1.235V with a 4235f For more information www.linear.com/LTC4235 13 LTC4235 Applications Information 100µA current and discharging to 0.2V with a 2µA current. At that point, the HGATE pin voltage is allowed to start up if the fault has been cleared as described in the Resetting Fault section. When the latched fault is cleared during the cool-off period, the FAULT pin pulls high. The total cool-off time for the MOSFET after an overcurrent fault is: tCOOL = CFT • 8 [s/µF] After the cool-off period, the HGATE pin is only allowed to pull up if the fault has been cleared for the latchoff part. For the auto-retry part, the latched fault is cleared automatically following the cool-off period and the HGATE pin voltage is allowed to restart. Resetting Fault (LTC4235-1) For the latchoff part, an overcurrent fault is latched after the fault timer expires and the FAULT pin is asserted low. Only the Hot Swap MOSFET is turned off and the ideal diode MOSFETs are not affected. To reset a latched fault and restart the output, pull the ON pin below 0.6V for more than 100µs and then high above 1.235V. The fault latch resets and the FAULT pin de-asserts on the falling edge of the ON pin. When ON goes high again and the cool-off cycle has completed, a debounce timing cycle is initiated before the HGATE pin voltage restarts. Toggling the EN pin high and then low again also resets a fault, but the FAULT pin pulls high at the end of the debounce cycle before the HGATE pin voltage starts up. Bringing all the supplies below the INTVCC undervoltage lockout threshold (2.2V) shuts off all the MOSFETs and resets the fault latch. A debounce cycle is initiated before a normal start-up when any of the supplies is restored above the INTVCC UVLO threshold. Auto-Retry after a Fault (LTC4235-2) For the auto-retry part, the latched fault is reset automatically at the end of the cool-off period as described in the FTMR Pin Functions section. At the end of the cool-off period, the fault latch is cleared and FAULT pulls high. The HGATE pin voltage is allowed to start up and turn on the Hot Swap MOSFET. If the output short persists, the supply powers up into a short with active current limiting until the fault timer expires and FAULT again pulls low. A 14 new cool-off cycle begins with FTMR ramping down with a 2µA current. The whole process repeats itself until the output short is removed. Since tFT and tCOOL are a function of FTMR capacitance CFT, the auto-retry cycle is equal to 0.15%, irrespective of CFT. Figure 4 shows an auto-retry sequence after an over current fault. FTMR 2V/DIV FAULT 10V/DIV HGATE 20V/DIV OUT 10V/DIV 100ms/DIV 4235 F04 Figure 4. Auto-Retry Sequence After a Fault Monitor Undervoltage Fault The ON pin functions as a turn-on control and an input supply monitor. A resistive divider connected between the supply diode-OR output (SENSE+) and GND at the ON pin monitors the supply for undervoltage condition. The undervoltage threshold is set by proper selection of the resistors at the ON rising threshold voltage (1.235V). For Figure 1, if R1 = 2k, R2 = 13.7k, the input supply undervoltage threshold is set to 9.7V. An undervoltage fault occurs if the diode-OR output supply falls below its undervoltage threshold. If the ON pin voltage falls below 1.155V but remains above 0.6V, the Hot Swap MOSFET is turned off by a 2mA pull-down from HGATE to ground. The Hot Swap MOSFET turns back on instantly without the debounce cycle when the diode-OR output supply rises above its undervoltage threshold. However, if the ON pin voltage drops below 0.6V, it turns off the Hot Swap MOSFET and clears the fault latch. The Hot Swap MOSFET turns back on only after a debounce cycle when the diode-OR output supply is restored above its undervoltage threshold. 4235f For more information www.linear.com/LTC4235 LTC4235 Applications Information During the undervoltage fault condition, FAULT will not be pulled low but PWRGD will be pulled high as HGATE is pulled low. The ideal diode function controlled by the ideal diode MOSFET is not affected by the undervoltage (UV) fault condition. Power Good Monitor Internal circuitry monitors the MOSFET gate overdrive between the HGATE and OUT pins. Also, an internal resistive divider that connects to OUT is used to determine a power good condition. The power good comparator drives high when the OUT pin rises above 10.5V, and drives low when OUT falls below 10.33V. The power good status for the input supply is reported via an open-drain output, PWRGD. It is normally pulled high by an external pull-up resistor or the internal 10µA pull-up. The PWRGD pin pulls low when the OUT power good comparator is high and the HGATE drive exceeds 4.2V. The PWRGD pin goes high when the HGATE is turned off by the ON or EN pins, or when the OUT power good comparator drives low, or when INTVCC enters undervoltage lockout. Current Sense Monitor The current through the external sense resistor is monitored by a LTC4235’s current sense amplifier at the SENSE+ and SENSE– pins (see Figure 5). The amplifier uses autozeroing circuitry to achieve an offset below 150µV over temperature, sense voltage and input supply voltage. The frequency of the auto-zero clock is 10kHz. An internal resistor RIN is connected between the amplifier’s negative input terminal and SENSE+ pin. The sense amplifier loop forces the negative input terminal to have the same potential as SENSE– and that develops a potential across RIN to be the same as the sense voltage VSENSE. A corresponding current, VSENSE/RIN, will flow through RIN. The high impedance inputs of the sense amplifier will not conduct this input current, allowing it to flow through an internal MOSFET to a resistor ROUT connected between the IMON and GND pins. The IMON output voltage is equal to (ROUT/ RIN) • VSENSE. The resistor ratio ROUT/RIN defines the voltage gain of the sense amplifier and is set to 100 with RIN = 200Ω and ROUT = 20k. Full scale input sense voltage to the sense amplifier is 25mV, corresponding to an output of 2.5V. The output clamps at 3.5V if the allowable input sense voltage range is exceeded. IMON Output Filtering A capacitor connected in parallel with ROUT will give a low pass response. This will reduce unwanted noise at the output, and may also be useful as a charge reservoir to keep the output steady while driving a switching circuit such as an ADC (see Figure 5). This output capacitor COUT in parallel with ROUT will create a pole in the output response at: fC = 1 2 • π •ROUT •COUT 12V 0.1µF LTC4235 REG SENSE VSENSE + SENSE– RIN 200Ω 0.1µF 10µF 5V HGATE REF+ I LOAD IMON VOUT LOAD IN ROUT 20k GND 0.1µF ROUT VOUT = ––––– • VSENSE = 100 • VSENSE R IN VCC SCL LTC2451 REF – GND 2-WIRE I2C INTERFACE SDA 4235 F05 Figure 5. High Side Current Monitor with LTC2451 ADC 4235f For more information www.linear.com/LTC4235 15 LTC4235 Applications Information REG Pin Bypassing MOSFET Selection The LTC4235 has an internally regulated supply near SENSE+ for internal bias of the current sense amplifier. It is not intended for use as a supply or bias pin for external circuitry. A 0.1µF capacitor should be connected between the REG and SENSE+ pins. This capacitor should be located very near to the device and close to the REG pin for the best performance. The LTC4235 drives N-channel MOSFETs to conduct the load current. The important features of the MOSFETs are on-resistance RDS(ON), the maximum drain-source voltage BVDSS and the threshold voltage. REG and IMON Start-Up The start-up current of the current sense amplifier when the LTC4235 is powered on consists of two parts: the first is the current necessary to charge the REG bypass capacitor, which is nominally 0.1µF. Since the REG voltage charges to approximately 4.1V below the SENSE+ voltage, this can require a significant amount of start-up current. The second source is the output current that flows into ROUT, which upon start-up may temporarily drive the IMON output high for less than 2ms. This is a temporary condition which will cease when the sense amplifier settles into normal closed-loop operation. CPO and DGATE Start-Up The CPO and DGATE pin voltages are initially pulled up to a diode below the IN pin when first powered up. CPO starts ramping up 7µs after INTVCC clears its undervoltage lockout level. Another 40µs later, DGATE also starts ramping up with CPO. The CPO ramp rate is determined by the CPO pull-up current into the combined CPO and DGATE pin capacitances. An internal clamp limits the CPO pin voltage to 12V above the IN pin, while the final DGATE pin voltage is determined by the gate drive amplifier. An internal 12V clamp limits the DGATE pin voltage above IN. CPO Capacitor Selection The recommended value of the capacitor between the CPO and IN pins is approximately 10× the input capacitance CISS of the ideal diode MOSFET. A larger capacitor takes a correspondingly longer time to charge up by the internal charge pump. A smaller capacitor suffers more voltage drop during a fast gate turn-on event as it shares charge with the MOSFET gate capacitance. 16 The gate drive for the ideal diode and Hot Swap MOSFET is guaranteed to be greater than 10V and is limited to 14V. An external Zener diode can be used to clamp the potential from the MOSFET’s gate to source if the rated breakdown voltage is less than 14V. The maximum allowable drain-source voltage BVDSS must be higher than the supply voltage including supply transients as the full supply voltage can appear across the MOSFET. If an input or output is connected to ground, the full supply voltage will appear across the MOSFET. The RDS(ON) should be small enough to conduct the maximum load current, and also stay within the MOSFET’s power rating. Supply Transient Protection When the capacitances at the input and output are very small, rapid changes in current during input or output short-circuit events can cause transients that exceed the 24V absolute maximum ratings of the IN and OUT pins. To minimize such spikes, use wider traces or heavier trace plating to reduce the power trace inductance. Also, bypass locally with a 10µF electrolytic and 0.1µF ceramic, or alternatively clamp the input with a transient voltage suppressor (Z1, Z2). A 100Ω, 0.1µF snubber damps the response and eliminates ringing (See Figure 10). Design Example As a design example for selecting components, consider a 12V system with a 7A maximum load current for the two supplies (see Figure 1). First, select the appropriate value of the current sense resistor RS for the 12V supply. Calculate the sense resistor value based on the maximum load current ILOAD(MAX) and 4235f For more information www.linear.com/LTC4235 LTC4235 Applications Information the lower limit for the current limit sense voltage threshold ΔVSENSE(TH)(MIN). ΔVSENSE(TH)(MIN) = ILOAD(MAX) 22.5mV = 3.2mΩ 7A Choose a 3mΩ sense resistor with a 1% tolerance. Next, calculate the RDS(ON) of the ideal diode MOSFET to achieve the desired forward drop at maximum load. Assuming a forward drop, ΔVFWD of 30mV across the MOSFET: RDS(ON) ≤ ΔVFWD ILOAD(MAX) = 30mV = 4.2mΩ 7A The SiR158DP offers a good choice with a maximum RDS(ON) of 1.8mΩ at VGS = 10V. The input capacitance CISS of the SiR158DP is about 4980pF. Slightly exceeding the 10× recommendation, a 0.1µF capacitor is selected for C2 and C3 at the CPO pins. Next, verify that the thermal ratings of the selected Hot Swap MOSFET are not exceeded during power-up or an overcurrent fault. Assuming the MOSFET dissipates power due to inrush current charging the load capacitor CL at power-up, the energy dissipated in the MOSFET is the same as the energy stored in the load capacitor, and is given by: ECL = 1 • CL • VIN2 2 The inrush current is set to 1A by adding capacitance CHG at the gate of the Hot Swap MOSFET. CHG = IINRUSH 2 tCHARGE 1 680µF • (12V ) = • = 6W 2 8ms The MOSFET selected must be able to tolerate 6W for 8ms during power-up. The SOA curves of the SiR158DP provide 45W (1.5A at 30V) for 100ms. This is sufficient to satisfy the requirement. The increase in junction temperature due to the power dissipated in the MOSFET is ΔT = PAVG • ZthJC where ZthJC is the junction-to-case thermal impedance. Under this condition, the SiR158DP data sheet indicates that the junction temperature will increase by 3°C using ZthJC = 0.5°C/W (single pulse). Next, the power dissipated in the MOSFET during an overcurrent fault must be safely limited. The fault timer capacitor (CFT) is used to prevent power dissipation in the MOSFET from exceeding the SOA rating during active current limit. A good way to determine a suitable value for CFT is to superimpose the foldback current limit profile shown in the Typical Performance Characteristics on the MOSFET data sheet’s SOA curves. For the SiR158DP MOSFET, this exercise yields the plot in Figure 6. 100 IDM LIMITED 1ms CL • VIN 680µF • 12V = = 8ms IINRUSH 1A CL • IHGATE(UP) ECL 10 For CL = 680µF, the time it takes to charge up CL is calculated as: tCHARGE = PAVG = 680µF • 10µA = = 6.8nF 1A Choose a practical value of 10nF for CHG. ID – DRAIN CURRENT (A) RS = The average power dissipated in the MOSFET is calculated as: 10ms ID LIMITED 100ms LIMITED BY RDS(ON)* 1 1s 10s 0.1 MOSFET POWER DISSIPATION CURVE RESULTING FROM FOLDBACK ACTIVE CURRENT LIMIT 0.01 0.01 DC BVDSS LIMITED 0.1 1 10 VDS – DRAIN-TO-SOURCE VOLTAGE (V) 100 4235 F06 * VGS > MINIMUM VGS AT WHICH RDS(ON) IS SPECIFIED Figure 6. SiR158DP SOA with Design Example MOSFET Power Dissipation Superimposed 4235f For more information www.linear.com/LTC4235 17 LTC4235 Applications Information As can be seen, the LTC4235’s foldback current limit profile roughly coincides with the 100ms SOA contour. Since this SOA plot is for an ambient temperature of 25°C only, a maximum fault timer period of much less than 100ms should be considered, such as 10ms or less. Selecting a 0.1µF ±10% value for CFT yields a maximum fault timer period of 1.75ms which should be small enough to protect the MOSFET during any overcurrent fault scenario. ⎛ VON(TH) ⎞ ⎛ 1.235V ⎞ R1= ⎜ • 0.2% = 2.4k • 0.2% = ⎜ ⎟ ⎝ 1µA ⎟⎠ ⎝ I IN(LEAK) ⎠ Choose R1 to be 2k to achieve less than ±0.2% error and calculating R2 yields: ⎛ VIN(UV) ⎞ R2 = ⎜ – 1⎟ • R1 ⎝ VON(TH) ⎠ Next, select the values for the resistive divider at the ON pin that defines the undervoltage threshold of 9.7V for the 12V supply at SENSE+. Since the leakage current for the ON pin can be as high as ±1µA, the total resistance in the divider should be low enough to minimize the resulting offset error. Calculate the bottom resistor R1 based on the following equation to obtain less than ±0.2% error due to leakage current. ⎛ 9.7V ⎞ R2 = ⎜ – 1⎟ • 2k = 13.7k ⎝ 1.235V ⎠ The final components to consider are a 0.1µF bypass (C1) at the INTVCC pin and a 0.1µF capacitor (C4) connected between the REG and SENSE+ pins. VIA TO GND PLANE • •• Z1 MD1 PowerPAK SO-8 IN1 W • CURRENT FLOW TO LOAD IN2 W S D D G S D D S S D D S G D D S • VIA TO IN1 VIA TO DGATE1 VIA TO C2 (CPO1) MH PowerPAK SO-8 RS • MD2 PowerPAK SO-8 • S D 20 19 18 17 S D S D G D • ••• VIA TO DGATE2 TRACK WIDTH W: 0.03" PER AMPERE ON 1oz Cu FOIL C2 1 16 2 15 • C1 3 • 5 12 6 11 LTC4235UFD 4 OUT 14 13 C4 • Z2 VIA TO C4 (REG) W RH • • CURRENT FLOW TO LOAD VIA TO SENSE+ VIA TO GND PLANE VIA TO GND PLANE 7 • 8 9 C3 10 4235 F08 Figure 7. Recommended PCB Layout for Power MOSFETs and Sense Resistor 18 4235f For more information www.linear.com/LTC4235 LTC4235 Applications Information PCB Layout Considerations To achieve accurate current sensing, a Kelvin connection for the sense resistor is recommended. The PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor and the power MOSFET should include good thermal management techniques for optimal device power dissipation. A recommended PCB layout is illustrated in Figure 7. Connect the IN and OUT pin traces as close as possible to the MOSFETs’ terminals. Keep the traces to the MOSFETs wide and short to minimize resistive losses. The PCB traces associated with the power path through the MOSFETs should have low resistance. The suggested trace width for 1oz copper foil is 0.03" for each ampere of DC current to keep PCB trace resistance, voltage drop and temperature rise to a minimum. Note that the sheet resistance of 1oz copper foil is approximately 0.5mΩ/square, and voltage drops due to trace resistance add up quickly in high current applications. It is also important to place the bypass capacitor C1 for the INTVCC pin, as close as possible between INTVCC and GND. Also place C2 near the CPO1 and IN1 pins, C3 near the CPO2 and IN2 pins, and C4 near the REG and SENSE+ pins. The transient voltage suppressors Z1 and Z2, when used, should be mounted close to the LTC4235 using short lead lengths. Prioritizing Supplies with D2OFF Figure 8 shows an application where the IN1 supply is passed to the output on the basis of priority, rather than simply allowing the highest voltage to prevail. This is achieved by connecting a resistive divider from IN1 at the D2OFF pin to suppress the turn-on of the ideal diode MOSFET MD2 in the IN2 power path. When the IN1 supply voltage falls below 11.4V, it allows the ideal diode MOSFET MD2, to turn on, causing the diode-OR output to be switched from the main 12V supply at IN1 to the auxiliary 12V supply at IN2. This configuration permits the load to be supplied from a lower IN1 supply as compared to IN2 until IN1 falls below the MD2 turn-on threshold. The threshold value used should not allow the IN1 supply to be operated at more than one diode voltage below IN2. Otherwise, MD2 conducts through the MOSFET’s body diode. The resistive divider connected from SENSE+ at the ON pin provides the undervoltage threshold of 9.7V for the diode-OR output supply. MD1 SiR818DP VMAIN 12V Z1 SMAJ15A VAUX 12V C2 0.1µF RS 0.004Ω MD2 SiR818DP MH SiR818DP + Z2 SMAJ15A RH 10Ω C3 0.1µF RHG 1k CHG 10nF C4 0.1µF R2 13.7k R1 2k BACKPLANE CONNECTOR CARD CONNECTOR C5 0.1µF IN1 DGATE1 CPO2 C6 0.1µF IN2 DGATE2 REG SENSE+ SENSE– HGATE 12V 5A VSENSE+ OUT R6 100k R5 100k FAULT PWRGD LTC4235 EN R4 21k R3 2.49k CPO1 ON CL 470µF IMON D2OFF GND INTVCC C1 0.1µF Figure 8. Plug-In Card 12V Prioritized Power Supply at IN1 For more information www.linear.com/LTC4235 ADC FTMR CFT 0.1µF 4235 F08 4235f 19 LTC4235 Applications Information MD1 SiR818DP VMAIN 12V Z1 SMAJ15A VAUX 12V R7 100Ω C2 0.1µF MD2 SiR818DP RS 0.004Ω MD3 SiR818DP MH SiR818DP + Z2 SMAJ15A RH 10Ω C3 0.1µF R2 13.7k C5 0.1µF R1 2k BACKPLANE CONNECTOR CARD CONNECTOR CPO1 ON IN1 DGATE1 CPO2 C4 0.1µF IN2 DGATE2 C6 0.1µF R3 2.49k REG SENSE+ SENSE– HGATE VSENSE+ OUT R6 100k R5 100k FAULT PWRGD LTC4235 EN R4 20k RHG 1k CHG 10nF CL 470µF 12V 5A ADC IMON D2OFF FTMR GND INTVCC 4235 F09 CFT 0.1µF C1 0.1µF Figure 9. 1V Supply Separation from IN2 for Prioritized Power Supply at IN1 Using Back-to-Back MOSFETs MD1 SiR158DP VIN1 12V Z1 SMAJ15A VIN2 12V Z2 SMAJ15A C2 0.1µF RSNUB1 100Ω CSNUB1 0.1µF RS 0.002Ω MD2 SiR158DP MH SiR158DP + RSNUB2 100Ω CSNUB2 0.1µF RH 10Ω C3 0.1µF PWREN R1 10k CPO1 ON IN1 DGATE1 CPO2 CARD CONNECTOR REG SENSE SENSE– HGATE OUT R4 2.7k D2 R3 2.7k D1 FAULT PWRGD LTC4235 EN BACKPLANE CONNECTOR + IN2 DGATE2 VSENSE+ RHG 1k CHG 10nF C4 0.1µF CL 220µF 12V 10A IMON GND INTVCC D2OFF C1 0.1µF ADC 4235 F09 FTMR CFT 0.1µF D1: GREEN LED LN1351C D2: RED LED LN1261CAL Figure 10. 12V, 10A Card Resident Application 20 4235f For more information www.linear.com/LTC4235 LTC4235 Package Description Please refer to http://www.linear.com/product/LTC4235#packaging for the most recent package drawings. UFD Package 20-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1711 Rev B) 0.70 ±0.05 4.50 ±0.05 1.50 REF 3.10 ±0.05 2.65 ±0.05 3.65 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.50 REF 4.10 ±0.05 5.50 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 (2 SIDES) 0.75 ±0.05 PIN 1 NOTCH R = 0.20 OR C = 0.35 1.50 REF R = 0.05 TYP 19 20 0.40 ±0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 ±0.10 (2 SIDES) 2.50 REF 3.65 ±0.10 2.65 ±0.10 (UFD20) QFN 0506 REV B 0.200 REF 0.00 – 0.05 R = 0.115 TYP 0.25 ±0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4235f For more information www.linear.com/LTC4235 21 LTC4235 Typical Application 12V, 5A Backplane Resident Ideal Diode-OR Application with Inrush Current Limiting MD1 SiR158DP VIN1 12V BULK SUPPLY BYPASS CAPACITOR VIN2 12V C2 0.1µF RS 0.004Ω MD2 SiR158DP MH SiR158DP + BULK SUPPLY BYPASS CAPACITOR RH 10Ω C3 0.1µF IN1 DGATE1 CPO2 REG SENSE+ IN2 DGATE2 SENSE– HGATE R2 13.7k R1 2k C5 0.1µF CL 1000µF RHG 1k CHG 10nF C4 0.1µF CPO1 12V 5A OUT FAULT PWRGD EN ON LTC4235 BACKPLANE INTVCC GND D2OFF IMON FTMR CFT 0.1µF C1 0.1µF PLUG-IN CARD ADC 4235 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC4210 Single Channel Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, TSOT23-6 LTC4211 Single Channel Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8, SO-8 or MSOP-10 LTC4215 Single Channel Hot Swap Controller Operates from 2.9V to 15V, I2C Compatible Monitoring, SSOP-16 or QFN-24 LTC4216 Single Channel Hot Swap Controller Operates from 0V to 6V, Active Current Limiting, MSOP-10 or DFN-12 LTC4218 Single Channel Hot Swap Controller Operates from 2.9V to 26.5V, Active Current Limiting, SSOP-16 or DFN-16 LTC4221 Dual Channel Hot Swap Controller Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16 LTC4222 Dual Channel Hot Swap Controller Operates from 2.9V to 29V, I2C Compatible Monitoring, SSOP-36 or QFN-32 LTC4223 Dual Supply Hot Swap Controller Controls 12V and 3.3V, Active Current Limiting, SSOP-16 or DFN-16 LTC4224 Dual Channel Hot Swap Controller Operates from 1V to 6V, Active Current Limiting, MSOP-10 or DFN-10 LTC4227 Dual Ideal Diode and Single Hot Swap Controller Operates from 2.9V to 18V, Controls Three N-Channels, SSOP-16 or QFN-20 LTC4228 Dual Ideal Diode and Hot Swap Controller Operates from 2.9V to 18V, Controls Four N-Channels, SSOP-28 or QFN-28 LTC4229 Ideal Diode and Hot Swap Controller Operates from 2.9V to 18V, Controls Two N-Channels, SSOP-24 or QFN-24 LTC4352 Low Voltage Ideal Diode Controller Operates from 0V to 18V, Controls N-Channel, MSOP-12 or DFN-12 LTC4353 Dual Low Voltage Ideal Diode Controller Operates from 0V to 18V, Controls Two N-Channels, MSOP-16 or DFN-16 LTC4355 Positive High Voltage Ideal Diode-OR and Monitor Operates from 9V to 80V, Controls Two N-Channels, SO-16, DFN-14 or MSOP-16 LTC4357 Positive High Voltage Ideal Diode Controller 22 Linear Technology Corporation Operates from 9V to 80V, Controls N-Channel, MSOP-8 or DFN-6 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC4235 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4235 4235f LT 1115 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2015