TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 LOW PIN COUNT SYNCHRONOUS BUCK CONTROLLER FEATURES • • • • • • • • • • • • • DESCRIPTION Input Operating Voltage Range: 4.5 V to 15 V Reference 0.591 V ±1% Voltage Mode Control Internal 5-V Regulator For Internal Housekeeping, Driver Power and Light External Loads Selectable Short-Circuit Protection Thresholds Pre-Bias Ouput Safe Fixed Switching Frequency of 300 kHz Internal Soft-Start Small 3 mm × 3 mm, 10-Pin SON Package Bootstrapped Drivers for N-Channel MOSFET Adaptive Anti-Cross Conduction Internal Bootstrap Diode 1.2-A Drivers for Decreased Switching Loss The TPS40190 is a cost-optimized synchronous buck controller that operates from 4.5 V to 15 V nominally, and implements a fixed frequency voltage mode power supply. The controller uses an adaptive anti-cross conduction scheme to prevent both the high-side and the rectifier MOSFET to be turned on at the same time, preventing shoot through current in the two MOSFETs. The controller also provides a short circuit protection threshold that is user selectable between one of three values. The protection level is set with a single external resistor connected from COMP to GND. During start-up, the impedance connected to COMP is sensed, and the information is decoded to select one of the three thresholds. When the controller senses an output short circuit, both MOSFETs are turned off and a timeout period is observed before attempting to restart. This provides limited power dissipation in the event of a sustained fault. The TPS40190 provides strong drivers to minimize switching losses in the power stage, reducing heat build up in the MOSFETs and allowing larger MOSFETs to be used without undue switching time penalty. APPLICATIONS • • • • Cable modem CPE Digital Set Top Box Graphics/Audio Cards Entry-level and Mid-Range Servers SIMPLIFIED APPLICATION DIAGRAM VDD TPS40190 1 ENABLE HDRV 10 SHUTDOWN 2 FB SW 9 3 COMP BOOT 8 4 VDD LDRV 7 5 GND BP5 6 VOUT UDG−05059 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 ORDERING INFORMATION (1) TA PACKAGE -40°C to 85°C Plastic DRC (SON) PART NUMBER (1) TPS40190DRCR TPS40190DRCT The TPS40190 is available taped and reeled only. Use large reel device type R to order quantities of 3000 units per reel. Use small reel device type T to order quantities of 250 per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPS40190 VDD Input voltage range VDD –0.3 to 16.5 SW –5 to 22 BOOST-SW, HDRV-SW (differential from BOOST or HDRV to SW) –0.3 to 6 COMP –0.3 to 3 FB, BP5, LDRV, ENABLE V –0.3 to 6 TJ Operating junction temperature range –40 to 125 Tstg Storage temperature –55 to 150 (1) UNIT °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS (1) (2) PACKAGE RθJA High-K Board (1) (°C/W) RθJC (2) (°C/W) DRC 47.9 14.1 The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7.5-cm x 7.5-cm), multilayer board with one-ounce internal power and ground planes and two-ounce copper traces on top and bottom of the board. The junction-to-case impedance is measured from the die to the thermal pad on the device package. RECOMMENDED OPERATING CONDITIIONS MIN NOM MAX UNIT VDD Input voltage 4.5 15 V TA Operating free-air temperature -40 85 °C 2 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, VVDD= 12 Vdc, TA =TJ, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0°C ≤ TJ≤ 85°C 585 591 597 -40°C ≤ TJ≤ 85°C 582 591 597 UNIT REFERENCE VFB Feedback voltage range mV INPUT SUPPLY VVDD Input voltage range IVDD Operating current 4.5 15.0 V VENABLE = 2.5 V, Outputs switching 2.5 mA VENABLE = 0.6 V 20 µA ON BOARD REGULATOR V5VBP Output voltage VVDD > 6 V, I5VBP≤ 10 mA VDO Regulator dropout voltage VVDD - VBP5 , VVDD = 5 V, IBP5≤ 25 mA ISC Regulator current limit threshold IBP5 Average current (1) 5.1 5.3 5.5 V 270 400 mV 40 mA 40 OSCILLATOR fSW Switching frequency VRMP Ramp amplitude (2) VVALLEY Valley voltage (2) 240 300 360 kHz 0.75 V 0.5 PWM DMAX tON(min) tDEAD Maximum duty cycle (2) Minimum controlled 85% pulse (2) Output driver dead time 130 HDRV off to LDRV on 50 LDRV off to HDRV on 25 ns SOFT-START tSS Soft-start time tSSDLY Soft-start delay time (3) tREG Time to regulation 3.0 4.7 7.0 6 ms 10.5 ERROR AMPLIFIER GBWP Gain bandwidth product (2) AOL DC gain (2) IIB Input bias current (current out of FB pin) IEAOP Output source current VFB = 0 V 1 IEAOM Output sink current VFB = 2 V 1 5 MHz 60 dB 100 0 nA mA SHORT CIRCUIT PROTECTION tPSS(min) Minimum pulse during short circuit (2) tBLNK Blanking time (2) tOFF Off-time between restart attempts VILIM Short circuit comparator threshold voltage (1) (2) (3) 250 100 140 25 95 180 ns ms RCOMP(GND) = OPEN, TJ = 25°C 256 320 384 RCOMP(GND) = 4 kΩ, TJ = 25°C 128 160 192 RCOMP(GND) = 12 kΩ, TJ = 25°C 368 460 552 mV 40 mA is the current available for MOSFET gate drive, the device itself and any external loads. The sum of these must not exceed 40 mA. Ensured by design. Not production tested. The delay time is the time delay from application of power to the device or from assertion of ENABLE until the output begins to rise. 3 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VVDD= 12 Vdc, TA =TJ, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 3 6 UNIT OUTPUT DRIVERS RHDHI High-side driver pull-up resistance VBOOT - VSW = 4.5 V, IHDRV = -100 mA RHDLO High-side driver pull-down resistance VBOOT - VSW = 4.5 V, IHDRV = 100 mA 1.5 3.0 RLDHI Low-side driver pull-up resistance ILDRV = -100 mA 2.5 5.0 RLDLO Low-side driver pull-down resistance ILDRV = 100 mA 0.80 1.50 15 35 10 25 15 35 10 25 4.10 4.25 4.40 V 270 320 370 mV (4) tHRISE High-side driver rise time tHFALL High-side driver fall time (4) tLRISE Low-side driver rise time (4) tLFALL Low-side driver fall time (4) CLOAD = 1 nF Ω ns UVLO VUVLO Turn-on voltage UVLOHYST Hysteresis SHUTDOWN VIH High-level input voltage, ENABLE VIL Low-level input votlage, ENABLE 2.8 0.6 V BOOT DIODE VDFWD (4) 4 Bootstrap diode forward voltage Ensured by design. Not production tested. IBOOT = 5 mA 0.6 0.8 1.2 V TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. BOOT 8 I Power supply for the flying high-side driver BP5 6 O Output bypass for the internal regulator. Connect 4.7-µF capacitor from this pin to GND. Low power, low noise loads may be connected here if desired. The sum of the external load and the gate drive requirements must not exceed 40 mA. COMP 3 O Output of the error amplifier. Connecting a resistance from COMP to GND sets the output short circuit detection threshold. See applications information for details. ENABLE 1 I Logic level input that starts or stops the controller from an external user command. A high level turns the controller on. This pin has a high-impedance internal pull-up integrated into the device. Because this pin is high impedance, a 10-nF capacitor to ground or an external pull-up resistor (100 kΩ) to VDD is recommended to avoid noise coupling to this pin. FB 2 I Inverting input to the error amplifier GND 5 - Common connection for the controller HDRV 10 O Bootstrapped output for driving the gate of the high side N channel FET. LDRV 7 O Output to the rectifier FET gate SW 9 I Sense line for the adaptive anti cross conduction circuitry. Serves as common connection for the flying high side FET driver VDD 4 I Power input to the controller DRC PACKAGE (TOP VIEW) GND 5 VDD COMP 4 3 FB ENABLE 2 1 TPS40190DRC 6 BP5 7 8 LDRV BOOT 9 10 SW HDRV 5 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION Introduction The TPS40190 is a cost optimized controller providing all the necessary features to construct a high-performance DC-DC converter while keeping costs to a minimum. Support for pre-biased outputs eliminates concerns about damaging sensitive loads during startup. Strong gate drivers for the high side and rectifier N-channel MOSFETs decrease switching losses for increased efficiency. Adaptive gate drive timing minimizes body diode conduction in the rectifier MOSFET, also increasing efficiency. Selectable short circuit protection thresholds and hiccup recovery from a short-circuit increase design flexibility and minimize power dissipation in the event of a prolonged output fault. A dedicated enable pin (ENABLE) allows the converter to be placed in a very low quiescent current shutdown mode. VDD SC 1.5 MΩ OC + CLK ENABLE 1 FAULT Fault Controller Soft−Start Ramp Generator SD UVLO SC SS Threshold Latch 4.25 V + 5−V Regulator VDD 4 BP5 6 CLK FAULT UVLO Oscillator + Error Amplifier SS + + 8 BOOT 10 HDRV 5V GND 5 FB 2 5V UVLO PWM Logic and Anti−Cross Conduction PWM Comparator 9 SW 5V 7 LDRV SC Threshold Latch 591 mV Short Circuit Threshold Selector SC: 160 mV, 320 mV or 460 mV below VDD COMP 3 TPS40190 UDG−05060 Internally fixed switching frequency and soft-start time reduce external component count, simplifying design and layout, as well as reducing footprint and cost. The 3 mm × 3 mm package size also contributes to a reduced overall converter footprint. Internally Fixed Parameters The TPS40190 has a fixed internal switching frequency of 300 kHz. Soft-start time is fixed at 4.7 ms typical and the UVLO level is set between 4.1 V and 4.4 V. 6 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION (continued) Output Short Circuit Protection The short circuit detection in the TPS40190 is done by sensing the voltage drop across the high side FET when it is on. If the voltage drop across this FET exceeds the selected threshold in any given switching cycle, a counter counts up one count and the FET is turned off early. If the voltage drop across that FET does not exceed this threshold, the counter is decremented for that cycle and the FET is allowed to remain on for the normal pulse width commanded by the internal pulse width modulator. If the counter fills up (a count of 7) a fault condition is declared and the drivers turn both FETs off. After a timeout of approximately 95 ms, the controller attempts to restart. If a short circuit is still present at the output, the current ramps quickly up to the short-circuit threshold and another fault condition is declared. The device then waits 95 ms to attempt to restart again. Typical waveforms during a short circuit event are shown in Figure 1 and Figure 2. VSW (10 V/ div) VOUT (100 mV/ div) VOUT (1 V/ div) T − Time − 10 µs / div IOUT (10 A/ div) IOUT (10 A/ div) T − Time − 10 µs / div Figure 1. Output Short Circuit Detected (Nominal Threshold 25 A) T − Time − 20 ms / div Figure 2. Output Fault Hiccup Restart Timing The TPS40190 provides three selectable short circuit protection thresholds: 160 mV, 320 mV and 460 mV. The particular threshold is selected by connecting a resistor from COMP to GND. Table 1 gives the short circuit thresholds for corresponding resistors from COMP to GND. Note that since the TPS40190 measures the resistance from COMP to GND during a 2-ms window, the compensation network from COMP to FB should have a time constant significantly less than 1 ms or there can be issues detecting the resistance and setting the correct short circuit threshold. This network should have no DC path from COMP to FB. The short circuit detection threshold in the TPS40190 has some temperature compensation built in to help offset the high-side FET rise in resistance as its temperature rises. A typical FET has a resistance temperature coefficient of about 4500 ppm/°C. The temperature coefficient of the short circuit threshold is approximately 4200 ppm/°C. Figure 3 shows how the short circuit threshold increases with temperature to help compensate for the FET resistance increase. The relative FET resistance change is based on an estimate of a linear 4500 ppm/°C temperature coefficient. The effectiveness of this compensation depends on how tight the thermal coupling between the TPS40190 and the high-side FET is. Better thermal coupling between the TPS40190 and the high-side FET gives better compensation effectiveness. 7 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 APPLICATION INFORMATION (continued) Relative Change RELATIVE SHORT CIRCUIT THRESHOLD CHANGE vs TEMPERATURE 1.3 FET Resistance 1.2 1.1 1.0 Short Circuit Threshold Voltage 0.9 0.8 0.7 −50 −25 0 25 50 75 TJ − Junction Temperature − °C 100 Figure 3. Table 1. Short Circuit Threshold Voltage Selection Short Circuit Protection Resistance RCOMP (kΩ) Nominal Current Limit Voltage VILIM (mV) 10.8 to 13.2 460 OPEN 320 3.6 to 4.4 160 The range of short circuit current thresholds that can be expected is given by Equation 1 and Equation 2. V ILIM(max) I SCP(max) + RDS(onMIN) I SCP(min) + RDS(onMAX) where • • • 8 (1) VILIM(min) ISCP is the short circuit current VILIM is the short circuit threshold RDS(on) is the channel resistance of the high-side MOSFET (2) TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 Enable Functionality The TPS40190 has a dedicated ENABLE pin. This simplifies user level interface design since no multiplexed functions exist. Another benefit is a true low power shutdown mode of operation. When the ENABLE pin is pulled to GND, the TPS40190 consumes a typical 20-µA of current. A functionally equivalent circuit to the enable circuitry on the TPS40190 is shown in Figure 4. VDD 4 200 kΩ 1.5 MΩ 1 kΩ ENABLE 1 200 Ω 1 kΩ To Enable Chip 300 kΩ GND 5 UDG−05061 Figure 4. TPS40190 ENABLE Pin Internal Circuitry If the ENABLE pin is left floating, the chip starts automatically. The pin must be pulled to less than 600 mV to guarantee that the TPS40190 is in shutdown mode. Note that the ENABLE pin is relatively high impedance. In some situations, there could be enough noise nearby to cause the ENABLE pin to swing below the 600 mV threshold and give erroneous shutdown commands to the rest of the device. There are two solutions to this problem should it arise. 1. Place a capacitor from ENABLE to GND. A side effect of this is to delay the start of the converter while the capacitor charges past the enable threshold 2. Place a resistor from VDD to ENABLE. This causes more current to flow in the shutdown mode, but does not delay converter startup. If a resistor is used, the total current into the ENABLE pin should be limited to no more than 500 µA. 9 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 Typical waveforms for startup and shutdown using the ENABLE pin are shown in Figure 5 and Figure 6. VENABLE (10 V/ div) VENABLE (5 V/ div) VLDRV (10 V/ div) VCOMP (500 mV/ div) VSW (10 V/ div) VOUT (500 mV/ div) VOUT (500 mV/ div) T − Time − 2 ms / div Figure 5. Startup Using ENABLE Pin T − Time − 20 µs / div Figure 6. Shutdown Using ENABLE Pin 5-V Regulator The TPS40190 has an on board 5-V regulator that allows the part to operate from a single voltage feed. No separate 5-V feed to the part is required. This regulator needs to have 4.7-µF of capacitance on the BP5 pin to guarantee stability. A ceramic capacitor is suggested for this purpose. This regulator can also be used to supply power to nearby circuitry, eliminating the need for a separate LDO in some cases. If this pin is used for external loads, keep in mind that this is the power supply for the internals of the TPS40190. While efforts have been made to reduce sensitivity, any noise induced on this line has an adverse effect on the overall performance of the internal circuitry and shows up as increased pulse jitter, skewed reference voltage, etc. The amount of power available from this pin varies with the size of the power MOSFETs that the drivers must operate. Larger MOSFETs require more gate drive current and reduces the amount of power available on this pin for other tasks. The total amount of current required by the gate drive and the external circuitry should not exceed 40 mA. The current required to drive the FET gates can be found from Equation 3. I G + f SW ǒQG (high) ) QG (low)Ǔ (3) Where • • • • IG is the required gate drive current fSW is the switching frequency (300 kHz) QG(high) is the gate charge requirement for the high-side FET at 5 V VGS QG(low) is the gate charge requirement for the low-side FET at 5 V VGS Startup Sequence and Timing The TPS40190 startup sequence is as follows. After input power is applied, the 5-V onboard regulator comes up. Once this regulator comes up, the TPS40190 goes through a period where it samples the impedance at the COMP pin and decides the short circuit protection threshold voltage. This is accomplished by placing 400 mV on the COMP pin for approximately 2 ms. During this time, the current is measured and compared against internal thresholds to select the short circuit protection threshold. After this, the COMP pin is brought low for 4 ms. This ensures that the feedback loop is preconditioned at startup and no sudden output rise occurs at the output of the converter when the converter is allowed to start switching. After these initial 6 milliseconds, the internal soft-start circuitry is engaged and the converter is allowed to start. See Figure 7. 10 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 Pre-Bias Outputs Some applications require that the converter not sink current during startup if a pre-existing voltage is higher than the output. Since synchronous buck converters inherently sink current some method of overcoming this characteristic must be employed. Applications that require this operation are typically power rails for a multi supply processor or ASIC. The method used in this controller, is to not allow the low side or rectifier FET to turn on until there the output voltage commanded by the start up ramp is higher than the pre-existing output voltage. This is detected by monitoring the internal pulse width modulator (PWM) for its first output pulse. Since this controller uses a closed loop startup, the first output pulse from the PWM does not occur until the output voltage is commanded to be higher than the pre-existing voltage. This effectively limits the controller to sourcing current only during the startup sequence. If the pre-existing voltage is higher than the intended regulation point for the output of the converter, the converter starts and sinks current when the soft-start time has completed. A typical pre-biased startup is shown in Figure 8. VIN (10 V/ div) VOUT 1 V/div VOUT (500 mV/ div) VLDRV (5 V/div) VCOMP (500 mV/ div) T − Time − 2 ms / div Figure 7. TPS40190 Startup Timing t − TIme − 1 ms/div Figure 8. Prebiased Startup Timing Typical Applications Some typical applications. 11 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 110 Ω 12 V 120 µF 10 kΩ 4.7 nF On/Off TPS40190 634 Ω 82 nF 1 ENABLE HDRV 10 2 FB SW 1.33 kΩ 47 µF TDK C3225X5R0J476M 2 22 µF TDK C3225X5R1C226M VOUT 100 nF 3 COMP BOOT 8 4 VDD LDRV 7 5 GND BP5 6 5 V, 10 A 1 Si4874BDY 1 1 4.7 µF 1 µF 1 2 µH, COEV DXM1306 2R0 9 10 nF 820 pF 2 2 Si4874BDY UDG−05072 Figure 9. 12-V to 5-V at 10 A 12 V 137 Ω 120 µF 10 kΩ 3.3 nF TPS40190 Off 12 nF 2.49 kΩ 1 ENABLE 2 FB HDRV 10 SW 2 VOUT 100 nF 3 COMP BOOT 8 4 VDD LDRV 7 5 GND BP5 6 1.2 V, 20 A Si7868ADP 1 1 1 4.7 µF 9.76 kΩ 12.1 kΩ 1 µF 1 100 µF TDK C3225X5R0J107M 2 22 µF TDK C3225X5R1C226M UDG−05073 Figure 10. 12-V to 1.2-V at 20 A 12 2 1.4 µH, Pulse PG0077.142 9 10 nF 180 pF Si7344DP TPS40190 www.ti.com + SLUS658A – JULY 2005 – REVISED AUGUST 2005 Figure 11. PMP1285, 12-V to 1.5-V, at 3.7 A 13 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 Typical Characteristics REFERENCE VOLTAGE vs TEMPERATURE 592.0 REFERENCE VOLTAGE vs INPUT VOLTAGE 591.02 VVDD = 12 V TJ = 25°C 591.00 VVREF − Voltage Reference − V VVREF − Voltage Reference − V 591.5 591.0 590.5 590.0 589.5 589.0 −50 590.98 590.96 590.94 590.92 590.90 590.88 4.5 −25 0 25 50 75 100 6.0 7.5 125 9.0 10.5 12.0 13.5 15.0 VVDD − Input Voltage − V TJ − Junction Temperature − °C Figure 13. OSCILATOR FREQUENCY vs TEMPERATURE OSCILATOR FREQUENCY vs INPUT VOLTAGE 293 VVDD = 12 V 304 302 300 298 296 294 292 290 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C Figure 14. 14 TJ = 25°C 292 fOSC − Oscillator Frequency − kHz fOSC − Oscillator Frequency − kHz 306 Figure 12. 125 291 290 289 288 287 286 4.5 6.0 7.5 9.0 10.5 12.0 VVDD − Input Voltage − V Figure 15. 13.5 15.0 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 Typical Characteristics (continued) OPERATING CURRENT vs TEMPERATURE OPERATING CURRENT vs INPUT VOLTAGE 18 14 IVDD − Operating Current − µA IVDD − Operating Current − µA 16 16 VVDD = 12 V VENABLE < 0.6 V 14 12 10 8 6 2 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C 10 8 6 4 0 4.5 125 9.0 10.5 12.0 Figure 17. ENABLE THRESHOLD ON vs TEMPERATURE ENABLE THRESHOLD ON vs INPUT VOLTAGE 13.5 15.0 1.840 TJ = 25°C 2.0 1.5 1.0 0.5 −25 7.5 Figure 16. VVDD = 12 V 0 −50 6.0 VVDD − Input Voltage − V VIH − Enable Threshold On − V VIH − Enable Threshold On − V 12 2 4 2.5 VENABLE < 0.6 V TJ = 25°C 0 25 50 75 100 TJ − Junction Temperature − °C Figure 18. 125 1.836 1.832 1.828 1.824 1.820 4.5 6.0 7.5 9.0 10.5 12.0 VVDD − Input Voltage − V 13.5 15.0 Figure 19. 15 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 Typical Characteristics (continued) ENABLE THRESHOLD OFF vs TEMPERATURE ENABLE THRESHOLD OFF vs INPUT VOLTAGE 1.4 1.20 VVDD = 12 V TJ = 25°C 1.2 1.0 VIL − Enable Threshold Off − V VIL − Enable Threshold Off − V 1.18 0.8 0.6 0.4 0.2 0 −50 −25 0 25 50 75 100 1.16 1.14 1.12 1.10 4.5 125 6.0 TJ − Junction Temperature − °C SOFT START TIMING vs TEMPERATURE TOTAL STARTUP TIME vs TEMPERATURE 13.5 15.0 100 125 11.6 VVDD = 12 V 11.4 Soft−Start Delay TIme 11.2 t − Time − ms t − Time − ms 12.0 Figure 21. 6.0 5.5 5.0 4.5 11.0 10.8 10.6 10.4 Soft−Start TIme −25 0 10.2 25 50 75 100 TJ − Junction Temperature − °C Figure 22. 16 10.5 Figure 20. VVDD = 12 V 4.0 −50 9.0 VVDD − Input Voltage − V 7.0 6.5 7.5 125 −50 −25 0 25 50 75 TJ − Junction Temperature − °C Figure 23. TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 Typical Characteristics (continued) SOFT START TIMING vs INPUT VOLTAGE CURRENT LIMIT THRESHOLD vs TEMPERATURE 4.700 VILIM − Current Limit Threshold Voltage − mV 4.705 TJ = 25°C tSS − Soft−Start Time − ms 4.695 4.690 4.685 4.680 4.675 4.670 4.665 4.660 4.655 4.5 6.0 7.5 9.0 10.5 12.0 VVDD − Input Voltage − V 13.5 150 100 50 −25 0 25 50 75 Figure 24. Figure 25. CURRENT LIMIT THRESHOLD vs INPUT VOLTAGE CURRENT LIMIT THRESHOLD vs TEMPERATURE VILIM − Current Limit Threshold Voltage − mV VILIM − Current Limit Threshold Voltage − mV 200 TJ = 25°C RCOMP = 4 kΩ 160.6 160.4 160.2 160.0 159.8 159.6 6.0 7.5 9.0 10.5 12.0 VVDD − Input Voltage − V Figure 26. 100 125 TJ − Junction Temperature − °C 160.8 159.4 4.5 VVDD = 12 V RCOMP = 4 kΩ 0 −50 15.0 161.2 161.0 250 13.5 15.0 600 VVDD = 12 V RCOMP = 12 kΩ 500 400 300 200 100 0 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C 125 Figure 27. 17 TPS40190 www.ti.com SLUS658A – JULY 2005 – REVISED AUGUST 2005 Typical Characteristics (continued) CURRENT LIMIT THRESHOLD vs INPUT VOLTAGE 469 450 TJ = 25°C RCOMP = 12 kΩ VILIM − Current Limit Threshold Voltage − mV ViLIM − Current Limit Threshold Voltage − mV 470 CURRENT LIMIT THRESHOLD vs TEMPERATURE 468 467 466 465 464 463 4.5 6.0 7.5 9.0 10.5 12.0 VVDD − Input Voltage − V 13.5 250 200 150 100 50 −25 0 25 50 75 100 125 Figure 29. CURRENT LIMIT THRESHOLD vs INPUT VOLTAGE UNDERVOLTAGE LOCKOUT TURN ON VOLTAGE vs TEMPERATURE 4.238 TJ = 25°C RCOMP = OPEN 4.236 VUVLO − Turn−On Voltage − V VILIM − Current Limit Threshold Voltage − mV 300 Figure 28. 319.5 319.0 318.5 318.0 317.5 6.0 7.5 9.0 10.5 12.0 VVDD − Input Voltage − V Figure 30. 18 350 TJ − Junction Temperature − °C 320.0 317.0 4.5 VVDD = 12 V RCOMP = OPEN 0 −50 15.0 321.0 320.5 400 13.5 15.0 4.234 4.232 4.230 4.228 4.226 4.224 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C Figure 31. 125 PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS40190DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40190DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40190DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40190DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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