INTEGRATED CIRCUITS 74LVC161 Presettable synchronous 4-bit binary counter; asynchronous reset Product specification Supersedes data of 1996 Aug 23 IC24 Data Handbook 1998 May 20 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 The 74LVC161 is a synchronous presettable binary counter which features an internal look–head carry and can be used for high–speed counting. Synchronous operation is provided by having all flip–flops clocked simultaneously on the positive–going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive–going edge of the clock (provided that the set–up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip–flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8–1A • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Asynchronous reset • Synchronous counting and loading • Two count enable inputs for n–bit cascading • Positive edge–triggered clock • Output drive capability 50 transmission lines @85C The look–ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set–up time, according to the following formula: DESCRIPTION The 74LVC161 is a high–performance, low–power, low–voltage, Si–gate CMOS device and superior to most advanced CMOS compatible TTL families. fmax = 1 _______________________________ tp(max) (CP to TC) + tSU (CEP to CP) QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; TR = TF 2.5ns PARAMETER SYMBOL CONDITIONS Propagation delay CP to Qn CP to TC MR to Qn MR to TC CET to TC tPHL/tPLH fMAX CI CPD TYPICAL CL = 50 pF VCC = 3.3V 4.9 5.7 5.2 5.7 4.5 UNIT ns maximum clock frequency 200 MHz input capacitance 5.0 pF 39 pF power dissipation capacitance per gate notes 1 and 2 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD x VCC2 x fi +Σ (CL x VCC2 x fo ) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL x VCC2 x fo ) = sum of the outputs 2. The condition is V1 = GND to VCC ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 16-Pin Plastic SO PACKAGES –40°C to +85°C 74LVC161 D 74LVC161 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +85°C 74LVC161 DB 74LVC161 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC161 PW 74LVC161PW DH SOT403-1 1998 May 20 2 853-1864 19421 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset PIN CONFIGURATION 74LVC161 PIN DESCRIPTION PIN NUMBER SYMBOL 1 MR asynchronous master reset (active LOW) 2 CP clock input (LOW-to-HIGH, edge-triggered) Q2 3,4,5,6 D0 to D3 Q3 7 CEP count enable inputs 10 CET 8 GND ground (0V) 9 PE 9 PE 10 CET 14,13,12,11 Q0 to Q3 MR 1 16 VCC CP 2 15 TC D0 3 14 Q0 D1 4 13 Q1 D2 5 12 D3 6 11 CEP 7 GND 8 SF00656 LOGIC SYMBOL 15 count enable carry input flip-flop outputs TC terminal count output VCC positive supply voltage LOGIC SYMBOL (IEEE/IEC) 1 TC Q0 14 4 D1 Q1 13 7 5 D2 Q2 12 10 6 D3 Q3 11 2 9 PE 10 parallel enable input (active LOW) 16 D0 7 data inputs 15 3 CEP CET FUNCTION CP 2 9 MR 3 1 CTR4 R M1 G3 G4 C2 /1,3,4+ 14 1,2 D 4 13 5 12 6 11 4 CT=15 15 VCC = Pin 16 GND = Pin 8 SY00065 1998 May 20 SY00066 3 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset FUNCTIONAL DIAGRAM FUNCTION TABLE 3 4 5 6 D0 D1 D2 D3 9 PE PARALLEL LOAD CIRCUITRY 10 CET BINARY COUNTER CP 1 MR Q0 Q1 Q2 Q3 14 13 12 11 INPUTS OUTPUTS OPERATING MODES MR CP CEP CET PE Dn Qn TC Reset (clear) L X X X X X L L Parallel load H H ↑ ↑ X X X X l l l h L H L * Count H ↑ h h h X count * Hold (do nothing) H H X X l X X l h h X X qn qn * L NOTES: * = The TC output is High when CET is High and the counter is at Terminal Count (HHHH) H = High voltage level h = High voltage level one setup time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one setup time prior to the Low-to-High clock transition q = Lower case letters indicate the state of the referenced output one setup time prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition TC 15 7 CEP 2 74LVC161 TYPICAL TIMING SEQUENCE SY00068 MR PE STATE DIAGRAM D0 D1 D2 0 1 2 3 4 D3 CP 15 5 14 6 13 7 CEP CET Q0 Q1 Q2 Q3 12 11 10 9 8 TC 12 13 RESET PRESET 14 15 0 COUNT 1 2 INHIBIT SF00664 SY00069 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one, and two; inhibit 1998 May 20 4 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 LOGIC DIAGRAM D1 D0 D2 D3 CET CEP PE FF0 D CP FF1 Q D CP FF2 Q D CP Q D CP Q Q CP Q RD FF3 Q RD Q RD RD MR Q0 Q1 Q2 Q3 TC SY00070 1998 May 20 5 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS LIMITS MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 UNIT V VI DC input voltage range 0 5.5 VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V Tamb Operating free-air temperature range tr, tf Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V V ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC PARAMETER CONDITIONS DC supply voltage RATING UNIT –0.5 to +6.5 V IIK DC input diode current VI 0 –50 mA VI DC input voltage Note 2 –0.5 to +5.5 V IOK DC output diode current VO VCC or VO 0 50 mA VO DC output voltage Note 2 IO DC output source or sink current VO = 0 to VCC IGND, ICC Tstg PTOT DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) –0.5 to VCC +0.5 V 50 mA 100 mA –65 to +150 °C above +70°C derate linearly with 8 mW/K 500 above +60°C derate linearly with 5.5 mW/K 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 May 20 6 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 TYP1 V VCC = 1.2V GND V VCC = 2.7 to 3.6V HIGH level output voltage 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC0.2 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC1.0 VCC VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100µA II ∆ICC Input leakage current VCC = 3 3.6V; 6V; VI = 5 5.5V 5V or GND Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 1998 May 20 7 V 0.40 GND VCC = 3.0V; VI = VIH or VIL; IO = 24mA ICC UNIT MAX 0.20 V 0.55 0 1 0.1 5 µA 0.1 10 µA 5 500 µA Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 500; Tamb = –40C to +85C LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM VCC = 2.7V VCC = 1.2V MIN TYP1 MAX MIN MAX TYP UNIT tPHL tPLH Propagation delay CP to Qn 1 – 4.9 8.0 – 9.0 24 ns tPHL tPLH Propagation delay CP to TC 1 – 5.7 9.5 – 11 28 ns tPHL tPLH Propagation delay CET to TC 2 – 4.5 7.8 – 8.8 22 ns tPHL Propagation delay MR to Qn 3 – 5.2 9.0 – 10 28 ns tPHL Propagation delay MR to TC 3 – 5.7 10 – 11 20 ns tW Clock pulse width HIGH or LOW 1 4.0 1.2 – 5.0 – – ns tW Master reset width LOW 3 3.0 1.6 – 4.0 – – ns trem Removal time MR to CP 3 0 –0.3 – 0 – – ns tsu Set-up time Dn to CP 4 2.5 1.0 – 3.0 – – ns tsu Set-up time PE to CP 4 3.0 1.2 – 3.5 – – ns tsu Set-up time CEP, CET to CP 5 5.0 2.1 – 5.5 – – ns th Hold time Dn, PE, CEP, CET to CP 4, 5 0 –1.7 – 0 – – ns 1 125 200 – 110 – – MHz fmax Maximum clock pulse frequency NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25°C. 1998 May 20 8 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 AC WAVEFORMS VM = 1.5 V at VCC 2.7 V VM = 0.5 S VCC at VCC < 2.7 V VOL and VOH are the typical output voltage drop that occur with the output load. VI PE INPUT GND VM tSU CP INPUT 1/fMAX tSU th VI th VM GND VI CP INPUT GND tSU VM VI VOH Dn INPUT tPLH tw tPHL tSU th VM GND VM Qn, TC OUTPUT VOL The shaded areas indicate when the input is permitted to change for predictable output performance. SC00137 Waveform 4. Setup and hold times for the input (Dn) and parallel enable input (PE). SY00071 Waveform 1. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock frequency. VI CEP, CET INPUT GND VM VI tsu CET INPUT tsu th th VI VM GND tPLH VM CP INPUT tPHL VM GND VOH VM TC OUTPUT VOL NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SC00138 SY00072 Waveform 2. th Waveform 5. Input (CET) to output (TC) propagation delays. CEP and CET setup and hold times. TEST CIRCUIT MR INPUT GND S1 VCC VI VM 2 * VCC Open GND 500Ω tw trem VO VI VI PULSE GENERATOR CP INPUT GND D.U.T. 50pF RT CL tPHL 500Ω VOH Qn, TC OUTPUT VOL VM SWITCH POSITION TEST SY00073 tPLH/tPHL Waveform 3. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master reset to clock (CP) removal times. S1 Open VCC VI < 2.7V VCC 2.7–3.6V 2.7V SV00903 Waveform 6. 1998 May 20 9 Load circuitry for switching times. Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset SO16: plastic small outline package; 16 leads; body width 3.9 mm 1998 May 20 10 74LVC161 SOT109-1 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1998 May 20 11 74LVC161 SOT338-1 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 1998 May 20 12 74LVC161 SOT403-1 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset NOTES 1998 May 20 13 74LVC161 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04496