INTEGRATED CIRCUITS 74LV109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger FEATURES 74LV109 DESCRIPTION • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. Tamb = 25°C The 74LV109 is a dual positive-edge triggered JK-type flip-flop featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. Tamb = 25°C The set and reset are asynchronous active LOW inputs and operate independently of the clock input. • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, • Output capability: standard • ICC category: flip-flops The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns PARAMETER TYPICAL UNIT 14 12 12 ns Maximum clock frequency 77 MHz Input capacitance 3.5 pF 20 pF SYMBOL tPHL/tPLH fmax CI CPD Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ CONDITIONS CL = 15 pF; VCC = 3.3 V Power dissipation capacitance per flip-flop VI = GND to VCC 1 NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA 16-Pin Plastic DIL PACKAGES –40°C to +125°C 74LV109 N 74LV109 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV109 D 74LV109 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV109 DB 74LV109 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV109 PW 74LV109PW DH SOT403-1 PIN CONFIGURATION 1R D 1 PIN DESCRIPTION 16 V CC 1J 2 15 2R 1K 3 14 2J PIN NUMBER D 1CP 4 13 2K 1S D 5 12 2CP 1Q 6 11 2S 1Q 7 10 2Q GND 8 9 2Q D SV00517 1998 Apr 20 PKG. DWG. # 2 SYMBOL FUNCTION 1, 15 1RD, 2RD Asynchronous reset input (active LOW) 2, 14, 3, 13 1J, 2J, 1K, 2K Synchronous inputs; flip-flops 1 and 2 4, 12 1CP, 2CP Clock input (LOW-to-HIGH, edge-triggered) 5, 11 1SD, 2SD Asynchronous set inputs (active LOW) 6, 10 1Q, 2Q True flip-flop outputs 7, 9 1Q, 2Q Complement flip-flop outputs 8 GND Ground (0 V) 16 VCC Positive supply voltage 853-1986 19255 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger LOGIC SYMBOL (IEEE/IEC) 5 FUNCTIONAL DIAGRAM 11 S 5 1SD 2 1J S 6 2 10 14 1J 1J 4 C1 7 Q 1Q 7 11 2SD R (a) 6 RD 15 R K 1Q 1 1RD 1K 1 Q 1K 9 13 1K J FF1 3 C1 SD 4 1CP CP 12 3 74LV109 SD (b) 14 2J J SV00519 12 2CP CP FF2 13 2K K LOGIC SYMBOL 2Q 10 Q Q 2Q 9 RD 5 11 1S D 2S D 15 2RD SV00520 2 1J J 1Q 6 14 2J Q 2Q 10 4 1CP 12 2CP CP 1Q 7 3 1K 13 2K Q K 2Q 9 1R D 2R D 1 15 SV00518 LOGIC DIAGRAM K C C C C Q Q J C C C C S R CP C C SV00521 1998 Apr 20 3 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LV109 FUNCTION TABLE INPUTS OPERATING MODES OUTPUTS nSD nRD nCP nJ nK nQ nQ Asynchronous set Asynchronous reset Undetermined L H L H L L X X X X X X X X X H L H L H H Toggle H H ↑ h l q q Load “0” (reset) Load “1” (set) Hold “no change” H H H H H H ↑ ↑ ↑ l h l l h h L H q H L q NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition. X = don’t care ↑ = LOW-to-HIGH CP transition RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP. MAX UNIT See Note 1 1.0 3.3 3.6 V DC supply voltage VI Input voltage 0 – VCC V VO Output voltage 0 – VCC V +85 +125 °C 500 200 100 ns/V Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times except for Schmitt-trigger inputs See DC and AC characteristics -40 -40 VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V – – – – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL PARAMETER CONDITIONS RATING UNIT VCC DC supply voltage –0.5 to +4.6 V "IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA "IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA "IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 "IGND, "ICC Tstg PTOT DC VCC or GND current for types with – standard outputs 50 Storage temperature range Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) –65 to +150 for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mA mA °C mW NOTE: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Apr 20 4 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LV109 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level l l Input I t voltage LOW level l l Input I t voltage TYP1 MAX 0.9 0.9 VCC = 2.0 V 1.4 1.4 VCC = 2.7 to 3.6 V 2.0 VOH HIGH level output voltage; STANDARD outputs UNIT MAX V 2.0 VCC = 1.2 V 0.3 0.3 VCC = 2.0 V 0.6 0.6 0.8 0.8 VCC = 1.2 V; VI = VIH or VIL; –IO = 100µA HIGH level output voltage; all outputs MIN VCC = 1.2 V VCC = 2.7 to 3.6 V VOH O -40°C to +125°C V 1.2 VCC = 2.0 V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7 V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0 V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 3.0 V; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 V V VCC = 1.2 V; VI = VIH or VIL; IO = 100µA 0 VCC = 2.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 2.7 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 0.25 0.40 0.50 V VOL O LOW level output voltage; all outputs VOL LOW level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; IO = 6mA Input leakage current VCC = 3.6 V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; flip-flops VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 80 µA ∆ICC Additional quiescent supply current per input VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 500 850 µA II V NOTE: 1. All typical values are measured at Tamb = 25°C. AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM VCC(V) tPHL/tPLH tPLH 1998 Apr 20 Propagation g delay y nCP to nQ, nQ Propagation g delay y nSD to nQ Figure 1 Figure 2 LIMITS CONDITION –40 to +85 °C MIN TYP1 –40 to +125 °C MAX MIN 1.2 90 2.0 31 58 70 2.7 23 43 51 3.0 to 3.6 182 34 41 1.2 55 2.0 19 36 44 2.7 14 26 33 3.0 to 3.6 102 21 26 5 UNIT MAX ns ns Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LV109 AC CHARACTERISTICS (Continued) GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM VCC(V) tPHL tPHL tPLH tW tW Propagation g delay y nSD to nQ Propagation g delay y nRD to nQ Propagation g delay y nRD to nQ Clock pulse width HIGH or LOW Set or reset pulse width HIGH or LOW Figure 2 Figure 2 Figure 2 Figure 1 Figure 2 LIMITS CONDITION –40 to +85 °C MIN Removal time nSD, nRD to nCP Figure 2 Set-up time nJ, nK to CP Figure 1 fmax Hold time nJ, nK to nCP Maximum clock ulse frequency pulse Figure 1 Figure 1 26 46 60 19 36 44 3.0 to 3.6 172 29 35 1.2 75 2.0 26 46 60 2.7 19 36 44 3.0 to 3.6 152 29 35 1.2 70 2.0 24 44 54 2.7 18 33 40 3.0 to 3.6 132 26 2.0 34 41 2.7 25 9 30 20 72 24 2.0 34 9 41 2.7 25 6 30 3.0 to 3.6 20 52 24 ns ns ns ns 35 2.0 24 12 29 2.7 18 9 21 3.0 to 3.6 14 72 17 ns 30 2.0 22 10 26 2.7 16 8 19 3.0 to 3.6 13 62 15 ns –5 2.0 5 –2 5 2.7 5 –1 5 3.0 to 3.6 5 02 5 2.0 14 40 12 2.7 19 58 16 24 702 20 6 ns 32 12 3.0 to 3.6 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3 V. UNIT MAX 2.7 3.0 to 3.6 1998 Apr 20 MIN 2.0 1.2 th MAX 75 1.2 tsu –40 to +125 °C 1.2 1.2 trem TYP1 ns MHz Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger AC WAVEFORMS 74LV109 TEST CIRCUIT VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. VCC VO VI VI nJ, nK INPUT GND PULSE GENERATOR VM t su VI nCP INPUT D.U.T. 50pF t su th 1/f max RT CL RL = 1k th Test Circuit for switching times VM DEFINITIONS GND RL = Load resistor tW t PHL CL = Load capacitance includes jig and probe capacitance t PLH RT = Termination resistance should be equal to ZOUT of pulse generators. VOH nQ OUTPUT VM TEST VOL tPLH/tPHL VOH nQ OUTPUT VCC < 2.7V 2.7–3.6V VM VI VCC 2.7V SV00901 VOL Figure 3. Load circuitry for switching times. t PLH t PHL The shaded areas indicate when the input is permitted to change for predictable output performance. SV00522 Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ and nK to nCP set-up, the nCP to nJ, nK hold times and the maximum clock pulse frequency. Vl nCP INPUT GND VM trem Vl nSD INPUT GND VM trem tW tW Vl nRD INPUT GND VM tPLH tPHL VOH nQ OUTPUT VOL VM tPHL tPLH VOH nQ OUTPUT VOL VM SV00523 Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD, nSD to nCP removal time. 1998 Apr 20 7 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger DIP16: plastic dual in-line package; 16 leads (300 mil) 1998 Apr 20 8 74LV109 SOT38-4 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger SO16: plastic small outline package; 16 leads; body width 3.9 mm 1998 Apr 20 9 74LV109 SOT109-1 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1998 Apr 20 10 74LV109 SOT338-1 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 1998 Apr 20 11 74LV109 SOT403-1 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LV109 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 Apr 20 12 Date of release: 05-96 9397-750-04417