INTEGRATED CIRCUITS 74LVC273 Octal D-type flip-flop with reset; positive-edge trigger Product specification Supersedes data of 1996 Jun 06 IC24 Data Handbook 1998 May 20 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger FEATURES 74LVC273 DESCRIPTION • Wide supply voltage range of 1.2V to 3.6V • Conforms to JEDEC standard 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface with TTL levels • Output drive capability 50Ω transmission lines @ 85°C The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf 2.5 ns SYMBOL PARAMETER CONDITIONS CL = 50pF VCC = 3.3V TYPICAL UNIT 6.0 6.0 ns tPHL/tPLH Propagation delay CP to Qn; MR to Qn fmax Maximum clock frequency 230 MHz CI Input capacitance 5.0 pF CPD Power dissipation capacitance per flip-flop 22 pF VI = GND to VCC1 NOTE: 1 CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 20-Pin Plastic SO –40°C to +85°C 74LVC273 D 74LVC273 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74LVC273 DB 74LVC273 DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC273 PW 74LVC273PW DH SOT360-1 PIN CONFIGURATION PIN DESCRIPTION MR 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP PIN NUMBER SYMBOL 1 MR 2, 5, 6, 9, 12, 15, 16, 19 Q0 – Q7 Flip-flop outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 – D7 Data inputs 10 GND Ground (0V) 11 CP Clock input (LOW-to-HIGH, edge-triggered) 20 VCC Positive power supply FUNCTION Master reset input (active LOW) SY00051 1998 May 20 2 853-2064 19419 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger LOGIC SYMBOL 74LVC273 IEEE/IEC LOGIC SYMBOL 11 CP CP 11 MR 1 C1 R 3 D0 Q0 2 D0 3 2 Q0 4 D1 Q1 5 D1 4 5 Q1 7 D2 Q2 6 D2 7 6 Q2 8 D3 Q3 9 D3 8 9 D4 13 12 D5 14 15 D6 17 16 Q6 D7 18 19 Q7 13 D4 Q4 12 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 1D Q3 Q4 Q5 SY00050 MR FUNCTION TABLE 1 OPERATING MODES SY00052 INPUTS OUTPUT MR CP Dn Q0 – Q7 Reset (clear) L X X L Load ‘1’ H h H Load ‘0’ H I L H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition = LOW-to-HIGH transition X = Don’t care RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS UNIT MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 DC Input voltage range 0 5.5 V VI/O DC Input voltage range for I/Os 0 VCC V VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V VCC VI V Tamb Operating free-air temperature range tr, tf Input rise and fall times 1998 May 20 VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V 3 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC PARAMETER CONDITIONS DC supply voltage RATING UNIT –0.5 to +6.5 V IIK DC input diode current VI t0 –50 mA –0.5 to +5.5 V "50 mA –0.5 to VCC +0.5 V VI DC input voltage Note 2 IOK DC output diode current VO uVCC or VO t 0 VO DC output voltage Note 2 IO DC output source or sink current VO = 0 to VCC IGND, ICC Tstg PTOT "50 mA "100 mA –65 to +150 °C DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K 500 above +60°C derate linearly with 5.5 mW/K 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VOL II VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 LOW level output voltage V 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*1.0 VCC V VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA 0.20 VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.55 V "0 1 "0.1 "5 µA VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 "10 µA Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA Additional quiescent supply current VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA 6V; VI = 5 5V or GND VCC = 3 3.6V; 5.5V IOZ 3-State output OFF-state current ICC NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 1998 May 20 MAX GND VCC = 2.7 to 3.6V HIGH level output voltage UNIT V VCC = 1.2V Input leakage current ∆ICC TYP1 4 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM MIN TYP1 MAX VCC = 2.7V MIN UNIT TYP MAX tPHL tPLH Propagation delay CP to Qn 1 6.0 10.2 6.6 11.2 ns tPHL Propagation delay MR to Qn 2 6.3 11.0 7.4 12.0 ns tW Clock pulse width HIGH or LOW 1 4 1.2 5 1.8 ns tW Master reset pulse width LOW 2 4 1.2 5 1.7 ns trem Removal time MR to CP 2 2 –1.0 3 –1.0 ns tsu Set-up time Dn to CP 3 2 0.7 3 1.0 ns th Hold time Dn to CP 3 0 –0.6 0 –0.9 ns Maximum clock pulse frequency 1 125 fmax 100 MHz NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25°C. AC WAVEFORMS VM = 1.5V at VCC 2.7V. VM = 0.5 VCC at VCC 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VI CP INPUT ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ VI th th VI VM Dn INPUT GND tw VOH tsu tsu 1/fMAX CP INPUT VM GND tPHL Qn OUTPUT VM GND tPLH VOH Qn OUTPUT VM VOL VM VOL SW00078 NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform 1. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency SW00079 Waveform 3. Data set-up and hold times for the data input (Dn) VCC MR INPUT VM VM GND tw VCC trem CP INPUT VM GND VOH Qn OUTPUT VOL tPHL VM SY00053 Waveform 2. Master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time 1998 May 20 5 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 TEST CIRCUIT tW 90% S1 VCC VS1 Open GND NEGATIVE PULSE 90% VM VI VM 10% 10% 0V VI RL VO PULSE GENERATOR tTHL (tf) tTLH (tr) tTLH (tr) tTHL (tf) D.U.T. RT RL CL 90% POSITIVE PULSE VI 90% VM VM 10% tW Test Circuit for 3-State Outputs 10% 0V VM = 1.5V Input Pulse Definition DEFINITIONS Switch position TEST S1 tPLH/tPHL Open tPLZ/tPZL VS1 tPHZ/tPZH GND VCC VI RL = VS1 < 2.7V VCC 2 VCC 2.7–3.6V 2.7V 2 VCC Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. SY00044 Waveform 4. Load circuitry for switching times 1998 May 20 6 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger SO20: plastic small outline package; 20 leads; body width 7.5 mm 1998 May 20 7 74LVC273 SOT163-1 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1998 May 20 8 74LVC273 SOT339-1 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1998 May 20 9 74LVC273 SOT360-1 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger 74LVC273 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04505