INTEGRATED CIRCUITS 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1997 Mar 18 IC24 Data Handbook 1998 Apr 28 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger FEATURES 74LVC109 DESCRIPTION • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Output capability: standard • ICC category: flip-flops The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. The 74LVC109 is a dual positive-edge triggered JK-type flip-flop featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns PARAMETER SYMBOL tPHL/tPLH fmax Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ CONDITIONS CL = 50 pF; VCC = 3.3 V Maximum clock frequency CI Input capacitance CPD Power dissipation capacitance per flip-flop VI = GND to VCC1 TYPICAL UNIT 4.0 4.5 4.5 ns 250 MHz 5.0 pF 27 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic SO PACKAGES –40°C to +85°C 74LVC109 D 74LVC109 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +85°C 74LVC109 DB 74LVC109 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC109 PW 74LVC109PW DH SOT403-1 PIN CONFIGURATION 1R D 1 PIN DESCRIPTION 16 V CC 1J 2 15 2R 1K 3 14 2J PIN NUMBER D 1CP 4 13 2K 1S D 5 12 2CP 1Q 6 11 2S 1Q 7 10 2Q GND 8 9 2Q D SV00517 1998 Apr 28 2 SYMBOL FUNCTION 1, 15 1RD, 2RD Asynchronous reset input (active LOW) 2, 14, 3, 13 1J, 2J, 1K, 2K Synchronous inputs; flip-flops 1 and 2 4, 12 1CP, 2CP Clock input (LOW-to-HIGH, edge-triggered) 5, 11 1SD, 2SD Asynchronous set inputs (active LOW) 6, 10 1Q, 2Q True flip-flop outputs 7, 9 1Q, 2Q Complement flip-flop outputs 8 GND Ground (O V) 16 VCC Positive supply voltage 853–1947 19308 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger LOGIC SYMBOL (IEEE/IEC) 5 FUNCTIONAL DIAGRAM 11 S 5 1SD 2 1J S 6 2 10 14 1J 1J 4 C1 7 Q 1Q 7 11 2SD R (a) 6 RD 15 R K 1Q 1 1RD 1K 1 Q 1K 9 13 1K J FF1 3 C1 SD 4 1CP CP 12 3 74LVC109 SD (b) 14 2J J SV00519 12 2CP CP FF2 13 2K K LOGIC SYMBOL 2Q 10 Q Q 2Q 9 RD 5 11 1S D 2S D 15 2RD SV00520 2 1J J 1Q 6 14 2J Q 2Q 10 4 1CP 12 2CP CP 1Q 7 3 1K 13 2K Q K 2Q 9 1R D 2R D 1 15 SV00518 LOGIC DIAGRAM K C C C C Q Q J C C C C S R CP C C SV00521 1998 Apr 28 3 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 FUNCTION TABLE INPUTS OPERATING MODES OUTPUTS nSD nRD nCP nJ nK nQ nQ Asynchronous set Asynchronous reset Undetermined L H L H L L X X X X X X X X X H L H L H H Toggle Load “0” (reset) Load “1” (set) Hold “no change” H H H H H H H H ↑ ↑ ↑ ↑ h l h l l l h h q L H q q H L q NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition. X = don’t care ↑ = LOW-to-HIGH CP transition RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS LIMITS MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 UNIT V VI DC input voltage range 0 5.5 VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V Tamb Operating free-air temperature range tr, tf Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V V ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC PARAMETER CONDITIONS UNIT –0.5 to +6.5 V IIK DC input diode current VI t 0 –50 mA VI DC input voltage Note 2 –0.5 to +5.5 V IOK DC output diode current VO uVCC or VO t 0 "50 mA VO DC output voltage Note 2 IO DC output source or sink current VO = 0 to VCC IGND, ICC Tstg PTOT DC supply voltage RATING DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K –0.5 to VCC +0.5 V "50 mA "100 mA –65 to +150 °C 500 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Apr 28 4 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C TYP1 MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 GND VCC = 2.7 to 3.6V 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*1.0 VCC VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage ICC ∆ICC V V 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND VCC = 3.0V; VI = VIH or VIL; IO = 24mA II MAX V VCC = 1.2V HIGH level output voltage UNIT 0.20 V 0.55 Input leakage current 6V; VI = 5 5V or GND VCC = 3 3.6V; 5.5V Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 "0 1 "0.1 "5 µA 0.1 10 µA 5 500 µA NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC CHARACTERISTICS GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500; Tamb = –40C to +85C LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V TYP1 MAX TYP MIN MIN NO TAG UNIT MAX tPHL/tPLH Propagation delay nCP to nQ, nQ Figures 1, 3 4.3 7.5 8.5 ns tPLH Propagation delay nSD to nQ nRD to nQ Figures 2, 3 4.5 8.0 9.0 ns tPHL Propagation delay nSD to nQ nRD to nQ Figures 2, 3 5.2 9.0 10 ns tW Clock pulse width HIGH or LOW Figure 1 3.3 tW Set or reset pulse width HIGH or LOW Figure 2 3.0 ns trem Removal time nSD, nRD to nCP Figure 2 3.0 ns tsu Set-up time nJ, nK to CP Figure 1 2.5 ns th Hold time nJ, nK to nCP Figure 1 2.0 ns Maximum clock pulse frequency Figure 1 150 fmax NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25°C. 1998 Apr 28 5 2.0 225 ns MHz Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. VI nJ, nK INPUT GND Vl nCP INPUT GND VM t su th VI nCP INPUT t su 1/f max th VM trem Vl nSD INPUT GND VM VM trem tW tW GND Vl tW t PHL VOH nQ OUTPUT t PLH nRD INPUT VM GND VM tPLH nQ OUTPUT VOL VOH nQ OUTPUT tPHL VOH VOL VM tPLH tPHL VM VOH VOL t PLH nQ OUTPUT VOL t PHL The shaded areas indicate when the input is permitted to change for predictable output performance. VM SV00522 SV00523 Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ and nK to nCP set-up, the nCP to nJ, nK hold times and the maximum clock pulse frequency. Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD, nSD to nCP removal time. TEST CIRCUIT S1 Vcc 2 < VCC Open GND Vl NEGATIVE PULSE 90% VM RL CL 10% 0V D.U.T. RT VI VM 10% RL VO PULSE GENERATOR tW 90% tTHL (tf) tTLH (tr) tTLH (tr) tTHL (tf) 90% POSITIVE PULSE VI 90% VM VM 10% tW Test Circuit for Outputs 10% 0V VM = 1.5V Input Pulse Definition DEFINITIONS SWITCH POSITION TEST tPLH/tPHL S1 Open VCC VI RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. < 2.7V VCC 2.7–3.6V 2.7V ≥ 4.5 V VCC RT = Termination resistance should be equal to ZOUT of pulse generators. SV00904 Figure 3. Load circuitry for switching times. 1998 Apr 28 6 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger SO16: plastic small outline package; 16 leads; body width 3.9 mm 1998 Apr 28 7 74LVC109 SOT109-1 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1998 Apr 28 8 74LVC109 SOT338-1 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 1998 Apr 28 9 74LVC109 SOT403-1 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1997 Mar 18 10 Date of release: 05-96 9397-750-04489