Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET FEATURES PHP69N03LT, PHB69N03LT PHD69N03LT SYMBOL • ’Trench’ technology • Very low on-state resistance • Fast switching • Low thermal resistance • Logic level compatible QUICK REFERENCE DATA VDSS = 25 V d ID = 69 A RDS(ON) ≤ 12 mΩ (VGS = 10 V) g RDS(ON) ≤ 14 mΩ (VGS = 5 V) s GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology. Applications:• High frequency computer motherboard d.c. to d.c. converters • High current switching The PHP69N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB69N03LT is supplied in the SOT404 (D2PAK) surface mounting package. The PHD69N03LT is supplied in the SOT428 (DPAK)surface mounting package. PINNING PIN SOT404 (D2PAK) SOT78 (TO220AB) DESCRIPTION 1 gate 2 drain 1 3 source tab tab tab 2 1 23 tab SOT428 (DPAK) 1 2 3 1 3 drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDSS VDGR VGS VGSM Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ ID IDM Ptot Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage (DC) Gate-source voltage (pulse peak value) Drain current (DC) Drain current (pulse peak value) Total power dissipation Operating junction and storage temperature MIN. MAX. UNIT Tj ≤ 150˚C - 25 25 ± 15 ± 20 V V V V Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C - 69 48 240 A A A Tmb = 25 ˚C - 55 125 175 W ˚C 1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages. October 1999 1 Rev 1.600 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LTT PHD69N03LT THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78 package, in free air SOT404 and SOT428 packages, pcb mounted, minimum footprint TYP. MAX. UNIT - - 1.2 K/W - 60 50 - K/W K/W AVALANCHE LIMITING VALUE SYMBOL PARAMETER WDSS CONDITIONS MIN. MAX. UNIT - 60 mJ Drain-source non-repetitive ID = 25 A; VDD ≤ 15 V; unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C energy ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; VGS(TO) Drain-source breakdown voltage Gate threshold voltage MIN. Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) gfs IGSS IDSS Drain-source on-state resistance VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175˚C Forward transconductance VDS = 25 V; ID = 25 A Gate source leakage current VGS = ±5 V; VDS = 0 V Zero gate voltage drain VDS = 25 V; VGS = 0 V; current Tj = 175˚C TYP. MAX. UNIT 25 22 1 0.5 12 - 1.5 8.5 11 40 10 0.05 - 2 2.3 12 14 26 100 10 500 V V V V V mΩ mΩ mΩ S nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 69 A; VDD = 15 V; VGS = 5 V - 26 7.6 11 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 15 V; ID = 25 A; VGS = 10 V; RG = 5 Ω Resistive load - 7 50 82 59 15 75 120 75 ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 1700 475 300 - pF pF pF October 1999 2 Rev 1.600 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LTT PHD69N03LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IS ISM CONDITIONS MIN. TYP. MAX. UNIT - - 69 A - - 240 A IF = 25 A; VGS = 0 V IF = 69 A; VGS = 0 V - 0.9 1.0 1.2 - V IF = 20 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V - 83 0.1 - ns µC Normalised Power Derating, PD (%) 1000 Peak Pulsed Drain Current, IDM (A) 100 90 RDS(on) = VDS/ ID 80 70 tp = 10 us 100 60 100 us 50 40 1 ms D.C. 10 30 10 ms 100 ms 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 1 175 1 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 10 Drain-Source Voltage, VDS (V) 100 Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp 10 Normalised Current Derating, ID (%) Transient thermal impedance, Zth j-mb (K/W) 100 90 80 1 70 D = 0.5 60 0.2 50 0.1 40 0.1 30 P D 0.05 tp D = tp/T 0.02 20 10 single pulse 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 0.01 1E-06 175 1E-04 1E-03 1E-02 1E-01 1E+00 Pulse width, tp (s) Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); VGS ≥ 5 V October 1999 1E-05 T 3 Rev 1.600 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LTT PHD69N03LT Drain Current, ID (A) 50 5V VGS = 10 V Transconductance, gfs (S) 50 Tj = 25 C VDS > ID X RDS(ON) 45 45 4.5 V Tj = 25 C 3V 40 40 35 35 175 C 2.8 V 30 30 25 25 2.6 V 20 20 15 15 2.4 V 10 10 2.2 V 5 5 2V 0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 0 2 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS Drain-Source On Resistance, RDS(on) (Ohms) 2.6 V 2.4 V Tj = 25 C 0.08 2.8V 0.06 3V 0.05 0.04 0.03 0.02 VGS =4.5 V 5V 0.01 10V 0 0 5 10 15 20 25 30 Drain Current, ID (A) 35 40 45 -60 50 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 30 35 40 -40 -20 0 20 40 60 80 100 Junction temperature, Tj (C) 120 140 160 180 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj) Threshold Voltage, VGS(TO) (V) Drain current, ID (A) 2.25 50 VDS > ID X RDS(ON) 45 15 20 25 Drain current, ID (A) Normalised On-state Resistance 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.09 0.07 10 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 0.1 2.2 V 5 2 maximum 1.75 40 35 1.5 typical 30 1.25 25 1 minimum 20 0.75 15 10 0.5 175 C Tj = 25 C 5 0.25 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 -60 Gate-source voltage, VGS (V) -20 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj October 1999 -40 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 4 Rev 1.600 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LTT PHD69N03LT Drain current, ID (A) 1.0E-01 Gate-source voltage, VGS (V) VDS = 5 V 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1.0E-02 1.0E-03 minimum typical maximum 1.0E-04 1.0E-05 1.0E-06 ID = 69 A Tj = 25 C VDD = 15 V 0 0 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 5 10 15 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 20 25 30 Gate charge, QG (nC) 35 40 45 50 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Source-Drain Diode Current, IF (A) 50 Capacitances, Ciss, Coss, Crss (pF) VGS = 0 V 10000 45 40 35 30 Ciss 175 C 25 1000 Tj = 25 C 20 15 Coss 10 Crss 5 0 100 0 0.1 1 10 Drain-Source Voltage, VDS (V) 100 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Source-Drain Voltage, VSDS (V) Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz October 1999 0.1 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 5 Rev 1.600 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LTT PHD69N03LT MECHANICAL DATA Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 E SOT78 A A1 P q D1 D L1 L2(1) Q b1 L 1 2 e e 3 c b 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) (1) UNIT A A1 b b1 c D D1 E mm 4.5 4.1 1.39 1.27 0.9 0.7 1.3 1.0 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 e L L1 2.54 15.0 13.5 3.30 2.79 L2 max. P q Q 3.0 3.8 3.6 3.0 2.7 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 TO-220 Fig.15. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g) Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8". October 1999 6 Rev 1.600 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LTT PHD69N03LT MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 OUTLINE VERSION D max. D1 E 11 1.60 1.20 10.30 9.70 e Lp HD Q 2.54 2.90 2.10 15.40 14.80 2.60 2.20 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 SOT404 Fig.16. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". October 1999 7 Rev 1.600 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LTT PHD69N03LT MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.17. SOT404 : soldering pattern for surface mounting. October 1999 8 Rev 1.600 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LTT PHD69N03LT MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped) SOT428 seating plane y A E A2 A A1 b2 D1 mounting base E1 D HE L2 2 L1 L 1 3 b1 w M A b c e e1 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 2.38 2.22 A1(1) A2 b b1 max. b2 c 0.65 0.45 0.89 0.71 0.89 0.71 1.1 0.9 5.36 5.26 0.4 0.2 D1 E D max. max. max. 6.22 5.98 4.81 4.45 6.73 6.47 E1 min. 4.0 e e1 2.285 4.57 HE max. L 10.4 9.6 2.95 2.55 L1 min. L2 w y max. 0.5 0.7 0.5 0.2 0.2 Note 1. Measured from heatsink back to lead. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT428 EUROPEAN PROJECTION ISSUE DATE 98-04-07 Fig.18. SOT428 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". October 1999 9 Rev 1.600 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LTT PHD69N03LT MOUNTING INSTRUCTIONS Dimensions in mm 7.0 7.0 2.15 1.5 2.5 4.57 Fig.19. SOT428 : soldering pattern for surface mounting. October 1999 10 Rev 1.600 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP69N03LT, PHB69N03LTT PHD69N03LT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1999 11 Rev 1.600