Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET FEATURES PHN1018 SYMBOL • ’Trench’ technology • Low on-state resistance • Fast switching • Low-profile surface mount package • Logic level compatible QUICK REFERENCE DATA VDSS = 25 V d ID = 9.6 A RDS(ON) ≤ 18 mΩ (VGS = 10 V) g RDS(ON) ≤ 21 mΩ (VGS = 5 V) s GENERAL DESCRIPTION PINNING SOT96-1 (SO8) N-channel enhancement mode logic level field-effect power transistor in a surface mounting plastic package using ’trench’ technology. PIN 4 gate Application:• High frequency computer motherboard d.c. to d.c. converters 5-8 drain 1-3 DESCRIPTION 8 7 6 5 1 2 3 4 source pin 1 index The PHN1018 is supplied in the SOT96-1 (SO8) surface mounting package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDSS VDGR Drain-source voltage Drain-gate voltage VGS VGSM ID Gate-source voltage (DC) Gate-source voltage (pulse peak value) Drain current (tp ≤ 10 s) Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ - IDM Ptot Drain current (pulse peak value) Total power dissipation Tj, Tstg Operating junction and storage temperature Ta = 25 ˚C Ta = 70 ˚C Ta = 25 ˚C Ta = 25 ˚C Ta = 70 ˚C - MIN. MAX. UNIT - 25 25 V V - ± 15 ± 20 V V - 55 9.6 7.7 38 2.5 1.6 150 A A A W W ˚C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-a Surface mounted, FR4 board, t ≤ 10 sec Rth j-a Thermal resistance junction to ambient Thermal resistance junction to ambient October 1999 Surface mounted, FR4 board 1 TYP. MAX. UNIT - 50 K/W 150 - K/W Rev 1.200 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHN1018 ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) Drain-source breakdown voltage Gate threshold voltage CONDITIONS MIN. VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 150˚C Tj = -55˚C RDS(ON) gfs IGSS IDSS Drain-source on-state resistance VGS = 10 V; ID = 10 A VGS = 5 V; ID = 10 A VGS = 5 V; ID = 10 A; Tj = 150˚C Forward transconductance VDS = 25 V; ID = 10 A Gate source leakage current VGS = ±5 V; VDS = 0 V Zero gate voltage drain VDS = 25 V; VGS = 0 V; current Tj = 150˚C TYP. MAX. UNIT 25 22 1 0.6 8 - 1.5 13 18 25 10 0.05 - 2 2.3 18 21 36 100 10 500 V V V V V mΩ mΩ mΩ S nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 10 A; VDD = 15 V; VGS = 5 V - 17 4 6 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 15 V; ID = 25 A; VGS = 10 V; RG = 5 Ω Resistive load - 6.4 62 50 30 12 75 75 45 ns ns ns ns Ld Ls Internal drain inductance Internal source inductance Drain leads to centre of die Source leads to source bond pad - 1 3 - nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 1050 330 220 - pF pF pF REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IDR Ta = 25 ˚C, tp ≤ 10 s VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IDRM October 1999 MIN. TYP. MAX. UNIT - - 9.6 A - - 38 A IF = 10 A; VGS = 0 V - 0.83 1.2 V IF = 10 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V - 100 0.13 - ns µC 2 Rev 1.200 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHN1018 Normalised Power Derating, Ptot (%) Transient thermal impedance, Zth j-mb (K/W) 100 100 D = 0.5 90 0.2 80 10 0.1 70 0.05 0.02 60 1 50 40 P D single pulse 30 D = tp/T tp 0.1 20 T 10 0.01 1E-06 0 0 20 40 60 80 100 120 140 1E-05 1E-04 1E-03 160 1E-02 1E-01 1E+00 1E+01 Pulse width, tp (s) Ambient temperature, Ta (C) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Ta) Fig.4. Transient thermal impedance. Zth j-a = f(t); parameter D = tp/T Drain Current, ID (A) 50 Normalised Current Derating, ID (%) VGS = 10 V 120 5V Tj = 25 C 4.5 V 45 40 100 3.2 V 35 80 30 3V 25 60 2.8 V 20 40 20 15 2.6 V 10 2.4 V 5 2.2 V 0 0 20 40 60 80 100 120 140 0 160 0 Ambient temperature, Ta (C) Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Ta); conditions: VGS ≥ 5 V 100 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 Drain-Source On Resistance, RDS(on) (Ohms) 0.1 tp = 10 us 2.6 V 2.2 V 10 0.4 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID 0.2 100 us 0.09 1 ms 0.08 10 ms 0.07 Tj = 25 C 2.4 V 2.8V 3V 3.2 V 0.06 100 ms 1 0.05 D.C. 0.04 0.03 0.1 5V VGS =4.5 V 0.02 0.01 0.01 10V 0 0.1 1 10 Drain-Source Voltage, VDS (V) 100 0 Fig.3. Safe operating area. Ta = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp October 1999 5 10 15 20 25 30 Drain Current, ID (A) 35 40 45 50 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 3 Rev 1.200 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHN1018 Threshold Voltage, VGS(TO) (V) Drain current, ID (A) 2.25 40 VDS > ID X RDS(ON) 2 35 maximum 1.75 30 1.5 25 typical 1.25 20 1 minimum 15 0.75 10 0.5 150 C 5 Tj = 25 C 0.25 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 -60 -40 -20 0 Gate-source voltage, VGS (V) 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Transconductance, gfs (S) 30 20 Drain current, ID (A) 1.0E-01 VDS > ID X RDS(ON) VDS = 5 V Tj = 25 C 25 1.0E-02 150 C 20 1.0E-03 15 minimum typical maximum 1.0E-04 10 1.0E-05 5 0 1.0E-06 0 5 10 15 20 25 Drain current, ID (A) 30 35 40 0 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised On-state Resistance Capacitances, Ciss, Coss, Crss (pF) 10000 Ciss 1000 Coss Crss 100 -60 -40 -20 0 20 40 60 80 100 Junction temperature, Tj (C) 120 140 160 180 0.1 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj) October 1999 1 10 Drain-Source Voltage, VDS (V) 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); VGS = 0 V; f = 1 MHz 4 Rev 1.200 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHN1018 Source-Drain Diode Current, IF (A) 50 Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VGS = 0 V ID = 10A 45 Tj = 25 C 40 VDD = 15 V 35 30 150 C 25 20 Tj = 25 C 15 10 5 0 0 5 10 15 20 25 30 Gate charge, QG (nC) 35 40 45 50 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Source-Drain Voltage, VSDS (V) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) October 1999 0.1 5 Rev 1.200 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHN1018 MECHANICAL DATA SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A max. A1 A2 mm inches UNIT A3 bp c D (1) E (2) 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 e HE 4.0 3.8 1.27 6.2 5.8 0.16 0.15 0.050 L Lp Q 1.05 1.0 0.4 0.7 0.6 0.244 0.039 0.028 0.041 0.228 0.016 0.024 v w y Z (1) 0.25 0.25 0.1 0.7 0.3 0.01 0.01 0.004 0.028 0.012 θ o 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 Fig.15. SOT96 surface mounting package. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8". October 1999 6 Rev 1.200 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHN1018 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1999 7 Rev 1.200