Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 × 48 × 8) DESCRIPTION The PLS100 (3-State) and PLS101 (Open Collector) are bipolar, fuse Programmable Logic Arrays (PLAs). Each device utilizes the standard AND/OR/Invert architecture to directly implement custom sum of product equations. Each device consists of 16 dedicated inputs and 8 dedicated outputs. Each output is capable of being actively controlled by any or all of the 48 product terms. The True, Complement, or Don’t Care condition of each of the 16 inputs and be ANDed together to comprise one P-term. All 48 P-terms can be selectively ORed to each output. The PLS100 and PLS101 are fully TTL compatible, and chip enable control for expansion of input variables and output inhibit. They feature either Open Collector or 3-State outputs for ease of expansion of product terms and application in bus-organized systems. Order codes are listed in the Ordering Information Table. PLS100/PLS101 FEATURES • Field-programmable (Ni-Cr link) • Input variables: 16 • Output functions: 8 • Product terms: 48 • I/O propagation delay: 50ns (max.) • Power dissipation: 600mW (typ.) • Input loading: –100µA (max.) • Chip Enable input • Output option: PIN CONFIGURATIONS N Package FE* 1 27 I8 I6 3 26 I9 I5 4 25 I10 I4 5 24 I11 I3 6 23 I12 I2 7 22 I13 I1 8 21 I14 I0 9 20 I15 F7 10 19 CE F6 11 18 F0 F5 12 17 F1 F4 13 16 F2 GND 14 15 F3 – PLS100: 3-State – PLS101: Open-Collector • Output disable function: – 3-State: Hi-Z – Open-Collector: High * APPLICATIONS • CRT display systems • Code conversion • Peripheral controllers • Function generators • Look-up and decision tables • Microprogramming • Address mapping • Character generators • Data security encoders • Fault detectors • Frequency synthesizers • 16-bit to 8-bit bus interface • Random logic replacement 28 VCC I7 2 Fuse Enable Pin: It is recommended that this pin be left open or connected to ground during normal operation. N = Plastic DIP (600mil-wide) A Package I5 I6 I7 FE VCC I8 I9 4 3 2 1 28 27 26 I4 5 25 I10 I3 6 24 I11 I2 7 23 I12 I1 8 22 I13 I0 9 21 I14 F7 10 20 I15 F6 11 19 CE 12 13 14 15 16 17 18 F5 F4 GND F3 F2 F1 F0 A = Plastic Leaded Chip Carrier ORDERING INFORMATION DESCRIPTION 3-STATE OPEN COLLECTOR DRAWING NUMBER 28-Pin Plastic Dual In-Line 600mil-wide PLS100N PLS101N 0413D 28-Pin Plastic Leaded Chip Carrier PLS100A PLS101A 0401F October 22, 1993 49 853–0308 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 × 48 × 8) PLS100/PLS101 LOGIC DIAGRAM (LOGIC TERMS–P) I0 9 I1 8 I2 7 I3 6 I4 5 I5 4 I6 3 I7 2 I8 27 I9 26 I10 25 I11 24 I12 23 I13 22 I14 21 I15 20 S0 X0 X1 X2 X3 X4 X5 X6 S1 S2 S3 S4 S5 S6 S7 18 F0 17 F1 16 F2 15 F3 13 F4 12 F5 11 F6 10 F7 19 CE X7 47 40 39 32 31 24 23 1615 NOTES: 1. All AND gate inputs with a blown link float to a logic “1”. 2. All OR gate inputs with a blown fuse float to logic “0”. 3. Programmable connection. October 22, 1993 50 8 7 0 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 × 48 × 8) PLS100/PLS101 FUNCTIONAL DIAGRAM I0 TYPICAL CONNECTION I1 I15 TYPICAL CONNECTION S0 F0 S6 F6 S7 F7 P0 P1 P47 CE ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER RATINGS UNIT VCC Supply voltage +7.0 VDC VIN Input voltage +5.5 VDC VO Output voltage +5.5 VDC IIN Input current ±30 mA IOUT Output current Tamb Operating temperature range Tstg Storage temperature range +100 mA 0 to +75 °C –65 to +150 °C NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other conditions above those indicated in the operational and programming specification of the device is not implied. THERMAL RATINGS TEMPERATURE Maximum junction 150°C Maximum ambient 75°C Allowable thermal rise ambient to junction 75°C October 22, 1993 The PLS100 device is also processed to military requirements for operation over the military temperature range. For specifications and ordering information consult the Philips Semiconductors Military Data Handbook. 51 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 × 48 × 8) PLS100/PLS101 DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS SYMBOL Input PARAMETER TEST CONDITIONS MIN 2.0 TYP1 MAX UNIT voltage2 VIH High VCC = MAX VIL Low VCC = MIN VIC Clamp3 Output VCC = MIN, IIN = –12mA V –0.8 0.8 V –1.2 V voltage2 VCC = MIN VOH High VOL Low5 (PLS100)4 IOH = –2mA 2.4 V IOL = 9.6mA 0.35 0.45 V Input current IIH High VIN = 5.5V <1 25 µA IIL Low VIN = 0.45V –10 –100 µA Output current IO(OFF) Hi-Z state (PLS100) IOS Short circuit (PLS100) 3, 6 ICC VCC supply current7 CE = High, VCC = MAX VOUT = 5.5V 1 40 µA VOUT = 0.45V –1 –40 µA –70 mA 170 mA CE = Low, VOUT = 0V VCC = MAX –15 120 Capacitance CE = High, VCC = 5.0V CIN Input COUT Output VIN = 2.0V 8 pF VOUT = 2.0V 17 pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one pin at a time. 4. Measured with VIL applied to CE and a logic high stored. 5. Measured with a programmed logic condition for which the output test is at a low logic level. Output sink current is applied through a resistor to VCC. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with the Chip Enable input grounded, all other inputs at 4.5V and the outputs open. October 22, 1993 52 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 × 48 × 8) PLS100/PLS101 AC ELECTRICAL CHARACTERISTICS 0°C < Tamb < +75°C, 4.75 < VCC < 5.25V, R1 = 470Ω, R2 = 1kΩ LIMITS SYMBOL PARAMETER TO FROM MIN TYP1 MAX UNIT Propagation delay2 tPD Input Output Input 35 50 ns tCE Chip Enable3 Output Chip Enable 15 30 ns Chip Disable3 Output Chip Enable 15 30 ns Disable time tCD NOTES: 1. All typical values are at VCC = 5V. Tamb = +25°C. 2. All propagation delays are measured and specified under worst case conditions. 3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. VOLTAGE WAVEFORMS TEST LOAD CIRCUIT +3.0V 90% VCC +5V S1 10% 0V C1 tR 5ns tF C2 R1 5ns F0 I0 +3.0V 90% INPUTS I15 CL R2 DUT 10% 0V 5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses TIMING DEFINITIONS SYMBOL tCE tCD CE 5ns GND OUTPUTS NOTE: C1 and C2 are to bypass VCC to GND. TIMING DIAGRAM PARAMETER Delay between beginning of Chip Enable Low (with Input valid) and when Data Output becomes valid. Delay between when Chip Enable becomes High and Data Output is in off state (Hi-Z or High). +3.0V INPUT 1.5V 0V ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 1.5V 0V tCE Delay between beginning of valid Input (with Chip Enable Low) and when Data Output becomes valid. October 22, 1993 +3.0V 1.5V CE F0 – F7 tPD F7 tCD VOH 1.5V VOL tPD Read Cycle 53 1.5V Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 × 48 × 8) LOGIC PROGRAMMING PLS100/PLS101 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors’ SNAP, Data I/O Corporation’s ABEL and Logical Devices Inc.’s CUPL design software packages. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. PLS100/PLS101 COMPLEMENT, INACTIVE, PRESET, etc., are defined below. PLS100/PLS101 logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors’ SNAP PLD design software package. PROGRAMMING AND SOFTWARE SUPPORT To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The sumbols for TRUE, Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this dat handbook for additional informational. OUTPUT POLARITY – (F) S S F O, B X ACTIVE LEVEL CODE LOW ACTIVE LEVEL HIGH1 (NON-INVERTING) L (INVERTING) CODE H “AND” ARRAY – (I) I I I I I I I I I I I P P P I P STATE CODE STATE CODE STATE CODE STATE CODE INACTIVE1,2 O I H I L DON’T CARE – “OR” ARRAY – (F) P P S S Pn STATUS CODE Pn STATUS ACTIVE1 A INACTIVE CODE • NOTES: 1. This is the initial unprogrammed state of all links. It is normally associated with all unused (inactive) AND gates Pn. 2. Any gate Pn will be unconditionally inhibited if any one of its (I) link pairs is left intact. VIRGIN STATE The PLS100/101 virgin devices are factory shipped in an unprogrammed state, with all fuses intact, such that: 1. All Pn terms are disabled (inactive) in the AND array. 2. All Pn terms are active in the OR array. 3. All outputs are Active-High. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. October 22, 1993 54 October 22, 1993 VARIABLE NAME PROGRAM TABLE # TOTAL NUMBER OF PARTS CUSTOMER SYMBOLIZED PART # PHILIPS DEVICE # PURCHASE ORDER # CUSTOMER NAME REV CF (XXXX) DATE L Im of used P-terms. – (dash) Don’t Care Enter (–) for unused inputs NOTE H Im INPUT VARIABLE (period) Prod. Term Not Present in Fp 2. Enter (A) for unused outputs of used P-terms. 1. Entries independent of output polarity. NOTES A Prod. Term Present in Fp OUTPUT FUNCTION PROGRAM TABLE ENTRIES L Active Low 2. Enter (H) for all unused outputs. 1. Polarity programmed once only. NOTES H Active High OUTPUT ACTIVE LEVEL Philips Semiconductors Programmable Logic Devices T E R M 47 PIN NO. Product specification Programmable logic arrays (16 × 48 × 8) PLS100/PLS101 PROGRAM TABLE AND POLARITY INPUT (Im) OR OUTPUT (FP) 0 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 20 21 22 23 24 25 26 27 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 55 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic arrays (16 × 48 × 8) PLS100/PLS101 SNAP RESOURCE SUMMARY DESIGNATIONS DIN100 I0 NIN100 I1 I15 AND TOUT100 OR S0 F0 S6 F6 S7 F7 EXOR100 P0 P1 P47 CE NOE100 October 22, 1993 56