PD - 97436
IRF7351PbF
HEXFET® Power MOSFET
Applications
l Synchronous Rectifier MOSFET for
Isolated DC-DC Converters
l Low Power Motor Drive Systems
Benefits
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
l 20V VGS Max. Gate Rating
VDSS
RDS(on) max
Qg (typ.)
60V 17.8mΩ@VGS = 10V 24nC
S1
1
8
D1
G1
2
7
D1
S2
3
6
D2
G2
4
5
D2
SO-8
Top View
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
Parameter
60
V
VGS
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
± 20
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
6.4
ID @ TA = 25°C
ID @ TA = 70°C
IDM
PD @TA = 25°C
Power Dissipation
f
f
8.0
c
PD @TA = 70°C
Power Dissipation
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
A
64
W
2.0
1.28
0.016
-55 to + 150
W/°C
°C
Thermal Resistance
Parameter
RθJL
RθJA
g
Junction-to-Ambient fg
Junction-to-Drain Lead
Typ.
Max.
Units
–––
20
°C/W
–––
62.5
Notes through
are on page 10
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1
11/18/09
IRF7351PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
Drain-to-Source Breakdown Voltage
60
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.068
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on)
Static Drain-to-Source On-Resistance
–––
13.7
17.8
VGS(th)
Gate Threshold Voltage
2.0
–––
4.0
mΩ
V
∆VGS(th)
Gate Threshold Voltage Coefficient
–––
-8.2
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
20
µA
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Forward Transconductance
18
–––
–––
Total Gate Charge
–––
24
36
IGSS
gfs
Qg
–––
V
VGS = 0V, ID = 250µA
VGS = 10V, ID = 8.0A
VDS = VGS, ID = 50µA
VDS = 60V, VGS = 0V
VDS = 60V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
S
VDS = 25V, ID = 6.4A
nC
VGS = 10V
Qgs1
Pre-Vth Gate-to-Source Charge
–––
3.8
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
1.2
–––
Qgd
Gate-to-Drain Charge
–––
7.2
–––
ID = 6.4A
Qgodr
–––
11.8
–––
See Fig. 17
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
8.4
–––
Qoss
Output Charge
–––
7.5
–––
td(on)
Turn-On Delay Time
–––
5.1
–––
tr
Rise Time
–––
5.9
–––
td(off)
Turn-Off Delay Time
–––
17
–––
tf
Fall Time
–––
6.7
–––
Ciss
Input Capacitance
–––
1330
–––
Coss
Output Capacitance
–––
190
–––
Crss
Reverse Transfer Capacitance
–––
92
–––
e
VDS = 30V
nC
VDS = 16V, VGS = 0V
VDD = 30V, VGS = 10V
ns
ID = 6.4A
e
RG = 1.8Ω
VGS = 0V
pF
VDS = 30V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
c
d
Typ.
–––
Max.
325
Units
mJ
–––
6.4
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
1.8
ISM
(Body Diode)
Pulsed Source Current
–––
–––
64
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.3
V
trr
Reverse Recovery Time
–––
20
30
ns
Qrr
Reverse Recovery Charge
–––
61
92
nC
2
c
Conditions
MOSFET symbol
A
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 6.4A, VGS = 0V
TJ = 25°C, IF = 6.4A, VDD = 30V
di/dt = 300A/µs
e
e
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IRF7351PbF
100
100
10
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
8.0V
6.0V
5.0V
4.5V
4.3V
4.0V
3.8V
1
≤60µs PULSE WIDTH
Tj = 25°C
BOTTOM
10
0.1
3.8V
≤60µs PULSE WIDTH
Tj = 150°C
3.8V
0.1
1
1
10
100
0.1
1000
1
10
100
1000
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
VGS
10V
8.0V
6.0V
5.0V
4.5V
4.3V
4.0V
3.8V
10
T J = 25°C
T J = 150°C
1
VDS = 25V
≤60µs PULSE WIDTH
0.1
1.8
ID = 8.0A
VGS = 10V
1.5
1.3
1.0
0.8
0.5
2
3
4
5
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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6
-60 -40 -20 0
20 40 60 80 100 120 140 160
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRF7351PbF
100000
14.0
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
ID= 6.4A
Coss = Cds + Cgd
C, Capacitance (pF)
10000
Ciss
1000
12.0
VGS, Gate-to-Source Voltage (V)
Crss = C gd
Coss
Crss
100
VDS= 48V
VDS= 30V
VDS= 12V
10.0
8.0
6.0
4.0
2.0
10
0.0
1
10
100
0
5
VDS, Drain-to-Source Voltage (V)
20
25
30
35
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
100
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
15
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
100
T J = 150°C
10
OPERATION IN THIS AREA
LIMITED BY R DS(on)
T J = 25°C
1
100µsec
10
10msec
0.1
1msec
DC
1
T A = 25°C
Tj = 150°C
Single Pulse
VGS = 0V
0.1
0.0
0.2
0.4
0.6
0.8
1.0
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10
1.2
0.01
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF7351PbF
3.5
8
VGS(th) , Gate threshold Voltage (V)
ID, Drain Current (A)
7
6
5
4
3
2
1
3.0
ID = 50µA
2.5
2.0
1.5
0
25
50
75
100
125
-75 -50 -25
150
0
25
50
75 100 125 150
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
Thermal Response ( Z thJA ) °C/W
100
D = 0.50
0.20
0.10
0.05
0.02
0.01
10
1
R1
R1
0.1
τJ
0.01
τJ
τ1
R2
R2
R3
R3
R4
R4
τ1
τ2
τ2
τ3
τ4
τ3
Ci= τi/Ri
Ci= τi/Ri
0.001
Ri (°C/W)
τA
τ4
τA
τi (sec)
3.6777
0.009926
21.765
25.24029
25.683
3.723179
11.374
0.348001
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
1000
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
50
1400
ID = 8.0A
EAS , Single Pulse Avalanche Energy (mJ)
RDS(on), Drain-to -Source On Resistance (m Ω)
IRF7351PbF
ID
0.53A
0.79A
BOTTOM 6.4A
1200
40
TOP
1000
30
T J = 125°C
20
10
T J = 25°C
0
0
5
10
15
20
800
600
400
200
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
VGS, Gate -to -Source Voltage (V)
Fig 12. On-Resistance vs. Gate Voltage
Fig 13. Maximum Avalanche Energy
vs. Drain Current
LD
VDS
15V
+
L
VDS
VDD -
DRIVER
D.U.T
D.U.T
RG
VGS
20V
IAS
tp
+
V
- DD
VGS
A
Pulse Width < 1µs
Duty Factor < 0.1%
0.01Ω
Fig 14a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
Fig 15a. Switching Time Test Circuit
VDS
90%
10%
VGS
I AS
Fig 14b. Unclamped Inductive Waveforms
6
td(on)
tr
td(off)
tf
Fig 15b. Switching Time Waveforms
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IRF7351PbF
D.U.T
Driver Gate Drive
P.W.
+
+
-
-
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
*
RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 17a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 17b. Gate Charge Waveform
7
IRF7351PbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
Ploss = (Irms × Rds(on ) )
*dissipated primarily in Q1.
2
⎛
⎞ ⎛
Qgs 2
⎞
Qgd
+⎜I ×
× Vin × f ⎟ + ⎜ I ×
× Vin × f ⎟
ig
ig
⎝
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
8
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
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IRF7351PbF
SO-8 Package Outline (Mosfet & Fetky)
Dimensions are shown in milimeters (inches)
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SO-8 Part Marking Information
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
IRF7351PbF
SO-8 Tape and Reel
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 16mH
RG = 25Ω, IAS = 6.4A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
When mounted on 1 inch square copper board.
Rθ is measured at TJ approximately 90°C.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 11/09
10
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