IRF IRF7821

PD - 94579B
IRF7821
HEXFET® Power MOSFET
Applications
l High Frequency Point-of-Load
Synchronous Buck Converter for
Applications in Networking &
Computing Systems.
VDSS
RDS(on) max
Qg(typ.)
30V
9.1mW@VGS= 10V
9.3nC
1
8
S
2
7
S
3
6
4
5
S
Benefits
l Very Low RDS(on) at 4.5V VGS
l Low Gate Charge
l Fully Characterized Avalanche Voltage
and Current
G
A
A
D
D
D
D
SO-8
Top View
Absolute Maximum Ratings
Parameter
VDS
Drain-to-Source Voltage
Max.
Units
30
V
VGS
Gate-to-Source Voltage
± 20
ID @ TA = 25°C
Continuous Drain Current, VGS @ 10V
13.6
ID @ TA = 70°C
Continuous Drain Current, VGS @ 10V
11
IDM
Pulsed Drain Current
100
PD @TA = 25°C
Power Dissipation
PD @TA = 70°C
Power Dissipation
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
f
f
c
A
2.5
W
1.6
0.02
-55 to + 155
W/°C
°C
Thermal Resistance
Parameter
RθJL
RθJA
g
Junction-to-Ambient fg
Junction-to-Drain Lead
Typ.
Max.
Units
–––
20
°C/W
–––
50
Notes  through … are on page 10
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1
1/14/03
IRF7821
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
Drain-to-Source Breakdown Voltage
30
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.025
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on)
Static Drain-to-Source On-Resistance
–––
7.0
9.1
mΩ
–––
9.5
12.5
V
VGS = 0V, ID = 250µA
VGS = 10V, ID = 13A
VGS = 4.5V, ID = 10A
VGS(th)
Gate Threshold Voltage
1.0
–––
–––
V
∆VGS(th)
Gate Threshold Voltage Coefficient
–––
- 4.9
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
VDS = 24V, VGS = 0V
–––
–––
150
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
Forward Transconductance
22
–––
–––
Total Gate Charge
–––
9.3
14
Qgs1
Pre-Vth Gate-to-Source Charge
–––
2.5
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
0.8
–––
Qgd
Gate-to-Drain Charge
–––
2.9
–––
ID = 10A
Qgodr
–––
3.1
–––
See Fig. 16
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
3.7
–––
IGSS
gfs
Qg
Qoss
Output Charge
–––
6.1
–––
td(on)
Turn-On Delay Time
–––
6.3
–––
tr
Rise Time
–––
2.7
–––
td(off)
Turn-Off Delay Time
–––
9.7
–––
tf
Fall Time
–––
7.3
–––
Ciss
Input Capacitance
–––
1010
–––
Coss
Output Capacitance
–––
360
–––
Crss
Reverse Transfer Capacitance
–––
110
–––
e
e
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V, TJ = 125°C
VGS = -20V
S
VDS = 15V, ID = 10A
VDS = 15V
nC
nC
VGS = 4.5V
VDS = 10V, VGS = 0V
VDD = 15V, VGS = 4.5V
e
ID = 10A
ns
Clamped Inductive Load
pF
VDS = 15V
VGS = 0V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
c
dh
Typ.
–––
Max.
44
Units
mJ
–––
10
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
3.1
ISM
(Body Diode)
Pulsed Source Current
–––
–––
100
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.0
V
trr
Reverse Recovery Time
–––
28
42
ns
Qrr
Reverse Recovery Charge
–––
23
35
nC
2
ch
Conditions
MOSFET symbol
A
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 10A, VGS = 0V
e
TJ = 25°C, IF = 10A, VDD = 10V
di/dt = 100A/µs
e
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IRF7821
100
100
VGS
10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
VGS
10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
TOP
10
1
2.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
2.5V
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
1
0.1
0.1
1
10
0.1
100
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
T J = 150°C
10.0
T J = 25°C
1.0
VDS = 15V
20µs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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ID = 13A
VGS = 10V
1.5
(Normalized)
RDS(on) , Drain-to-Source On Resistance
100.0
ID, Drain-to-Source Current (Α)
1
1.0
0.5
6.0
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF7821
10000
12
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
VGS , Gate-to-Source Voltage (V)
ID= 10A
C, Capacitance (pF)
Coss = Cds + Cgd
Ciss
1000
Coss
Crss
100
VDS= 24V
VDS= 15V
10
8
6
4
2
0
10
1
10
0
100
5
10
15
20
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
100.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100
T J = 150°C
10.0
1.0
T J = 25°C
10
1msec
1
10msec
VGS = 0V
0.1
0.1
0.0
0.5
1.0
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1.5
100µsec
Tc = 25°C
Tj = 150°C
Single Pulse
0.1
1.0
10.0
100.0
1000.0
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF7821
2.6
VGS(th) Gate threshold Voltage (V)
14
ID , Drain Current (A)
12
10
8
6
4
2
2.2
1.8
ID = 250µA
1.4
1.0
0
25
50
75
100
125
-75
150
-50
-25
25
50
75
100
125
150
T J , Temperature ( °C )
T J , Junction Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
0
Fig 10. Threshold Voltage Vs. Temperature
100
Thermal Response ( Z thJA )
D = 0.50
0.20
10
0.10
0.05
0.02
0.01
1
0.1
SINGLE PULSE
( THERMAL RESPONSE )
0.01
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
30
100
ID = 13A
25
20
15
T J = 125°C
10
T J = 25°C
5
0
2.0
4.0
6.0
8.0
10.0
EAS, Single Pulse Avalanche Energy (mJ)
RDS(on), Drain-to -Source On Resistance ( mΩ)
IRF7821
ID
4.5A
TOP
8.0A
BOTTOM 10A
80
60
40
20
0
25
VGS, Gate-to-Source Voltage (V)
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 13c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12. On-Resistance Vs. Gate Voltage
LD
VDS
15V
L
VDS
VDD
DRIVER
D.U.T
D.U.T
RG
+
V
- DD
IAS
VGS
20V
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
A
0.01Ω
tp
Fig 13a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
Fig 14a. Switching Time Test Circuit
VDS
90%
10%
VGS
I AS
Fig 13b. Unclamped Inductive Waveforms
6
td(on)
tf
td(off)
tr
Fig 14b. Switching Time Waveforms
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IRF7821
D.U.T
Driver Gate Drive
+
P.W.
ƒ
+
‚
-
-
„
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
*

RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Qgs1 Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 16. Gate Charge Test Circuit
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Fig 17. Gate Charge Waveform
7
IRF7821
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
Q

+  oss × Vin × f + (Qrr × Vin × f )
 2

This can be expanded and approximated by;
Ploss = (Irms × Rds(on ) )
*dissipated primarily in Q1.
2

 
Qgs 2

Qgd
+I ×
× Vin × f  +  I ×
× Vin × f 
ig
ig

 

+ (Qg × Vg × f )
+
 Qoss
× Vin × f 
 2

This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRF7821
SO-8 Package Details
D
5
A
8
6
7
6
5
H
1
2
3
0.25 [.010]
4
A
MAX
MIN
.0532
.0688
1.35
1.75
A1 .0040
.0098
0.10
0.25
b
.013
.020
0.33
0.51
c
.0075
.0098
0.19
0.25
D
.189
.1968
4.80
5.00
E
.1497
.1574
3.80
4.00
e
.050 BASIC
1.27 BAS IC
e1
6X
e
e1
8X b
0.25 [.010]
A
A1
MILLIMETERS
MIN
A
E
INCHES
DIM
B
MAX
.025 BASIC
0.635 BAS IC
H
.2284
.2440
5.80
6.20
K
.0099
.0196
0.25
0.50
L
.016
.050
0.40
1.27
y
0°
8°
0°
8°
K x 45°
C
y
0.10 [.004]
8X L
8X c
7
C A B
FOOT PRINT
NOT ES :
1. DIMENS IONING & T OLERANCING PER AS ME Y14.5M-1994.
8X 0.72 [.028]
2. CONT ROLLING DIMENS ION: MILLIMET ER
3. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ].
4. OUT LINE CONFORMS T O JEDEC OUT LINE MS -012AA.
5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS .
MOLD PROT RUS IONS NOT T O EXCEED 0.15 [.006].
6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS .
MOLD PROT RUS IONS NOT T O EXCEED 0.25 [.010].
6.46 [.255]
7 DIMENS ION IS THE LENGT H OF LEAD F OR S OLDERING T O
A S UBS T RAT E.
3X 1.27 [.050]
8X 1.78 [.070]
SO-8 Part Marking
EXAMPLE: T HIS IS AN IRF7101 (MOSFET )
INT ERNATIONAL
RECT IFIER
LOGO
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YWW
XXXX
F7101
DAT E CODE (YWW)
Y = LAS T DIGIT OF T HE YEAR
WW = WEEK
LOT CODE
PART NUMBER
9
IRF7821
SO-8 Tape and Reel
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 0.87mH
RG = 25Ω, IAS = 10A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ When mounted on 1 inch square copper board
… Rθ is measured at TJ approximately 90°C
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.1/04
10
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