PD - 94637B IRF8113 HEXFET® Power MOSFET Applications l Synchronous MOSFET for Notebook Processor Power l Synchronous Rectifier MOSFET for Isolated DC-DC Converters in Networking Systems Benefits l Very Low RDS(on) at 4.5V VGS l Low Gate Charge l Fully Characterized Avalanche Voltage and Current l 100% Tested for RG VDSS RDS(on) max Qg Typ. 30V 5.6m:@VGS = 10V 24nC A A D S 1 8 S 2 7 D S 3 6 D G 4 5 D SO-8 Top View Absolute Maximum Ratings Max. Units VDS Drain-to-Source Voltage Parameter 30 V VGS Gate-to-Source Voltage ± 20 ID @ TA = 25°C Continuous Drain Current, VGS @ 10V 17.2 ID @ TA = 70°C Continuous Drain Current, VGS @ 10V 13.8 IDM Pulsed Drain Current 135 f f c PD @TA = 25°C Power Dissipation PD @TA = 70°C Power Dissipation TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range A W 2.5 1.6 0.02 -55 to + 150 W/°C °C Thermal Resistance Parameter RθJL RθJA g Junction-to-Ambient fg Junction-to-Drain Lead Typ. Max. Units ––– 20 °C/W ––– 50 Notes through are on page 10 www.irf.com 1 6/30/05 IRF8113 Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units Drain-to-Source Breakdown Voltage 30 ––– ––– ∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.024 ––– V/°C Reference to 25°C, ID = 1mA RDS(on) Static Drain-to-Source On-Resistance mΩ ––– 4.7 5.6 ––– 5.8 6.8 V Conditions BVDSS VGS = 10V, ID = 17.2A VGS = 4.5V, ID = 13.8A VGS(th) Gate Threshold Voltage 1.5 ––– 2.2 V ∆VGS(th) Gate Threshold Voltage Coefficient ––– - 5.4 ––– mV/°C IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA ––– ––– 150 Gate-to-Source Forward Leakage ––– ––– 100 Gate-to-Source Reverse Leakage ––– ––– -100 gfs Forward Transconductance 73 ––– ––– Qg IGSS VGS = 0V, ID = 250µA e e VDS = VGS, ID = 250µA VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V S VDS = 15V, ID = 13.3A Total Gate Charge ––– 24 36 Qgs1 Pre-Vth Gate-to-Source Charge ––– 6.2 ––– Qgs2 Post-Vth Gate-to-Source Charge ––– 2.0 ––– Qgd Gate-to-Drain Charge ––– 8.5 ––– ID = 13.3A Qgodr Gate Charge Overdrive ––– 7.3 ––– See Fig. 16 Qsw Switch Charge (Qgs2 + Qgd) ––– 10.5 ––– Qoss Output Charge ––– 10 ––– nC RG Gate Resistance ––– 0.8 1.5 Ω td(on) Turn-On Delay Time ––– 13 ––– tr Rise Time ––– 8.9 ––– td(off) Turn-Off Delay Time ––– 17 ––– tf Fall Time ––– 3.5 ––– Ciss Input Capacitance ––– 2910 ––– Coss Output Capacitance ––– 600 ––– Crss Reverse Transfer Capacitance ––– 250 ––– VDS = 15V nC VGS = 4.5V VDS = 10V, VGS = 0V VDD = 15V, VGS = 4.5V e ID = 13.3A ns Clamped Inductive Load pF VDS = 15V VGS = 0V ƒ = 1.0MHz Avalanche Characteristics EAS Parameter Single Pulse Avalanche Energy IAR Avalanche Current c d Typ. Max. Units ––– 48 mJ ––– 13.3 A Diode Characteristics Parameter IS Continuous Source Current Min. Typ. Max. Units ––– ––– 3.1 (Body Diode) ISM Pulsed Source Current c MOSFET symbol A ––– ––– 135 Conditions showing the integral reverse (Body Diode) VSD Diode Forward Voltage ––– ––– 1.0 V p-n junction diode. TJ = 25°C, IS = 13.3A, VGS = 0V trr Reverse Recovery Time ––– 34 51 ns TJ = 25°C, IF = 13.3A, VDD = 10V Qrr Reverse Recovery Charge ––– 21 32 nC di/dt = 100A/µs 2 e e www.irf.com IRF8113 1000 1000 VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V 100 10 2.5V 20µs PULSE WIDTH Tj = 25°C 1 100 2.5V 10 20µs PULSE WIDTH Tj = 150°C 1 0.01 0.1 1 10 100 0.01 VDS, Drain-to-Source Voltage (V) 1 10 100 Fig 2. Typical Output Characteristics 1000 2.0 T J = 150°C T J = 25°C 10 VDS = 15V 20µs PULSE WIDTH 1 2.5 3.0 3.5 VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 4.0 ID = 16.6A VGS = 10V 1.5 (Normalized) RDS(on) , Drain-to-Source On Resistance ID, Drain-to-Source Current (Α) 0.1 VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 100 VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 1.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 T J , Junction Temperature (°C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRF8113 100000 12 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd VGS , Gate-to-Source Voltage (V) ID= 13.3A C, Capacitance (pF) Coss = Cds + Cgd 10000 Ciss 1000 Coss Crss 8 6 4 2 0 100 1 10 0 100 20 30 40 50 60 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 1000.0 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 10 Q G Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) OPERATION IN THIS AREA LIMITED BY R DS(on) 100 100.0 T J = 150°C 10.0 1.0 T J = 25°C 1msec 1 0.1 0.1 0.2 0.4 0.6 0.8 1.0 VSD, Source-toDrain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 1.2 100µsec 10 VGS = 0V 4 VDS= 24V VDS= 15V 10 10msec Tc = 25°C Tj = 150°C Single Pulse 0.1 1.0 10.0 100.0 1000.0 VDS , Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRF8113 18 2.2 VGS(th) Gate threshold Voltage (V) 16 ID , Drain Current (A) 14 12 10 8 6 4 2 0 2.0 1.8 ID = 250µA 1.6 1.4 1.2 1.0 0.8 25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150 T J , Temperature ( °C ) T J , Junction Temperature (°C) Fig 10. Threshold Voltage Vs. Temperature Fig 9. Maximum Drain Current Vs. Case Temperature Thermal Response ( Z thJA ) 100 10 D = 0.50 0.20 0.10 0.05 1 0.02 0.01 τJ 0.1 R1 R1 τJ τ1 τ1 R2 R2 τ2 R3 R3 τC τ τ3 τ2 Ci= τi/Ri Ci i/Ri 0.01 Ri (°C/W) R4 R4 τ3 τ4 τ4 τi (sec) 0.924 0.000228 13.395 0.1728 22.046 1.5543 14.911 22.5 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient www.irf.com 5 IRF8113 D.U.T RG VGS 20V DRIVER L VDS + V - DD IAS A 0.01Ω tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS EAS, Single Pulse Avalanche Energy (mJ) 200 15V ID 7.3A 8.2A BOTTOM 13.3A TOP 160 120 80 40 0 tp 25 50 75 100 125 150 Starting T J , Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current LD VDS I AS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T VGS Current Regulator Same Type as D.U.T. Pulse Width < 1µs Duty Factor < 0.1% 50KΩ 12V .2µF Fig 14a. Switching Time Test Circuit .3µF D.U.T. + V - DS VDS 90% VGS 3mA 10% IG ID Current Sampling Resistors Fig 13. Gate Charge Test Circuit 6 VGS td(on) tr td(off) tf Fig 14b. Switching Time Waveforms www.irf.com IRF8113 D.U.T Driver Gate Drive + • • • • D.U.T. ISD Waveform Reverse Recovery Current + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period * RG D= VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer - - Period P.W. + VDD + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRF8113 Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝ 2 ⎠ This can be expanded and approximated by; Ploss = (Irms × Rds(on ) ) 2 ⎛ ⎞ ⎛ Qgs 2 ⎞ Qgd +⎜I × × Vin × f ⎟ + ⎜ I × × Vin × f ⎟ ig ig ⎝ ⎠ ⎝ ⎠ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝ 2 ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. 8 *dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic www.irf.com IRF8113 SO-8 Package Details D DIM B 8 6 7 6 MIN .0532 .0688 1.35 1.75 A1 .0040 .0098 0.10 0.25 b .013 .020 0.33 0.51 c .0075 .0098 0.19 0.25 D .189 .1968 4.80 5.00 E .1497 .1574 3.80 4.00 e .050 BAS IC 1.27 BAS IC e1 A 5 H E 1 6X 2 3 0.25 [.010] 4 A e e1 0.25 [.010] MAX .025 BAS IC 0.635 BAS IC H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 y 0° 8° 0° 8° K x 45° A C A1 8X b MILLIMETERS MAX 5 A INCHES MIN y 0.10 [.004] 8X L 8X c 7 C A B FOOTPRINT NOT ES : 1. DIMENS IONING & T OLERANCING PER AS ME Y14.5M-1994. 8X 0.72 [.028] 2. CONT ROLLING DIMENS ION: MILLIMET ER 3. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]. 4. OUT LINE CONFORMS T O JEDEC OUT LINE MS -012AA. 5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS . MOLD PROTRUS IONS NOT T O EXCEED 0.15 [.006]. 6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS . MOLD PROTRUS IONS NOT T O EXCEED 0.25 [.010]. 6.46 [.255] 7 DIMENS ION IS THE LENGT H OF LEAD FOR S OLDERING TO A S UBS T RAT E. 3X 1.27 [.050] 8X 1.78 [.070] SO-8 Part Marking EXAMPLE: T HIS IS AN IRF7101 (MOS FET ) INT ERNAT IONAL RECT IFIER LOGO XXXX F7101 DAT E CODE (YWW) P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) Y = LAS T DIGIT OF T HE YEAR WW = WEEK A = ASS EMBLY S IT E CODE LOT CODE PART NUMBER www.irf.com 9 IRF8113 SO-8 Tape and Reel TERMINAL NUMBER 1 12.3 ( .484 ) 11.7 ( .461 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 330.00 (12.992) MAX. 14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 0.54mH RG = 25Ω, IAS = 13.3A. Pulse width ≤ 400µs; duty cycle ≤ 2%. When mounted on 1 inch square copper board Rθ is measured at TJ approximately 90°C Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.6/05 10 www.irf.com