TI SN65LVDM1676DGG

SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
D Sixteen Low-Voltage Differential
Transceivers Designed for Signaling Rates†
D
D
D
D
D
D
D
D
D
Up to 630 Mbps
Simplex (Point-to-Point) and Half-Duplex
(Multipoint) Interface
Typical Differential Output Voltage of
340 mV Into a 50-Ω Load
Integrated 110-Ω Line Termination on
‘LVDM1677 Product
Propagation Delay Time:
− Driver: 2.5 ns Typ
− Receiver: 3 ns Typ
Recommended Maximum Transfer Rate:
− Driver: 650 M-Transfers/s
− Receiver: 350 M-Transfers/s
Driver is High Impedance When Disabled or
With VCC < 1.5 V for Power Up/Down
Glitch-Free Performance and Hot-Plugging
Events
Bus-Terminal ESD Protection Exceeds
12 kV
Low-Voltage TTL (LVTTL) Logic Input
Levels Are 5-V Tolerant
Packaged in Thin Shrink Small-Outline
Package With 20 mil Terminal Pitch
description
SN65LVDM1676DGG ( Marked as LVDM1676)
SN65LVDM1677DGG (Marked as LVDM1677)
(TOP VIEW)
GND
VCC
VCC
GND
ATX/RX
A1A
A2A
A3A
A4A
BTX/RX
B1A
B2A
B3A
B4A
GND
VCC
VCC
GND
C1A
C2A
C3A
C4A
CTX/RX
D1A
D2A
D3A
D4A
DTX/RX
GND
VCC
VCC
GND
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
D4Y
D4Z
The SN65LVDM1676 and SN65LVDM1677
27
38
(integrated termination) are sixteen differential
28
37
line drivers and receivers configured as trans29
36
ceivers that use low-voltage differential signaling
30
35
(LVDS) to achieve signaling rates in excess of
31
34
600 Mbps. These products are similar to
32
33
TIA/EIA-644 standard compliant devices
(SN65LVDS) counterparts except that the output
current of the drivers are doubled. This modification provides a minimum differential output voltage magnitude
of 247 mV into a 50-Ω load and allows double-terminated lines and half-duplex operation. The receivers detect
a voltage difference of 100 mV with up to 1 V of ground potential difference between a transmitter and receiver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
Copyright  2001 − 2004, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
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1
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
description (continued)
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The large number of transceivers integrated into the same substrate along with
the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for
synchronous parallel data transfers. (Note: The ultimate rate and distance of data transfer is dependent upon
the attenuation characteristics of the media, the noise coupling to the environment, and other system
characteristics.)
The SN65LVDM1676 and SN65LVDM1677 are characterized for operation from −40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
(Y − Z)
TX/RX
A
Y
Z
A
VID ≥ 100 mV
−100 mV < VID < 100 mV
L
NA
Z
Z
H
L
NA
Z
Z
?
VID ≤ 100 mV
Open circuit
L
NA
Z
Z
L
L
NA
Z
Z
H
NA
H
L
L
H
Z
NA
H
H
H
L
Z
H = high level, L= low level, Z= high impedance, ? = indeterminate
LVD Transceiver
Y
A
Z
TX/RX
2
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SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
logic diagram (positive logic)
A1A
A1Y
B1A
A1Z
A2A
B1Z
A2Y
B2A
A2Z
BTX/RX
A3Y
B3A
A3Z
A4A
A4Y
B4A
C1Y
D1A
C2Y
D2A
D2Y
D2Z
CTX/RX
DTX/RX
C3Y
D3A
C3Z
C4A
D1Y
D1Z
C2Z
C3A
B4Y
B4Z
C1Z
C2A
B3Y
B3Z
A4Z
C1A
B2Y
B2Z
ATX/RX
A3A
B1Y
D3Y
D3Z
C4Y
D4A
C4Z
D4Y
D4Z
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3
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
equivalent input and output schematic diagrams
VCC
VCC
50 Ω
A, TX/RX Input
10 kΩ
5Ω
Y or Z
Output
7V
300 kΩ
7V
VCC
300 kΩ
VCC
300 kΩ
5Ω
A Output
Z Input
Y Input
7V
7V
110 Ω
’LVDM1677 Product Only
4
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7V
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V
Input voltage range: A, TX/RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V
Differential input voltage magnitude, VID, (SN65LVDM1677 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V
Receiver output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Electrostatic discharge: Y, Z, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:8 kV, B:600 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:7 kV, B:500 V
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
3. This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no airflow.
DISSIPATION RATING TABLE
TA ≤ 25°C
POWER RATING
PACKAGE
OPERATING FACTOR‡
ABOVE TA = 25°C
DGG
2094 mW
16.7 mW/°C
‡ All typical values are at 25°C and with a 3.3-V supply.
TA = 85°C
POWER RATING
1089 mW
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC
3
3.3
3.6
High-level input voltage, VIH
2
0.1
ŤVIDŤ
Common-mode input voltage, VIC
2.4 –
2
0.8
V
0.6
V
ŤVIDŤ
Receiver low-level output current, IOL
−8
Operating free-air temperature, TA
V
2
VCC−0.8
8
Receiver high-level output current, IOH
V
V
Low-level input voltage, VIL
Magnitude of differential input voltage, VID
UNIT
V
mA
mA
−40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
device
TYP‡
MAX
Driver enabled, receiver disabled, RL 50 Ω
140
175
Driver disabled, receiver enabled, no load
45
60
PARAMETER
ICC
Supply current
TEST CONDITIONS
MIN
UNIT
mA
‡ All typical values are at 25°C and with a 3.3-V supply.
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5
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
driver
PARAMETER
TEST CONDITIONS
VOD
Differential output voltage magnitude
∆VOD
Change in differential output voltage magnitude
between logic states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage between logic states
VOC(PP)
IIH
Peak-to-peak common-mode output voltage
IIL
Low-level input current
IOS
Short-circuit output current
IO(OFF)
CIN
Power-off output current
RL = 50 Ω, See Figure 1 and Figure 2
See Figure 3
High-level input current
MIN
TYP
MAX
247
340
454
mV
−50
50
1.125
1.375
−50
50
mV
50
150
mV
3
20
µA
2
10
µA
10
mA
10
mA
±10
µA
VIH = 2 V
VIL = 0.8 V
VOY or VOZ = 0 V
VOD = 0 V
VCC = 1.5 V,
VO = 2.4 V
VI = 0.4 sin (4E6pt) + 0.5 V
Input capacitance
UNIT
5
V
pF
receiver
PARAMETER
TEST CONDITIONS
VIT+
VIT−
Positive-going differential input voltage threshold
VOH
VOL
High-level output voltage
II
Input current (Y or Z inputs)
IID
Differential input current |IIY − IIZ| (inputs)
See Figure 6 and Table 1
IOH = −8 mA
IOL = 8 mA
Low-level output voltage
’LVDM1676
’LVDM1677
6
TYP†
MAX
UNIT
100
Negative-going differential input voltage threshold
II(OFF)
Power-off input current (Y or Z inputs)
† All typical values are at 25°C and with a 3.3-V supply.
MIN
2.4
VIY = 0.2 V and VIZ = 0 V,
VIY = 2.4 V and VIZ = 2.2 V
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V
0.4
VI = 0 V
VI = 2.4 V
VIY = 0 V and VIZ = 100 mV,
VIY = 2.4 V and VIZ = 2.3 V
VCC = 0 V,
mV
−100
VI = 2.4 V
−24
−1.2
5
1.5
−40
−8
V
µA
A
10
µA
2.2
mA
±25
µA
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
driver
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output
1.3
2.5
3.6
ns
Propagation delay time, high-to-low-level output
1.3
2.5
3.6
ns
tr
tf
Differential output signal rise time
0.5
1.2
ns
0.5
1.2
ns
tsk(p)
tsk(o)
Pulse skew (|tPHL − tPLH|)
0.1
0.6
ns
0.1
0.4
ns
1
ns
11
20
ns
10
20
ns
3
10
ns
tsk(pp)
tPZH
tPZL
tPHZ
RL = 50 Ω,
CL = 10 pF,
See Figure 4
Differential output signal fall time
Channel-to-channel output skew†
Part-to-part skew‡
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
See Figure 5
tPLZ
Propagation delay time, low-level-to-high-impedance output
3
10
ns
† tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical specified loads.
‡ tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
receiver
PARAMETER
TEST CONDITIONS
MIN
TYP§
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output
1.5
3
4.5
ns
Propagation delay time, high-to-low-level output
1.5
3
4.5
ns
tr
tf
Output signal rise time
0.6
1.6
ns
0.6
1.6
ns
tsk(p)
tsk(o)
Pulse skew (|tPHL − tPLH|)
0.2
0.8
ns
Channel-to-channel output skew†
Part-to-part skew‡
0.7
1.2
ns
1
ns
9
15
ns
8
15
ns
12
20
tsk(pp)
tPZH
tPZL
tPHZ
CL = 10 pF,
See Figure 7
Output signal fall time
Propagation delay time, high-impedance-to-high-level output
See Figure 8
Propagation delay time, high-impedance-to-low-level output
See Figure 8
Propagation delay time, high-level-to-high-impedance output
ns
See Figure 8
tPLZ
Propagation delay time, low-level-to-high-impedance output
11
20
ns
† tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical specified loads.
‡ tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
§ All typical values are at 25°C and with a 3.3-V supply.
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7
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
IOY
Y
II
Z
VOD
IOZ
VOY
VI
VOC
VOZ
(VOY + VOZ)/2
Figure 1. Driver Voltage and Current Definitions
3.75 kΩ
Y
VOD
Input
Z
RL
3.75 kΩ
±
0 V ≤ VTEST ≤ 2.4 V
Figure 2. Driver VOD Test Circuit
Y
25 Ω ± 1% (2 Places)
3V
A
0V
Input
Z
VOC(PP)
VOC
CL = 10 pF
(2 Places)
VOC(SS)
VOC
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse
width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP) is made
on test equipment with a −3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
8
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SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
3V
VCC/2
0V
Input
tpLH
Y
Input
VOD
Z
tpHL
50 Ω ± 1 %
100%
80%
VOD(H)
Output
CL = 10 pF
(2 Places)
0V
VOD(L)
20%
0%
tf
tr
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse
width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
25 Ω ± 1% (2 Places)
Y
0.8 V or 2 V
Z
CL = 10 pF
(2 Places)
TX/RX
VOY
VOZ
+
−
1.2 V
3V
VCC/2
0V
TX/RX
tpZH
tpHZ
≅ 1.4 V
1.25 V
1.2 V
VOY or VOZ
tpZL
tpLZ
1.2 V
1.15 V
≅1V
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse
width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
VOZ or VOY
Figure 5. Enable and Disable Time Circuit and Definitions
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9
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
Y
Y
VID
Z
(VIY + VIZ)/2
VIY
VIC
VO
VIZ
Figure 6. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
VIY
1.25 V
VIZ
1.15 V
VID
100 mV
VIC
1.2 V
1.15 V
1.25 V
−100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
−100 mV
2.35 V
0.1 V
0V
100 mV
0.05 V
0V
0.1 V
−100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
−600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
−600 mV
2.1 V
0.6 V
0V
600 mV
0.3 V
0V
0.6 V
−600 mV
0.3 V
VID
VIY
1.4 V
VIZ
1V
VID
0.4 V
0V
VIY
VIZ
CL = 10 pF
VO
−0.4 V
tpHL
VO
tpLH
80%
20%
tf
~VCC
VCC/2
~0V
tr
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse
width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 7. Timing Test Circuit and Waveforms
10
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SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
1.2 V
Z
500 Ω
A
Y
10 pF
VO
±
VTEST
TX/RX
NOTE: All input pulses are supplied by a generator having the following
characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture
capacitance within 0,06 m of the D.U.T.
2.5 V
VTEST
Y
1V
3V
VCC/2
0V
TX/RX
tpLZ
tpZL
2.5 V
VCC/2
A
VOL + 0.5 V
VOL
0V
VTEST
Y
1.4 V
3V
VCC/2
0V
TX/RX
tpHZ
tpZH
V
−
OH 0.5 V
A
VOH
VCC/2
0V
Figure 8. Enable/Disable Time Test Circuit and Waveforms
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11
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
VIC − Common-Mode Input Voltage − V
VCC > 3.15 V
VCC = 3 V
2
1.5
1
0.5
MIN
0
0
0.1
0.2
0.4
0.3
0.5
0.6
|VID|− Differential Input Voltage − V
Figure 9
DRIVER
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
VCC = 3.3 V
TA = 25°C
VCC = 3.3 V
TA = 25°C
V OH − High-Level Output Voltage − V
V OL − Low-Level Output Voltage − V
4
3
2
1
0
2.5
2
1.5
1
.5
0
0
2
4
6
8
10
12
IOL − Low-Level Output Current − mA
0
−2
−4
−6
IOH − High-Level Output Current − mA
Figure 10
12
3
Figure 11
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−8
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
RECEIVER
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
4
VCC = 3.3 V
TA = 25°C
VOL − Low-Level Output Votlage − V
VOH − High-Level Output Voltage − V
VCC = 3.3 V
TA = 25°C
3
2
1
4
3
2
1
0
0
0
−20
−40
−60
IOH − High-Level Output Current − mA
−80
0
20
40
60
IOL − Low-Level Output Current − mA
80
Figure 13
Figure 12
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13
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
driver eye pattern
test conditions
D VCC = 3.3 V
D TA = 25°C (ambient temperature)
D All 16 channels switching simultaneously with NRZ data. Scope is triggered at the same frequency with
pulse. Input signal level = 0 to 3 V single ended.
D Resistive loading with no added capacitance
equipment
HP E8043A Mainframe System
Tektronix PS2521
Programmable
Power Supply
HPE4841A 660 MHz Data Generator
4
HPE4841A 660 MHz Data Generator
4
Bench Test Board
HPE4841A 660 MHz Data Generator
4
Tektronix P6248
1.7 GHz Differential Probe
HPE4841A 660 MHz Data Generator
4
Tektronix TDS 784 1 GHz
Oscilloscope
Figure 14. Driver Test Equipment Setup
100 Mbps
650 Mbps
Figure 15. Typical Driver Eye Pattern for the SN65LVDM1676
14
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SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
receiver eye pattern
test conditions
D VCC = 3.3 V
D TA = 25°C (ambient temperature)
D All 16 channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with NRZ
data. Input signal level is 1 V to 1.4 V differential.
D 50-Ω resistive loading with no added capacitance
equipment
HP E8043A Mainframe System
Tektronix PS2521
Programmable
Power Supply
HPE4841A 660 MHz Data Generator
8
HPE4841A 660 MHz Data Generator
8
Bench Test Board
HPE4841A 660 MHz Data Generator
8
Tektronix P6248
1.7 GHz Differential Probe
HPE4841A 660 MHz Data Generator
8
Tektronix TDS 784 1 GHz
Oscilloscope
Figure 16. Receiver Test Equipment Setup
100 Mbps
350 Mbps
Figure 17. Typical Receiver Eye Pattern for the SN65LVDM1677
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15
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between −50 mV and 50 mV
and within its recommended input common-mode voltage range. TI’s LVDS receiver is different, however, in how
it handles the open-input circuit situation.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 18. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level, regardless of the differential input voltage.
VCC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
VIT ≈ 2.3 V
Figure 18. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 50-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
16
WWW.TI.COM
SLLS430B − NOVEMBER 2000 − REVISED OCTOBER 2004
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°−ā 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
WWW.TI.COM
17
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LVDM1676DGG
ACTIVE
TSSOP
DGG
64
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDM1676DGGG4
ACTIVE
TSSOP
DGG
64
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDM1676DGGR
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDM1676DGGRG4
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDM1677DGG
ACTIVE
TSSOP
DGG
64
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDM1677DGGG4
ACTIVE
TSSOP
DGG
64
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDM1677DGGR
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDM1677DGGRG4
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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