INTEGRATED CIRCUITS DATA SHEET TDA8360; TDA8361; TDA8362 Integrated PAL and PAL/NTSC TV processors Objective specification File under Integrated Circuits, IC02 Philips Semiconductors March 1994 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 FEATURES Additional features GENERAL DESCRIPTION Available in TDA8360, TDA8361 and TDA8362 TDA8360 The TDA8360, TDA8361 and TDA8362 are single-chip TV processors which contain nearly all small signal functions that are required for a colour television receiver. For a complete receiver the following circuits need to be added: a base-band delay line (TDA4661), a tuner and output stages for audio, video and horizontal and vertical deflection. • Vision IF amplifier with high sensitivity and good differential gain and phase • Multistandard FM sound demodulator (4.5 MHz to 6.5 MHz) • Integrated chrominance trap and bandpass filters (automatically calibrated) • Alignment-free PAL colour decoder for all PAL standards, including PAL-N and PAL-M. TDA8361 • PAL/NTSC colour decoder with automatic search system • Integrated luminance delay line • Source selection for external audio/video (A/V) inputs (separate Y/C signals can also be applied). • RGB control circuit with linear RGB inputs and fast blanking TDA8362 • Horizontal synchronization with two control loops and alignment-free horizontal oscillator without external components • Multistandard vision IF circuit (positive and negative modulation) • Vertical count-down circuit (50/60 Hz) and vertical preamplifier • Low dissipation (700 mW) • Source selection for external A/V inputs (separate Y/C signals can also be applied) • Small amount of peripheral components compared with competition ICs • Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications. • PAL/NTSC colour decoder with automatic search system Because of the different functional contents of the ICs the set maker can make the optimum choice depending on the requirements for the receiver. The TDA8360 is intended for simple PAL receivers (all PAL standards, including PAL-N and PAL-M are possible). The TDA8361 contains a PAL/NTSC decoder and has an A/V switch. • Only one adjustment (vision IF demodulator) • The supply voltage for the ICs is 8 V. They are mounted in a shrink DIL envelope with 52 pins and are pin compatible. For real multistandard applications the TDA8362 is available. In addition to the extra functions which are available in the TDA8361, the TDA8362 can handle signals with positive modulation and it supplies the signals which are required for the SECAM decoder TDA8395. ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS PIN POSITION MATERIAL CODE TDA8360 52 shrink DIL plastic SOT247AG TDA8361 52 shrink DIL plastic SOT247AG TDA8362 52 shrink DIL plastic SOT247AG March 1994 2 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP supply voltage 7.2 8.0 8.8 V IP supply current − 80 − mA Input voltages V45,46(rms) video IF amplifier sensitivity (RMS value) − 70 100 µV V5(rms) sound IF amplifier sensitivity (RMS value) − 1 − mV V6(rms) external audio input (RMS value) TDA8361, TDA8362 − 350 − mV V15(p-p) external CVBS input (peak-to-peak value) TDA8361, TDA8362 − 1 − V V22,23,24(p−p) RGB inputs (peak-to-peak value) − 0.7 − V Output signals VO(p-p) demodulated CVBS output (peak-to-peak value) − 2.4 − V I47 tuner AGC control current 0 − 5 mA V44 AFC output voltage swing − 6 − V V50(rms) audio output voltage (RMS value) − 700 − mV V18,19,20(p-p) RGB output signal amplitudes (peak-to-peak value) − 4 − V I37 horizontal output current 10 − − mA I43 vertical output current 1 − − mA 0 − 5 V Control voltages Vcontrol March 1994 control voltages for Volume, Contrast, Saturation, Brightness, Hue and Peaking 3 March 1994 4 SOIF volume control DEC DEM 5 51 50 1 4 8 7 44 3 2 46 45 LIMITER VOLUME TEST VIDEO AMPLIFIER DEMODULATOR IF AMPLIFIER 48 9 10 VP PLL PREAMPLIFIER MUTE SUPPLY VIDEO IDENTIFICATION AFC AND SAMPLEAND-HOLD GND2 GND1 11 49 AGC 47 DEC BG 52 41 VFB LINE OSCILLATOR PHASE 1 40 CVBS INT 13 TRAP AND BYPASS POWER RESET 36 PH2LF VSTART COINCIDENCE DETECTOR TDA8360 42 PH1LF 38 37 HOUT PEAKIN 14 Y DELAY PEAKING 35 COLOUR KILLERS XTAL OSCILLATOR 34 XTAL2 PWL LUMINANCE MATRIX MATRIX PAL IDENTIFICATION XTAL1 sandcastle CHROMINANCE BANDPASS ACC AMPLIFIER TUNING PHASE 2 39 Fig.1 Block diagram for TDA8360. DEC FT 12 TUNING NOISE DETECTOR H AND V SEPARATION VERTICAL DIVIDER VERTICAL OUTPUT 43 VOUT VRAMP FBI/SCO CON 25 17 BRI OUTPUT STAGES CLAMP SWITCH CLAMPS SET DEMODULATOR PHASE DETECTOR 18 19 20 21 22 23 24 29 28 26 31 30 33 MLA621 - 1 BOUT GOUT ROUT RGBIN RIN GIN BIN B-Y input from TDA4661 R-Y input SAT B-Y output R-Y output to TDA4661 DET Integrated PAL and PAL/NTSC TV processors AUOUT AUDEEM DEC DIG IDENT IFOUT AFCOUT IFDEM2 IFDEM1 IFIN2 IFIN1 AGCOUT TUNE ADJ DEC AGC flyback Philips Semiconductors Objective specification TDA8360; TDA8361; TDA8362 March 1994 5 SOIF volume control DEC DEM AUOUT 5 51 50 6 1 4 8 7 44 3 2 46 45 LIMITER VOLUME TEST VIDEO AMPLIFIER DEMODULATOR IF AMPLIFIER 48 9 10 VP PLL PREAMPLIFIER MUTE SUPPLY VIDEO IDENTIFICATION AFC AND SAMPLEAND-HOLD GND2 GND1 11 49 AGC 47 52 41 VFB CVBS INT 13 38 ACC AMPLIFIER TUNING PHASE 2 39 37 HOUT CHROMA 16 CHROMINANCE SWITCH Y DELAY PEAKING XTAL1 sandcastle CHROMINANCE BANDPASS 14 36 PEAKIN CVBS EXT 15 LUMINANCE SWITCH TRAP AND BYPASS POWER RESET COINCIDENCE DETECTOR LINE OSCILLATOR PHASE 1 40 VSTART PH2LF Fig.2 Block diagram for TDA8361. DEC FT 12 TDA8361 TUNING NOISE DETECTOR 42 VRAMP H AND V SEPARATION VERTICAL DIVIDER VERTICAL OUTPUT 43 VOUT DEC BG DEC AGC FBI/SCO 35 PWL LUMINANCE MATRIX MATRIX SYSTEM MANAGER COLOUR KILLERS XTAL OSCILLATOR 34 XTAL2 17 CON BRI 25 OUTPUT STAGES CLAMP SWITCH CLAMPS SET DEMODULATOR PHASE DETECTOR HUE CONTROL 18 19 20 21 22 23 24 29 28 26 31 30 33 27 MLA622 - 1 BOUT GOUT ROUT RGBIN RIN GIN BIN B-Y input from TDA4661 R-Y input SAT B-Y output R-Y output to TDA4661 DET HUE Integrated PAL and PAL/NTSC TV processors EXTAU AUDEEM DEC DIG IDENT IFOUT AFCOUT IFDEM2 IFDEM1 IFIN2 IFIN1 AGCOUT TUNE ADJ PH1LF flayback Philips Semiconductors Objective specification TDA8360; TDA8361; TDA8362 March 1994 6 DEC DIG 11 GND2 8 SOIF 5 51 6 1 7 3 2 49 46 GND1 9 VP 10 SUPPLY LIMITER SWITCH VOLUME 52 50 DEC BG VIDEO IDENTIFICATION DEMODULATOR IF AMPLIFIER 4 48 TEST PLL PREAMPLIFIER MUTE VIDEO AMPLIFIER AFC AND SAMPLEAND-HOLD AGC 47 AGCOUT 44 41 VFB 13 15 CVBS INT CVBSEXT 16 LUMINANCE SWITCH CHROMINANCE SWITCH NOISE DETECTOR 36 38 37 PEAKIN 14 Y DELAY PEAKING CHROMINANCE BANDPASS ACC AMPLIFIER XTAL1 sandcastle HOUT COINCIDENCE DETECTOR TUNING PHASE 2 39 FBI/SCO Fig.3 Block diagram for TDA8362. DEC FT 12 TUNING TRAP AND BYPASS LINE OSCILLATOR PHASE 1 40 flyback PH2LF VSTART H AND V SEPARATION CHROMA 42 TDA8362 POWER RESET VERTICAL DIVIDER VERTICAL OUTPUT 43 VOUT AFCOUT DEC AGC PH1LF 35 PWL LUMINANCE MATRIX MATRIX COLOUR KILLERS SYSTEM MANAGER XTAL OSCILLATOR 34 21 25 BRI 17 OUTPUT STAGES CLAMP SWITCH CLAMPS SET DEMODULATOR PHASE DETECTOR HUE CONTROL 27 HUE CON SAT RGBIN 26 32 XTALOUT XTAL2 18 19 20 22 23 24 29 28 31 30 33 MBC214 - 1 BOUT GOUT ROUT RIN GIN BIN B-Y input from TDA4661 R-Y input B-Y output R-Y output to TDA4661 DET Integrated PAL and PAL/NTSC TV processors volume control DEC DEM AUDEEM EXTAU IFDEM2 IFOUT IFDEM1 TUNE ADJ IFIN2 IFIN1 45 IDENT AUOUT VRAMP Philips Semiconductors Objective specification TDA8360; TDA8361; TDA8362 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 PINNING (TDA8362) SYMBOL PIN DESCRIPTION AUDEEM 1 audio de-emphasis and ± modulation switch IFDEM1 2 IF demodulator tuned circuit IFDEM2 3 IF demodulator tuned circuit IDENT 4 video identification output/MUTE input AUDEEM 1 52 DEC BG SOIF 5 sound IF input and volume control IFDEM1 2 51 DEC DEM EXTAU 6 external audio input IFDEM2 3 50 AUOUT IFOUT 7 IF video output IDENT 4 49 TUNEADJ DECDIG 8 decoupling digital supply GND1 9 ground 1 VP 10 supply voltage (+8 V) GND2 11 ground 2 DECFT 12 decoupling filter tuning 13 internal CVBS input SOIF 5 48 DECAGC EXTAU 6 47 AGCOUT IFOUT 7 46 IFIN2 DEC DIG 8 45 IFIN1 CVBSINT GND1 9 44 AFCOUT PEAKIN 14 peaking control input 43 VOUT CVBSEXT 15 external CVBS input CHROMA 16 chrominance and A/V switch input BRI 17 brightness control input BOUT 18 blue output V P 10 42 VRAMP GND2 11 DEC FT 12 41 VFB CVBS INT 13 40 PH1LF GOUT 19 green output 39 PH2LF ROUT 20 red output CVBS EXT 15 38 FBI/SCO RGBIN 21 RGB insertion and blanking input CHROMA 16 37 HOUT RIN 22 red input 36 VSTART GIN 23 green input BIN 24 blue input CON 25 contrast control input SAT 26 saturation control input TDA8362 PEAKIN 14 BRI 17 BOUT 18 35 XTAL2 GOUT 19 34 XTAL1 ROUT 20 33 DET HUE 27 hue control input (or chrominance output) 32 XTALOUT BYI 28 B−Y input signal RIN 22 31 BYO RYI 29 R−Y input signal GIN 23 30 RYO RYO 30 R−Y output signal BYO 31 B−Y output signal XTALOUT 32 4.43 MHz output for TDA8395 DET 33 loop filter burst phase detector XTAL1 34 3.58 MHz crystal connection XTAL2 35 4.43 MHz crystal connection VSTART 36 supply/start horizontal oscillator HOUT 37 horizontal output FBI/SCO 38 flyback input/sandcastle output PH2LF 39 phase 2 loop filter PH1LF 40 phase 1 loop filter RGBIN 21 BIN 24 29 RYI CON 25 28 BYI SAT 26 27 HUE MBC203 Fig.4 Pin configuration for TDA8362. March 1994 7 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL VFB PIN 41 DESCRIPTION vertical feedback input VRAMP 42 vertical ramp generator VOUT 43 vertical output AFCOUT 44 AFC output IFIN1 45 IF input 1 IFIN2 46 IF input 2 AGCOUT 47 tuner AGC output DECAGC 48 AGC decoupling capacitor TUNEADJ 49 tuner take-over adjustment AUOUT 50 audio output DECDEM 51 decoupling sound demodulator DECBG 52 decoupling bandgap supply TDA8360 The TDA8360 has the following differences to the pinning: Pin 6: external audio input not connected Pin 15: external CVBS input not connected Pin 16: chrominance and A/V switch input not connected Pin 27: hue control input not connected. TDA8361 The TDA8361 has the following differences to the pinning: Pin 1: only audio de-emphasis Pin 27: only hue control Pin 32: 4.43 MHz output for TDA8395 is not connected. FUNCTIONAL DESCRIPTION Video IF amplifier The IF amplifier contains 3 AC-coupled control stages with a total gain control range of greater than 60 dB. The sensitivity of the circuit is comparable with that of modern IF ICs. March 1994 TDA8360; TDA8361; TDA8362 The reference carrier for the video demodulator is obtained by means of passive regeneration of the picture carrier. The external reference tuned circuit is the only remaining adjustment of the IC. In the TDA8362 the polarity of the demodulator can be switched so that the circuit is suitable for both positive and negative modulated signals. The AFC circuit is driven with the same reference signal as the video demodulator. To ensure that the video content does not disturb the AFC operation a sample-and-hold circuit is incorporated; the capacitor for this function is internal. The AFC output voltage is 6 V. The AGC detector operates on levels, top sync for negative modulated and top white for positive modulated signals.The AGC detector time constant capacitor is connected externally. This is mainly because of the flexibility of the application. The time constant of the AGC system during positive modulation (TDA8362) is slow, this is to avoid any visible picture variations. This, however, causes the system to react very slowly to sudden changes in the input signal amplitude. 8 To overcome this problem a speed-up circuit has been included which detects whether the AGC detector is activated every frame period. If, during a 3-frame period, no action is detected the speed of the system is increased. When the incoming signal has no peak white information (e.g. test lines in the vertical retrace period) the gain would be video signal dependent. To avoid this effect the circuit also contains a black level AGC detector which is activated when the black level of the video signal exceeds a certain level. The TDA8361 and TDA8362 contain a video identification circuit which is independent of the synchronization circuit. Therefore search tuning is possible when the display section of the receiver is used as a monitor. In the TDA8360 this circuit is only used for stable OSD at no signal input. In the normal television mode the identification output is connected to the coincidence detector, this applies to all three devices. The identification output voltage is LOW when no transmitter is identified. In this condition the sound demodulator is switched off (mute function). When a transmitter is identified the output voltage is HIGH. The voltage level is dependent on the frequency of the incoming chrominance signal. Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors Sound circuit The sound bandpass and trap filters have to be connected externally. The filtered intercarrier signal is fed to a limiter circuit and is demodulated by means of a PLL demodulator. The PLL circuit tunes itself automatically to the incoming signal, consequently, no adjustment is required. The volume is DC controlled. The composite audio output signal has an amplitude of 700 mV RMS at a volume control setting of −6 dB. The de-emphasis capacitor has to be connected externally. The non-controlled audio signal can be obtained from this pin via a buffer stage. The amplitude of this signal is 350 mV RMS. The TDA8361 and TDA8362 external audio input signal must have an amplitude of 350 mV RMS. The audio/video switch is controlled via the chrominance input pin. Synchronization circuit The sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed level. The sync pulses are then fed to the slicing stage (separator) which operates at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence detector is used for transmitter identification and to detect whether the line oscillator is synchronized. When the circuit is not synchronized the voltage on the peaking control pin (pin 14) is LOW so that this condition can be detected externally. The first PLL has a very high static steepness, this ensures that the phase of the picture is independent of the line frequency. The line oscillator operates at twice the line frequency. March 1994 TDA8360; TDA8361; TDA8362 The oscillator network is internal. Because of the spread of internal components an automatic adjustment circuit has been added to the IC. The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. This results in a free-running frequency which deviates less than 2% from the typical value. The circuit employs a second control loop to generate the drive pulses for the horizontal driver stage. X-ray protection can be realised by switching the pin of the second control loop to the positive supply line. The detection circuit must be connected externally. When the X-ray protection is active the horizontal output voltage is switched to a high level. When the voltage on this pin returns to its normal level the horizontal output is released again. The IC contains a start-up circuit for the horizontal oscillator. When this feature is required a current of 6.5 mA has to be supplied to pin 36. For an application without start-up both supply pins (10 and 36) must be connected to the 8 V supply line. The drive signal for the vertical ramp generator is generated by means of a divider circuit. The RC network for the ramp generator is external. Integrated video filters The circuit contains a chrominance bandpass and trap circuit. The filters are realised by means of gyrator circuits and are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. In the TDA8361 and TDA8362 the chrominance trap is active only when the separate chrominance input pin is connected to ground or to the positive supply voltage and when a colour signal is recognized. 9 When the pin is left open-circuit the trap is switched off so that the circuit can also be used for S-VHS applications. The luminance delay line and the delay for the peaking circuit are also realised by means of gyrator circuits. Colour decoder The colour decoder in the various ICs contains an alignment-free crystal oscillator, a colour killer circuit and colour difference demodulators. The 90° phase shift for the reference signal is achieved internally. Because the main differences of the 3 ICs are found in the colour decoder the various types will be discussed. TDA8360 This IC contains only a PAL decoder. Depending on the frequency of the crystals which are connected to the IC the decoder can demodulate all PAL standards. Because the horizontal oscillator is calibrated by using the crystal frequency as a reference the 4.4 MHz crystal must be connected to pin 35 and the 3.5 MHz crystal to pin 34. When only one crystal is connected to the IC the other crystal pin must be connected to the positive supply rail via a 47 kΩ resistor. For applications with two 3.5 MHz crystals both must be connected to pin 34 and the switching between the crystals must be made externally. Switching of the crystals is only allowed directly after the vertical retrace. The circuit will indicate whether a PAL signal has been identified by the colour decoder via the saturation control pin. When two crystals are connected to the IC the output voltage of the video identification circuit indicates the frequency of the incoming chrominance signal. Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors The conditions are: • Signal identified at fosc = 3.6 MHz; VO = 6 V • Signal identified at fosc = 4.4 MHz (or no colour); VO = 8 V. This information can be used to switch the sound bandpass filter and trap filter. TDA8361 This IC contains an automatic PAL/NTSC decoder. The conditions for connecting the reference crystals are the same as for the TDA8360. The decoder can be forced to PAL when the hue control pin is connected to the positive supply voltage via a 5 kΩ or 10 kΩ resistor (approximately). The decoder cannot be forced to the NTSC standard. It is also possible to see if a colour signal is recognized via the saturation pin. TDA8362 In addition to the possibilities of the TDA8361, the TDA8362 can co-operate with the SECAM add-on decoder TDA8395. The communication between the two ICs is achieved via pin 32. The TDA8362 supplies the reference signal (4.43 MHz) for the calibration system of the TDA8395, identification of the colour standard is via the same connection. When a SECAM signal is detected by the TDA8395 the IC will draw a current of 150 µA. When TDA8362 has not identified a colour signal in this condition it will go into the SECAM mode, that means it will switch off the R−Y and B−Y outputs and increase the voltage level on pin 32. March 1994 TDA8360; TDA8361; TDA8362 This voltage will switch off the colour-killer in the TDA8395 and switch on the R−Y and B−Y outputs of the TDA8395. Forcing the system to the SECAM standard can be achieved by loading pin 32 with a current of 150 µA. Then the system manager in the TDA8362 will not search for PAL or NTSC signals. Forcing to NTSC is not possible. For PAL/SECAM applications the input signal for the TDA8395 can be obtained from pin 27 (hue control) when this pin is connected to the positive supply rail via the 5 kΩ or 10 kΩ resistor. An external source selector is required by the TDA8395/TDA8362 combination for PAL/SECAM/NTSC applications. RGB output circuit The colour difference signals are matrixed with the luminance signal to obtain the RGB signals. Linear amplifiers have been chosen for the RGB inputs so that the circuit is suitable for incoming signals from the SCART connector. The contrast and brightness controls operate on internal and external signals. The fast blanking pin has a second detection level at 3.5 V. When this level is exceeded the RGB outputs are blanked so that “On-Screen-Display” signals can be applied to the outputs. The output signal has an amplitude of approximately 4 V, black-to-white, with nominal input signals and nominal control settings. The nominal black level is 1.3 V. 10 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL PARAMETER MIN. MAX. UNIT VP supply voltage − 9.0 V Tstg storage temperature −25 +150 °C Tamb operating ambient temperature −25 +70 °C Tsol soldering temperature for 5 s − 260 °C Tj maximum junction temperature (operating) − 150 °C THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER THERMAL RESISTANCE from junction to ambient in free air 40 K/W CHARACTERISTICS VP = 8 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VP supply voltage (pin 10) 7.2 8.0 8.8 V IP supply current (pin 10) − 80 − mA IHOSC horizontal oscillator start current (pin 36) note 1 6.5 − − mA Ptot total power dissipation including start supply − 0.7 − W IF circuit VISION IF AMPLIFIER INPUTS (PINS 45 AND 46) Vi(rms) input sensitivity (RMS value) note 2 fi = 38.90 MHz − 70 100 µV fi = 45.75 MHz − 70 100 µV fi = 58.75 MHz − 70 100 µV RI Input resistance (differential) note 3 − 2 − kΩ CI Input capacitance (differential) note 3 − 3 − pF Gcr gain control range 64 − − dB Vi(rms) maximum input signal (RMS value) 100 − − mV March 1994 11 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL PARAMETER TDA8360; TDA8361; TDA8362 CONDITIONS MIN. TYP. MAX. UNIT VIDEO AMPLIFIER OUTPUT; NOTE 4 (PIN 7) V7 negative modulation zero signal output level note 5 top sync level V7 4.45 4.6 4.75 V 1.9 2 2.1 V 1.85 2 2.15 V 4.2 4.3 4.4 V positive modulation (TDA8362) zero signal output level note 5 white level ∆V7 difference in amplitude between negative and positive modulation − 0 15 % V7 detection level of black level for positive modulation when no peak white is available in the signal − 3.1 − V ZO video output impedance − − 50 Ω Ibias internal bias current of NPN emitter follower output transistor 1 − − mA Isource maximum source current − − 5 mA B bandwidth of demodulated output signal −3 dB 6 9 − MHz Gdiff gain differential note 6 − 2 5 % Φdiff phase differential notes 6 and 7 − 1 5 deg NLvid video non linearity note 8 − − 5 % Vth white spot threshold voltage level − 4.8 − V Vins white spot insertion voltage level − 3.2 − V Nclamp noise inverter clamping voltage level − 1.4 − V Nins noise inverter insertion level note 9 − 2.6 − V δmod intermodulation notes 7 and 10 S/N blue Vo = 0.92 or 1.1 MHz 60 66 − dB yellow Vo = 0.92 or 1.1 MHz 56 62 − dB blue Vo = 2.66 or 3.3 MHz 60 66 − dB yellow Vo = 2.66 or 3.3 MHz 60 66 − dB signal-to-noise ratio notes 7 and 11 Vi = 10 mV 52 60 − dB end of control range 52 61 − dB V7 residual carrier signal note 7 − 1 − mV V7 residual 2nd harmonic of carrier signal note 7 − 0.5 − mV March 1994 12 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL PARAMETER TDA8360; TDA8361; TDA8362 CONDITIONS MIN. TYP. MAX. UNIT IF AND TUNER AGC; NOTE 12 Timing of IF-AGC (C48 = 2.2 µF) − − 10 % − 2 − ms − 25 − ms − 100 − ms for negative modulation − − 10 µA for positive modulation − − 200 nA modulated video interference tinc response time for an IF input signal amplitude increase of 52 dB for positive and negative modulation tdec response time for an IF input signal amplitude decrease of 52 dB 30% AM for 1 to 100 mV; 0 to 200 Hz for negative modulation for positive modulation (TDA8362) Ileak allowed leakage current of the AGC capacitor note 13 Tuner take-over adjustment (pin 49) V49(rms) minimum starting level voltage for tuner take-over (RMS value) − 0.2 0.5 mV V49(rms) maximum starting level voltage for tuner take-over (RMS value) 100 150 − mV Vcr control voltage range 0.5 − 4.5 V Tuner control output (pin 47) V47 maximum tuner AGC output voltage maximum gain − − VP + 1 V V47(sat) output saturation voltage minimum gain; I47 = 2 mA − − 300 mV I47 maximum tuner AGC output swing 5 − − mA Ileak leakage current RF AGC − − 1 µA ∆V47 input signal variation for complete tuner control 1 2 4 dB − 6 − V − 33 − mV/kHz − − 50 kHz IO(max) = 1 mA AFC OUTPUT; NOTE 14 (PIN 44) V44 output voltage swing fsl AFC slope fos AFC offset VO output voltage at centre frequency − 3.5 − V ZO output impedance − 50 − kΩ note 7 SWITCHING TO POSITIVE MODULATION (TDA8362); NOTE 15 (PIN 1) V1 minimum voltage on pin 1 to switch the video demodulator and AGC to positive modulation − − VP − 1 V II input current − − 1 mA March 1994 13 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL PARAMETER TDA8360; TDA8361; TDA8362 CONDITIONS MIN. TYP. MAX. UNIT VIDEO IDENTIFICATION OUTPUT (PIN 4) VO output voltage ZO output impedance VO output voltage − − 0.5 V − 25 − kΩ − 6 − V − video identified; colour signal available/unavailable ;fosc = 4.4 MHz 8 − V video not identified video identified; colour signal available; fosc = 3.5 MHz td delay time of identification after the AGC has stabilized on a new transmitter − − 10 ms I4 maximum load current at pin 4 − − 25 µA − 1 2 mV 4.2 − 6.8 MHz Sound circuit DEMODULATOR INPUT; NOTE 16 (PIN 5) V5(rms) input limiting for PLL catching range (RMS value) ∆f catching range PLL note 17 RI DC input resistance note 3 100 − − kΩ CI input capacitance note 3 − 15 − pF AMR AM rejection VI = 50 mV RMS; note 18 60 66 − dB note 17 − 350 − mV DE-EMPHASIS (PIN 1) VO(rms) output signal amplitude (RMS value) RO output resistance − 15 − kΩ V1 DC output voltage − 3 − V 500 700 900 mV AUDIO ATTENUATOR OUTPUT (PIN 50) −6 dB; note 17 V50(rms) controlled output signal amplitude (RMS value) RO output resistance − 250 − Ω V50 DC output voltage − 3.3 − V THD total harmonic distortion note 19 − − 0.5 % S/Nint internal signal-to-noise ratio note 7 − 60 − dB S/Next external signal-to-noise ratio note 7 − 80 − dB VOLcr control range see also Fig.5 − 80 − dB OSS suppression of output signal when mute is active − 80 − dB ∆V50 DC shift of the output when mute is active − 10 50 mV March 1994 note 20 14 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL PARAMETER TDA8360; TDA8361; TDA8362 CONDITIONS MIN. TYP. MAX. UNIT EXTERNAL AUDIO INPUT (TDA8361, TDA8362); NOTE 21 (PIN 6) V6(rms) input signal amplitude (RMS value) − 350 700 mV RI input resistance − 25 − kΩ ∆GV voltage gain difference between input maximum volume and output − 12 − dB αcr crosstalk between internal and external audio signals 60 − − dB − 2 2.8 V − 4 − µA − 1 1.4 V − 4 − µA 50 − − dB − 0.3 − V CVBS/On-Screen Display and CD inputs INTERNAL AND EXTERNAL CVBS INPUTS (PINS 13 AND 15) V13(p-p) internal CVBS input voltage (peak-to-peak value) I13 internal CVBS input current V15(p-p) external CVBS input voltage; TDA8361, TDA8362 (peak-to-peak value) I15 external CVBS input current; TDA8361, TDA8362 ISS suppression of non-selected CVBS input signal; TDA8361, TDA8362 notes 3 and 22 note 3 note 23 COMBINED CHROMINANCE AND SWITCH INPUT (TDA8361, TDA8362; PIN 16) V16(p-p) chrominance input voltage (peak-to-peak value) V16(p-p) input signal amplitude before clipping note 7 occurs (peak-to-peak value) 1 − − V RI chrominance input resistance − 15 − kΩ CI chrominance input capacitance − − 5 pF V16 DC input voltage to switch the A/V switch to internal mode − − 0.5 V V16 DC input voltage to switch the A/V switch to external mode VP − 0.5 − − V V16 DC input voltage for chrominance insertion 3 4 5 V SSCVBS suppression of non-selected notes 7 and 23 chrominance signal from CVBS input 50 − − dB March 1994 notes 3 and 24 note 3 15 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL TDA8360; TDA8361; TDA8362 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT RGB INPUTS FOR ON-SCREEN DISPLAY (PINS 22, 23 AND 24) − 0.7 0.8 V input signal amplitude before clipping occurs (peak-to-peak value) 1 − − V Vdiff difference of black level of internal and external signals at the outputs − − 100 mV I22,23,24 input currents − 0.1 − µA V22,23,24(p-p) input signal amplitude for an output signal of 4V (black-to-white) (peak-to-peak value) V22,23,24(p-p) note 25 FAST BLANKING (PIN 21) VI fast blanking input voltage no data insertion − − 0.4 V VI fast blanking input voltage data insertion 0.9 − − V V21(max) maximum input pulse data insertion − − 3 V td delay of data insertion − − 20 ns I21 input current − 0.2 − mA SSint suppression of internal RGB signals with data insertion at f = 0 to 5 MHz note 23 46 − − dB SSext suppression of external RGB signals with data insertion at f = 0 to 5 MHz note 23 46 − − dB VI input voltage to blank the RGB outputs to facilitate ‘On-Screen-Display’ signals being applied to these outputs note 26 4 − − V td delay between the input pulse and the blanking at the output note 7 − 30 − ns COLOUR DIFFERENCE INPUT SIGNALS (PINS 28 AND 29) V29(p-p) input signal amplitude (R−Y) (peak-to-peak value) − 1.05 − V V28(p-p) input signal amplitude (B−Y) (peak-to-peak value) − 1.35 − V I28,29 input current for both inputs − 0.1 1.0 µA − fSC − MHz Chrominance filters CHROMINANCE TRAP CIRCUIT ftrap trap frequency QF trap quality factor SR colour subcarrier rejection notes 7 and 27 − 2 − 20 − − dB − fSC − MHz − 3 − CHROMINANCE BANDPASS CIRCUIT fc centre frequency QBP bandpass quality factor March 1994 note 7 16 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL TDA8360; TDA8361; TDA8362 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Delay line and peaking circuit Y DELAY LINE td delay time note 7 − 480 − ns B bandwidth of internal delay line note 7 8 − − MHz at 50% of pulse; note 7 − 160 − ns PEAKING CONTROL; NOTE 28, SEE ALSO FIG.6 (PIN 14) tW width of preshoot or overshoot Scth peaking signal compression threshold − 50 − IRE I14 input current when no video input signal present − 1 − mA VI voltage level to switch off peaking − 7 − V Horizontal and vertical synchronization circuits SYNC VIDEO INPUT (TDA8361, TDA8362; PINS 13 AND 15) V13 sync pulse amplitude referenced to pin 15; note 3 50 300 − mV SL slicing level note 29 − 50 − % width of the vertical sync pulse without sync instability note 30 22 − − µs note 44 − 15625 − Hz − − ±2 % − 0.2 0.5 % VERTICAL SYNC tW HORIZONTAL OSCILLATOR ffr free running frequency ∆ffr spread on free running frequency ∆fosc/∆VP frequency variation with respect to the supply voltage VP = 8 V ±10%; note 7 ∆fosc/∆T frequency variation with temperature Tamb = 25 °C ±50 °C; − note 7 1 − Hz/K ∆fosc( max) maximum frequency deviation at the start of the horizontal output − − 75 % − ±0.9 ±1.2 kHz ±0.6 ±0.9 − kHz FIRST CONTROL LOOP; NOTE 31 (FILTER CONNECTED TO PIN 40) fHR holding range PLL fCR catching range PLL S/N signal-to-noise ratio of the video input signal at which the time constant is switched − 20 − dB HYS hysteresis at the switching point − 3 − dB March 1994 note 7 17 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL PARAMETER TDA8360; TDA8361; TDA8362 CONDITIONS MIN. TYP. MAX. UNIT SECOND CONTROL LOOP; NOTE 32 (CAPACITOR CONNECTED TO PIN 39) ∆ϕi/∆ϕo control sensitivity tcr control range from start of horizontal output to flyback tshift maximum horizontal shift range ∆ϕi/∆ϕo shift control sensitivity V39 voltage to switch on the X-ray protection II input current during protection − 150 − µs/µs 11 12 − µs note 7 ±2 − − µs note 7 − 3 − µA/µs 6 − − V − − tbf µA − − 0.3 V without RL on pin 39 HORIZONTAL OUTPUT (PIN 37) VOL LOW level output voltage IO = 10 mA IO(max) maximum allowed output current 10 − − mA VO(max) maximum allowed output voltage − − VP V δdf duty factor note 7 − 50 − % note 7 100 − 300 µA FLYBACK INPUT/SANDCASTLE OUTPUT (PIN 38) I38 required input current during flyback pulse VO output voltage during burst key 4.8 5.3 5.8 V VO output voltage during blanking 1.8 2.0 2.2 V VIcl clamped input voltage during flyback 2.6 3.0 3.4 V tW burst key pulse width 3.3 3.5 3.7 µs tW vertical blanking pulse width − 14 − lines td delay of start of burst key to start of sync 5.2 5.4 5.6 µs note 33 VERTICAL SECTION; NOTE 34 ffr free running frequency − 50/60 − Hz flock locking range 45 − 64.5 Hz divider value not locked − 625/525 − locking range (lines/frame) 488 − 722 − − 2 µA − 0.3 − mA − 1.5 1.8 V − − 1.6 µs VERTICAL RAMP GENERATOR (PIN 42) I42 input current during scan Idis discharge current during retrace Vsaw(p-p) sawtooth amplitude (peak-to-peak value) td delay from field-to-field March 1994 note 7 in 50 Hz mode 18 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL PARAMETER TDA8360; TDA8361; TDA8362 CONDITIONS MIN. TYP. MAX. UNIT VERTICAL OUTPUT (PIN 43) IO available output current 1 − − mA Iint internal bias current of NPN emitter follower − 0.2 − mA VO(max) maximum available output voltage 4 − − V VO(min) minimum available output voltage − − 0.3 V note 7 VERTICAL FEEDBACK INPUT (PIN 41) V41 DC input voltage 2.0 2.5 3.0 V V41 AC input voltage − 1 − V I41 input current − − 15 µA ∆tp internal pre-correction to sawtooth note 35 − 3 − % ∆T/∆V temperature dependency on amplitude ∆T = 40 °C − − 1 % VGL vertical guard switching level with respect to the DC feedback level; switching level LOW − − −1.5 V VGH vertical guard switching level with respect to the DC feedback level; switching level HIGH − − +1.5 V td delay of scan start power on at 60 Hz − 140 − ms note 36 26 − − dB Colour demodulation part CHROMINANCE AMPLIFIER ACCcr ACC control range ∆V change in amplitude of the output signals over the ACC range − − 2 dB THRon threshold colour killer ON −30 − −38 dB HYSoff hysteresis colour killer OFF − +3 − dB − +1 − dB 2.3 − 2.7 strong input signal note 7 S/N ≥ 40 dB noisy input signal ACL CIRCUIT chrominance burst ratio at which the ACL starts to operate REFERENCE PART Phase-locked loop; note 37 fCR catching range 300 − − Hz ∆ϕ phase shift for a ±200 Hz deviation of note 7 the oscillator frequency − − 2 deg March 1994 19 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL PARAMETER TDA8360; TDA8361; TDA8362 CONDITIONS MIN. TYP. MAX. UNIT Oscillator TCosc temperature coefficient of fosc note 7 − 2.0 2.5 Hz/K ∆fosc fosc deviation with respect to VP note 7; VP = 8 V ±10% − − 250 Hz RI input resistance (pin 34) fi = 3.58 MHz; note 4 − 1.5 − kΩ RI input resistance (pin 35) fi = 4.43 MHz; note 4 − 1 − kΩ CI input capacitance (pins 34 and 35) note 4 − − 10 pF R required resistance to VP to force the oscillator into one crystal mode − 47 − kΩ ±60 − deg HUE CONTROL AND CHROMINANCE OUTPUT (TDA8361, TDA8362); NOTE 38 (PIN 27) HUEcr hue control range see also Fig.7 ±45 ∆HUE hue variation for ±10% VP note 7 − 0 5 deg ∆HUE/∆T hue variation with temperature Tamb = 0 to +7 °C; note 7 − 0 − deg R value of resistor connected to VP to switch the PAL decoder and to obtain a chrominance input signal for the TDA8395 (TDA8362) 4.7 10 12 kΩ VO(p-p) chrominance output signal to the TDA8395 (peak-to-peak value) 330 − mV nominal output signal − DEMODULATORS V30(p-p) (R−Y) output signal amplitude (peak-to-peak value) note 39 − 0.525 − V V31(p-p) (B−Y) output signal amplitude (peak-to-peak value) note 39 − 0.675 − V G gain ratio of both demodulators G(B−Y)/G(R−Y) 1.6 1.78 1.96 −1 − +1 dB − 250 − Ω − 650 − kHz (R−Y) output − − 10 mV (B−Y) output − − 10 mV (R−Y) output − − 10 mV (B−Y) output − − 10 mV spread of signal amplitude ratio PAL/NTSC note 7 ZO output impedance (R−Y)/(B−Y) output B bandwidth of demodulators −3 dB; note 40 V30,31(p-p) residual carrier output voltage (peak-to-peak value) f = fosc V30,31(p-p) March 1994 residual carrier output voltage (peak-to-peak value) f = 2fosc 20 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL PARAMETER TDA8360; TDA8361; TDA8362 CONDITIONS MIN. TYP. MAX. UNIT DEMODULATORS V30(p-p) H/2 ripple at (R−Y) output (peak-to-peak value) only burst fed to input − − 25 mV ∆VO/∆T change of output signal amplitude with temperature note 7 − 0.1 − %/K ∆VO/∆VP change of output signal amplitude with supply voltage note 7 − − ±0.1 dB ϕe phase error in the demodulated signals − − 5 deg − −0.51 ±10% − − −0.19 ±25% − COLOUR DIFFERENCE MATRIXES IN CONTROL CIRCUIT G−Y/−(R−Y) PAL/SECAM mode with TDA8362/TDA8395 −(R−Y) and −(B−Y) not affected G−Y/−(B−Y) −(B−Y) NTSC mode; the CD matrix results in nominal hue setting the following signal (1.14/−10°) −1.12UR − 1.12VR −(R−Y) NTSC mode; the CD matrix results in nominal hue setting the following signal (1.14/100°) −0.20UR + 1.12VR G−Y NTSC mode; the CD matrix results in the following signal (0.30/235°) −0.25VR − 0.17UR nominal hue setting REFERENCE SIGNAL OUTPUT FOR TDA8395 (TDA8362; PIN 32) fref reference frequency V32(p-p) output signal amplitude (peak-to-peak value) note 41 − 4.43 − MHz 0.2 0.25 0.3 V VO output voltage level PAL/NTSC identified − 1.5 − V VO output voltage level no PAL/NTSC; SECAM (by TDA8395) identified − 5 − V I32 required current to force TDA8362/TDA8395 combination in SECAM mode 150 − − µA Control part SATURATION CONTROL; NOTE 25 (PIN 26) SATcr saturation control range see also Fig.8 52 − − dB ∆SAT/∆V saturation level change VP = ±10%;note 7 − 0 − % II input current no colour identified − 1 − mA Vctr control voltage to switch colour PLL in the free-running mode note 37 VP − 1 − − V March 1994 21 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL PARAMETER TDA8360; TDA8361; TDA8362 CONDITIONS MIN. TYP. MAX. UNIT CONTRAST CONTROL; NOTE 25 (PIN 25) CONcr contrast control range − 20 − dB − − 0.7 dB see also Fig.10 − ±1 − V see also Fig.9 tracking between the three channels over a control range of 10 dB BRIGHTNESS CONTROL (PIN 17) BRIcr brightness control range RGB AMPLIFIERS (PINS 18, 19 AND 20) V18,19,20(p-p) output signal amplitudes (peak-to-peak value) nominal luminance input signal and nominal contrast; note 25 3.5 4.0 4.5 V V20(p-p) output signal amplitudes for the RED channel (peak-to-peak value) nominal settings for contrast and saturation control and no luminance signal to the R−Y signal (PAL) 3.8 4.2 4.6 V V18,19,20 blanking level at the RGB outputs 0.5 0.6 0.8 V V18,19,20 black level at the RGB outputs note 25 1.2 1.3 1.4 V Vpwl maximum peak white level note 42 − 6 − V IO available output current 5 − − mA ZO output impedance − 150 − Ω Isource current source of output stage 1.8 2.0 − mA relative spread between the RGB output signals − − 5 % − 60 − dB S/N signal-to-noise ratio of output signals note 43 for RGB input note 7 50 56 − dB note 23 − − 25 mV − − 25 mV nominal brightness − − 100 mV black level shift with picture content note 7 − 0 − mV variation of black level with temperature note 7 −2 − 0 mV/K for CVBS input fres(p-p) residual frequency at fosc in the RGB outputs (peak-to-peak value) fres(p-p) residual frequency at 2fosc plus higher harmonics in the RGB outputs (peak-to-peak value) Vdiff difference in black level between the three outputs Vbl ∆bl/∆T March 1994 note 7 22 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors SYMBOL PARAMETER TDA8360; TDA8361; TDA8362 CONDITIONS MIN. TYP. MAX. UNIT RGB AMPLIFIERS (PINS 18, 19 AND 20) ∆bl/∆CON variation of black level over contrast range nominal saturation; note 7 − − 100 mV ∆bl/∆SAT variation of black level over saturation range nominal contrast; note 7 − − 50 mV ∆bl relative variation in black level between the three channels during variations of supply voltage (±10%) nominal saturation − − 50 mV saturation (50 dB) nominal contrast − − 25 mV contrast (20 dB) nominal saturation − − 60 mV brightness (±0.5 V) nominal controls − − 100 mV − − 10 mV 8 − − MHz Vdiff differential drift of black level over a temperature range of 40 °C note 7 B bandwidth of output signals for −3 dB RGB input CVBS input fosc = 3.58 MHz − 2.8 − MHz CVBS input fosc = 4.43 MHz − 3.5 − MHz 8 − − MHz S-VHS input Notes to the “Characteristics” 1. It is possible to start the horizontal oscillator when a current of 5.5 mA is supplied to this pin. In this condition the main part of the IC is not active and this results in the frequency of the oscillator not being controlled at the correct value. Consequently, the oscillator frequency will be higher than normal, the maximum deviation will be 75%. When the start-up function is used the maximum voltage on pin 36 must be limited to 8.8 volts. 2. On set AGC. 3. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 4. Measured at 10 mV RMS top sync input signal. 5. So called projected zero point, i.e. with switched demodulator. 6. Measured in accordance with the test line given in Fig.11. For the differential phase test the peak white setting is reduced to 87%. The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. The phase difference is defined as the difference in degrees between the largest and smallest phase angle. 7. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 8. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.12. 9. Insertion (suppression of the interference pulses) to a level of 2.6 V is active only during a strong input signal. This is because the noise inverter has a negative effect on the sound performance at a weak input signal. 10. The test set-up and input conditions are given in Fig.13. The figures are measured with an input signal of 10 mV RMS. March 1994 23 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 11. Measured with a source impedance of 75 Ω, where: V O (black-to-white) S/N = 20 log --------------------------------------------------------V m ( rms ) ( B = 5 MHz ) 12. To obtain a good noise immunity of the AGC circuit the AGC detector is gated during the sync pulse. This gating is switched off during the vertical retrace to avoid disturbances of the signal amplitude due to phase errors of the incoming video signal which are caused by the head-switching of VCRs. 13. When the leakage current of the capacitor exceeds this value it will result in a reduced performance of the AGC (amplitude variation during line or frame) but it will not result in a hang-up situation. 14. The AFC slope is directly related to the Q-factor of the demodulator tuned circuit. The given AFC steepness is obtained with a Q-factor of 60. When a lower steepness is required this can be obtained by connecting an external resistor to the AFC output (the output impedance is 50 kΩ). The AFC off-set is tested with a double sideband input signal and with the reference tuned circuit tuned to minimum AGC voltage (optimum tuning for the demodulator). 15. For positive modulated signals the FM sound demodulator for the sound is not required. This is because the sound signal is amplitude modulated. Therefore the TDA8362 can be switched to positive modulation via the de-emphasis pin (pin 1). When switched to positive modulation the audio switch is set to ‘external’ so that the demodulated audio signal can be supplied to the input. The option between AM sound and SCART audio signals is achieved by means of an external switch. 16. The sound IF input is combined with the AF volume control. The IF signal is internally AC coupled to the limiter amplifier. The volume control voltage must be supplied to this pin via a resistor. 17. VI = 100 mV RMS; FM: 1 kHz, ∆f = ±50 kHz. 18. VI = 50 mV RMS, f = 4.5/5.5 MHz; FM: 70 Hz ±50 kHz deviation AM: 1 kHz at 30% modulation. 19. VI = 100 mV RMS, 5.5 MHz; FM: 1 kHz, ±17.5 kHz deviation; 15 kHz bandwidth; audio attenuator at −6 dB. 20. Audio attenuator at −20 dB; temperature range 10 to 50 °C. 21. In the TDA8361 and TDA8362 the audio and CVBS switches are controlled via the chrominance input pin. Table 1 lists the various possibilities. When the DC voltage has a value between 3 and 5 V the switches are set to the S-VHS position. The chrominance trap is then switched off and separate Y and chrominance signals have to be applied to the inputs (the audio switch is set to external in this condition). The audio switch is also set to external when the IF amplifier is switched to positive modulation (see also note 15). 22. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 23. This parameter is measured at nominal settings of the various control voltages. 24. Burst amplitude; for a colour bar with 75% saturation the chrominance signal amplitude is 660 mV (p-p). 25. Nominal contrast is specified as maximum contrast −3 dB. Nominal saturation as maximum −12 dB. The nominal brightness control voltage is 2.5 V. 26. When the data blanking input pulse exceeds a level of 4 V the RGB outputs are blanked. In this condition it is possible to supply ‘On-Screen-Display’ signals to the outputs. This blanking overrules both the internal and external RGB signals. 27. The −3 dB bandwidth of the circuit can be calculated by means of the following equation: 1 f –3 dB = f osc 1 – -------- 2Q March 1994 24 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 28. The amplitude response curve can be expressed as follows: A(f) = 1 + K1 − cos (180 x f/3.1 MHz) and is realised with a transversal peaking filter having delay sections of 160 ns each. In the ‘neutral’ setting K = 0 and in the minimum setting K = −0.5. The peaking signal amplifier is linear for 250 ns step input signals up to 50 IRE units. For higher amplitudes the marginal gain is reduced. When the horizontal PLL is not synchronized (no signal present at the video input) the peaking control voltage is pulled down by means of an internal current. This information can be used to detect whether an input signal is available. 29. Slicing level independent of sync pulse amplitude. 30. The horizontal and vertical sync are stable while processing Copy Guard signals and signals with phase shifted sync pulses (stretched tapes). Trick mode conditions of the VCR will also not disturb the synchronization. The value given is the delay caused by the vertical sync pulse integrator. The integrator has been designed such that the vertical sync is not disturbed for special anti-copy tapes with vertical sync pulses with an on/off time of 10/22 µs. 31. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition. Therefore the circuit contains a noise detector and the time constant is switched to ‘slow’ when excessive noise is present in the signal (only when the internal video signal is selected, when the video switch is in the external mode the time constant is always ‘fast’). In the ‘fast’ mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. When no video signal is received the time constant of the first loop is switched to ‘very slow’. This ensures a stable OSD when the receiver is switched to a channel without transmitter. The output current of the phase detector for the various conditions is shown in Table 2. 32. Picture shift can be obtained by means of a variable external load on the second phase detector. The control range is ±2 µs; the required current for this phase shift is ±6 µA. 33. The vertical blanking pulse in the RGB outputs has a width of 22 or 17.5 lines (50 or 60 Hz system). The width of the vertical sync pulse in the sandcastle pulse is 14 lines. This is to prevent a phase distortion on top of the picture due to a timing modulation of the incoming flyback pulse. 34. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This divider circuit has 2 search modes of operation: The ‘large window’ mode is switched on when the circuit is not synchronized or, when a non-standard signal is received (the number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz) The ‘narrow window’ mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. 35. This precorrection is intended to compensate for non-linearity of AC coupled vertical output stages. The value given indicates the amplitude of the correction waveform with respect to the sawtooth amplitude. 36. At a chrominance input voltage (related to CVBS2) of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)) the dynamic range of the ACC is +6 and −20 dB. March 1994 25 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 37. All frequency variations are referenced to 3.58/4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520. If the spurious response of the 4.43 MHz crystal is lower than −3 dB with respect to the fundamental frequency for a damping resistance of 1 kΩ, oscillation at the fundamental frequency is guaranteed. The spurious response of the 3.58 MHz crystal must be lower than −3 dB with respect to the fundamental frequency for a damping resistance of 1.5 kΩ. The catching and detuning range are measured for nominal crystal parameters. These are: a) load resonance frequency f0 (CL = 20 pF) = 4.433619 or 3.579545 MHz b) motional capacitance CM = 20.6 fF (4.43 MHz crystal) or (3.58 MHz crystal) c) parallel capacitance C0 = 5.5 pF (4.43 MHz crystal) or 4.5 pF (3.58 MHz crystal). The actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off chip. The free-running frequency of the oscillator can be checked by pulling the saturation control pin to the positive supply rail. In that condition the colour killer is not active so that the frequency off-set is visible on the screen. When two crystals are connected to the IC the circuit must be forced to one of the crystals during this test to prevent the oscillator continuously switching between the two frequencies. 38. In the TDA8362 the hue control pin has a double function. When the control voltage has a value of 0 to 5 V (normal control range) the hue can be controlled when NTSC signals are decoded. When this voltage is increased to a value greater than 5.5 V the decoder is forced to the PAL standard. When this pin is connected to the positive supply line via a 10 kΩ resistor the selected CVBS signal, of the CVBS switch, is available. This signal can be applied to the SECAM decoder TDA8395. The phase shift of the hue control can be measured at the colour difference outputs (pins 30 and 31). 39. The −(R−Y) and −(B−Y) signals are demodulated with the 90° phase difference of the reference carrier and a gain ratio −(B−Y)/−(R−Y) = 1.78. The matrixing to the required signals is achieved in the control part. 40. This value indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter. The bandwidth of the demodulator low-pass filter is approximately 1 MHz. 41. The reference signal for the TDA8395 is available only when the crystal oscillator is operating at a frequency of 4.43 MHz. When a SECAM signal is identified this signal is only available during the vertical retrace period thus avoiding crosstalk with the incoming SECAM signal during scan. 42. When one of the three output signals exceeds this level the gain of the amplifiers is reduced. This is achieved by a reduction of contrast and thus avoids clipping of the output signals. The discharge current at pin 25 is 0.2 mA. When the black level exceeds a value of 2 V the maximum peak-to-peak value of the video output signal will be less than 4 V (p-p); this is due to the operation of the peak-white limiter. 43. The signal-to-noise ratio is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz). During the measurement the peaking control voltage is set to nominal. 44. The typical free running frequency is dependent on the crystal which is used for calibration. With 4.4 MHz the typical free running frequency is 15625, with 3.58 MHz the typical free running frequency is 15734. Calibration during start-up is always carried out with a 4.4 MHz crystal if no forced mode is used. March 1994 26 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 Table 1 Audio and CVBS switch selection. LEVEL (pin 16) INTERNAL CVBS EXTERNAL CVBS/Y CHROMINANCE CHROMINANCE TRAP DC ≤ 0.5 V ON OFF OFF ON internal 3 ≤ DC ≤ 5 V OFF ON (Y) ON OFF external DC ≥ 7.5 V OFF ON (CVBS) OFF ON external AUDIO Table 2 Output current of phase detector. CURRENT Φ1 DURING SCAN (µA) VERTICAL RETRACE (µA) GATED YES/NO Weak signal and synchronized 30 30 YES (5.7 µs) Strong signal and synchronized 180 270 NO Not synchronized 180 270 NO 6 6 NO No video identification QUALITY SPECIFICATION Quality level in accordance with UZW B0/FQ-0601. SYMBOL ESD PARAMETER RANGE A protection circuit specification (note 1) Note 1. All pins are protected against ESD by means of internal clamping diodes. March 1994 27 RANGE B UNIT 2000 200 V 100 200 pF 1500 0 Ω Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 MBC207 - 1 MBC208 50 0 (dB) (%) 20 30 40 10 60 10 80 30 100 0 1 2 3 4 (V) 50 5 0 Fig.5 Volume control curve. 1 2 3 4 (V) 5 Fig.6 Peaking control curve. MBC206 - 1 60 (deg) MBC204 300 40 (%) 250 20 200 0 150 20 100 40 60 50 0 1 2 3 4 (V) 0 5 Fig.7 Hue control curve March 1994 0 1 2 3 4 (V) Fig.8 Saturation control curve. 28 5 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 MBC205 100 MBC209 1.0 (%) 80 (V) 60 0 40 20 1.0 0 0 1 2 3 4 (V) 5 0 3 4 5 Fig.10 Brightness control curve. MBC212 100% 92% 30% for negative modulation 100% = 10% rest carrier Fig.11 Video output signal. March 1994 2 (V) Fig.9 Contrast control curve. 16 % 1 29 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors andbook, full pagewidth TDA8360; TDA8361; TDA8362 MBC211 100% 86% 72% 58% 44% 30% 10 12 22 26 32 36 40 44 48 52 60 64 µs 56 Fig.12 Test signal waveform. 3.2 dB handbook, full pagewidth 10 dB 13.2 dB 13.2 dB 30 dB 30 dB SC CC PC SC CC PC MBC213 BLUE YELLOW PC SC Σ ATTENUATOR TEST CIRCUIT SPECTRUM ANALYZER gain setting adjusted for blue CC MBC210 Input signal conditions: SC = sound carrier; CC = colour carrier; PC = picture carrier. All amplitudes with respect to top sync level. V O at 3.58 or 4.4 MHz Value at 0.92 or 1.1 MHz = 20 log ------------------------------------------------------------ + 3.6 dB V O at 0.92 or 1.1 MHz V O at 3.58 or 4.4 MHz Value at 2.66 or 3.3 MHz = 20 log -----------------------------------------------------------V O at 2.66 or 3.3 MHz Fig.13 Test set-up intermodulation. March 1994 30 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 seating plane PACKAGE OUTLINE handbook, full pagewidth 15.80 15.24 47.92 47.02 4.57 5.08 max max 3.2 2.8 0.51 min 1.73 max 0.53 max 1.778 (25x) 0.18 M 0.32 max 15.24 17.15 15.90 1.3 max MSA267 52 27 14.1 13.7 1 26 Dimensions in mm. Fig.14 52-lead shrink dual in-line; plastic (SOT247AG). SOLDERING REPAIRING SOLDERED JOINTS Plastic dual in-line packages Apply the soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 °C, it must not be in contact for more than 10 s; if between 300 and 400 °C, for not more than 5 s. BY DIP OR WAVE The maximum permissible temperature of the solder is 260 °C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. March 1994 31 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. March 1994 32 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 NOTES March 1994 33 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 NOTES March 1994 34 Philips Semiconductors Objective specification Integrated PAL and PAL/NTSC TV processors TDA8360; TDA8361; TDA8362 NOTES March 1994 35 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)829-1166, Fax. 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(0)4806 960 India: PHILIPS ELECTRONICS & ELECTRICALS Ltd., Components Dept., Shivsagar Estate, Block 'A', Dr. Annie Besant Rd., Worli, BOMBAY 400 018, Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: Viale F. Testi, 327, 20162 MILANO, Tel. (02)6752.1, Fax. (02)6752.3350 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, KOKIO 108, Tel. (03)3740 5101, Fax. (03)3740 0570 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)757 5511, Fax. (03)757 4880 Mexico: Philips Components, 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Tel. (040)78 37 49, Fax. (040)78 83 99 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (22)74 8000, Fax. (22)74 8341 Philips Semiconductors Pakistan: Philips Markaz, M.A. Jinnah Rd., KARACHI 3, Tel. (021)577 039, Fax. (021)569 1832 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: Av. Eng. Duarte Pacheco 6, 1009 LISBOA Codex, Tel. (01)683 121, Fax. (01)658 013 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: 195-215 Main Road, Martindale, P.O. Box 7430,JOHANNESBURG 2000, Tel. (011)470-5433, Fax. (011)470-5494 Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. (01)488 2211, Fax. (01)481 7730 Taiwan: 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 10446, Tel. (2)388 7666, Fax. (2)382 4382 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna - Trad Road Km. 3 Prakanong, BANGKOK 10260, Tel. (2)399-3280 to 9, (2)398-2083, Fax. (2)398-2080 Turkey: Talatpasa Cad. No. 5, 80640 LEVENT/ISTANBUL, Tel. (0212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors Limited, P.O. Box 65, Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (071)436 41 44, Fax. (071)323 03 42 United States: INTEGRATED CIRCUITS: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd., P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601 For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BAF-1, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD29 © Philips Electronics N.V. 1994 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 9397 727 10011