PHILIPS TDA9800T

INTEGRATED CIRCUITS
DATA SHEET
TDA9800
VIF-PLL demodulator and FM-PLL
detector
Preliminary specification
File under Integrated Circuits, IC02
July 1994
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
• AGC output voltage for tuner; adjustable take-over point
(TOP)
FEATURES
• Suitable for negative vision modulation
• AFC detector without extra reference circuit
• Applicable for IF frequencies of 38.9 MHz, 45.75 MHz
and 58.75 MHz
• Alignment-free FM-PLL detector with high linearity
• Stabilizer circuit for ripple rejection and to achieve
constant output signals
• Gain controlled wide band VIF amplifier (AC coupled)
• True synchronous demodulation with active carrier
regeneration (ultra-linear demodulation, good
intermodulation figures, reduced harmonics and
excellent pulse response)
• 5 to 8 V positive supply voltage range, low power
consumption (300 mW at +5 V supply voltage).
• Peak sync AGC for negative modulation
GENERAL DESCRIPTION
• Video amplifier to match sound trap and sound filter
The TDA9800 is a monolithic integrated circuit for vision
and sound IF signal processing in TV and VTR sets.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP. MAX.
UNIT
VP
positive supply voltage (pin 20)
4.5
5
8.8
V
IP
supply current
51
60
69
mA
Vi IF
vision IF input signal sensitivity (RMS value, pins 1 and 2)
−
50
90
µV
maximum vision IF input signal (RMS value, pins 1 and 2)
70
150
−
mV
Gv
IF gain control
64
70
73
dB
Vo CVBS
CVBS output signal on pin 7 (peak-to-peak value)
1.7
2.0
2.3
V
B
−3 dB video bandwidth on pin 7
6
8
−
MHz
S/N (W)
signal-to-noise ratio weighted; for video
56
59
−
dB
α0.92/1.1
intermodulation attenuation
56
62
−
dB
56
62
−
dB
αH
suppression of harmonics in video signal
35
40
−
dB
Vo AF
maximum AF output signal for THD < 1.5% (RMS value, pin 9)
0.8
−
−
V
Tamb
operating ambient temperature
−20
−
+70
°C
α2.76/3.3
ORDERING INFORMATION
PACKAGE
EXTENDED TYPE
NUMBER
PINS
PIN POSITION
MATERIAL
CODE
TDA9800
20
DIL
plastic
SOT146(1)
TDA9800T
20
mini-pack
plastic
SOT163A(2)
Note
1. SOT146-1; 1996 December 6.
2. SOT163-1; 1996 December 6.
July 1994
2
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
handbook, full pagewidth
VP = 5 V (9 V)
2fPC
GND 18
IF input
Vi PC
VP
TPLL
VCO2
VCO1
AFC
20
6
17
16
15
INTERNAL
REFERENCE
VOLTAGE
Vi VIF1 1
TRAVELLING
WAVE
DIVIDER
VCO
AF
AMPLIFIER
AFC
9 Vo AF
10 CAF
CAF
3-STAGE
IF-AMPLIFIER
FREQUENCY
DETECTOR
AND PHASE
DETECTOR
Vi VIF2 2
VIDEO
DEMODULATOR
CCS 4
VIDEO
AMPLIFIER
FM-PLL
TDA9800
sound
mute
takeover
point
AGC
DETECTOR
IF
AGC
TUNER
AGC
3
12
19
5
TOP
TAGC
CAGC
MUTE
CAGC
sound
MUTE
tuner AGC
output
BUFFER AND
NOISE
CLIPPING
8
n.c.
7
2 V (p-p)
13
14
11
Vo(vid)
Vi(vid)
Vi IC
SOUND
TRAP
1 V (p-p)
Vo CVBS
SOUND
FILTER
video and
intercarrier
MED329
Fig.1 Block diagram.
July 1994
3
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
PINNING
SYMBOL
Vi IF
PIN
1
DESCRIPTION
vision IF differential input signal
2
TADJ
3
tuner AGC take-over adjust (TOP)
φADJ
4
phase detector adjust
MUTE
5
sound mute switch
TPLL
6
PLL time constant of phase detector
Vo CVBS
7
CVBS (positive) output signal
n.c.
8
not connected
Vo AF
9
audio frequency output signal
CAF
10
decoupling capacitor of audio frequency amplifier
Vi IC
11
sound intercarrier input signal
TAGC
12
tuner AGC output
Vo VID
13
video and sound intercarrier output signal
Vi VID
14
video input signal to buffer amplifier
AFC
15
automatic frequency control output
VCO1
16
VCO reference circuit for 2 fPC
VCO2
17
GND
18
ground (0 V)
CAGC
19
AGC capacitor
VP
20
positive supply voltage
handbook, halfpage
Vi VIF1
1
20 VP
Vi VIF2
2
19 CAGC
TOP
3
18 GND
17 VCO2
CCS 4
MUTE
16 VCO1
5
TPLL 6
TDA9800
15 AFC
Vo CVBS 7
14 Vi(vid)
13 Vo(vid)
n.c. 8
Vo AF 9
12 TAGC
11 Vi IC
CAF 10
MED330
Fig.2 Pin configuration.
July 1994
4
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
with 90 degree phase difference independent of
frequency.
FUNCTIONAL DESCRIPTION
Vision IF input
Video amplifier, buffer and noise clipping
The vision IF amplifier consists of three AC-coupled
differential amplifier stages; each stage comprises a
controlled feedback network by means of emitter
degeneration.
The video amplifier is a wide bandwidth operational
amplifier with internal feedback. A nominal positive
modulated video signal of 1 V (p-p) is present on the
composite video output (pin 13). The input impedance of
the 7 dB wideband buffer amplifier (with internal feedback)
is suitable for ceramic sound trap filters. The CVBS output
(pin 7) provides a positive video signal of 2 V (p-p). Noise
clipping is provided internally.
IF and tuner AGC
The automatic control voltage to maintain the video output
signal at a constant level is generated according to the
transmission standard. Since the TDA9800 is suitable for
negative modulation only the peak-sync level is detected.
The AGC detector charges and discharges the capacitor
on pin 19 to set the IF gain and the tuner gain. The AGC
capacitor voltage is transferred to an internal IF control
signal, and is fed to the tuner AGC to generate the tuner
AGC output current on pin 12 (open-collector output). The
tuner AGC voltage take over point is adjusted on pin 3.
This allows the tuner and the IF SAW filter to be matched
to achieve the optimum IF input level.
Sound demodulation
The FM sound intercarrier signal is fed to pin 11 and
through a limiter amplifier before it is demodulated. This
achieves high sensitivity and high AM suppression. The
limiter amplifier consists of seven internal AC-coupled
stages, minimizing the DC offset.
The FM-PLL demodulator consists of an RC-oscillator,
loop filter and phase detector. The oscillator frequency is
locked on the FM intercarrier signal from the limiter
amplifier. As a result of this locking, the RC-oscillator is
frequency-modulated.
The modulating signal voltage (AF signal) is used to
control the oscillator frequency. By this, the FM-PLL
operates as an FM demodulator.
The audio frequency amplifier with internal feedback is
designed for high gain and high common mode rejection.
The low-level AF signal output from the FM-PLL
demodulator is amplified and buffered in a low-ohmic
audio signal output stage (pin 9). An external decoupling
capacitor on pin 10 removes the DC voltage from the audio
amplifier input.
By using the sound mute switch (pin 5) the AF amplifier is
set to mute state.
Frequency detector, phase detector and video
demodulator
The IF amplifier output signal is fed to a frequency detector
and to a phase detector. During acquisition the frequency
detector produces a DC current which is proportional to the
frequency difference between the input and the VCO
signal. After frequency lock-in the phase detector
produces a DC current proportional to the phase
difference between the VCO and the input signal. Via the
loop filter the DC current of either frequency detector or
phase detector is converted into a DC voltage, which
controls the VCO frequency.
The video demodulator is a linear multiplier, designed for
low distortion and wide bandwidth. The vision IF input
signal is multiplied by the in-phase component of the VCO
output. The demodulated output signal is fed via an
integrated low-pass filter (fg = 12 MHz) to the video
amplifier for suppression of the carrier harmonics.
VCO and travelling wave divider
The VCO operates with a symmetrically-connected
reference LC-circuit, operating at double vision carrier
frequency. Frequency control is performed by an internal
varicap diode. The voltage to set the VCO frequency to the
actual frequency of double vision carrier frequency, is also
amplified and converted for the AFC output current.
The VCO signal is divided-by-two in a travelling wave
divider, which generates two differential output signals
July 1994
TDA9800
5
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
supply voltage (pin 20) for a maximum chip temperature (note 1)
VP
SOT146 at +120 °C
0
8.8
V
SOT163A at +100 °C
0
5.5
V
VI
voltage on pins 1, 2, 7, 11, 13, 14, 15 and 19
0
VP
V
ts max
short-circuit time
−
10
s
V12
tuner AGC output voltage
−
13.2
V
Tstg
storage temperature range
−25
+150
°C
VESD
electrostatic handling for all pins (note 2)
−
±300
V
Notes
1. Supply current IP = 69 mA at Tamb = +70 °C.
2. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor (negative and positive voltage).
THERMAL RESISTANCE
SYMBOL
Rth j-a
July 1994
PARAMETER
THERMAL RESISTANCE
from junction to ambient in free air
SOT146
73 K/W
SOT163A
85 K/W
6
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
CHARACTERISTICS
The following characteristics apply for VP = 5 V; Tamb = +25 °C; see Table 1 for input frequencies and picture to sound
ratios; VilF = 10 mV RMS value (sync level); video modulation DSB; residual carrier: 10%; video signal in accordance
with CCIR line 17 or NTC-7 Composite; measurements taken in Fig.3 unless otherwise specified
SYMBOL
PARAMETER
VP
supply voltage (pin 20)
IP
supply current
CONDITIONS
note 1
MIN.
TYP.
MAX.
UNIT
4.5
5
8.8
V
51
60
69
mA
−
50
90
µV
input sensitivity (RMS value) at
58.75 MHz
−
60
100
µV
maximum input signal (RMS value) at +1 dB video at output
38.9 MHz and 45.75 MHz
70
150
−
mV
maximum input signal (RMS value) at
58.75 MHz
80
160
−
mV
−
0.7
1
dB
38.9 MHz and
45.75 MHz
64
70
−
dB
58.75 MHz
62
Vision IF input (pins 1 and 2)
Vi
input sensitivity (RMS value) at
38.9 MHz and 45.75 MHz
−1 dB video at output
∆Vo int.
internal IF amplitude difference
between picture and sound carrier
within AGC range;
B/G: ∆f = 5.5 MHz;
M/N: ∆f = 4.5 MHz
GIF
IF gain control
see Fig.4
68
−
dB
upper cut-off frequency 70
100
−
MHz
input resistance (differential)
1.7
2.2
2.7
kΩ
Ci
input capacitance (differential)
1.2
1.7
2.5
pF
V1, 2
DC input voltage
3.0
3.4
3.8
V
B
−3 dB IF bandwidth
Ri
True synchronous video demodulator
note 2
fVCO
maximum oscillator frequency for
carrier regeneration
f = 2fPC
125
130
−
MHz
∆fVCO
oscillator drift (free running) as a
function of temperature
IAFC = 0; note 3
−
−
±20
ppm/K
Vo ref
oscillator swing at pins 16 and 17
(RMS value)
fPC = 38.9 MHz
−
120
−
mV
fPC = 45.75 MHz
−
100
−
mV
fPC = 58.75 MHz
−
80
−
mV
1.5
2
−
MHz
1.5
2
−
MHz
−
−
30
ms
∆fPC
vision carrier capture range
(negative)
vision carrier capture range (positive)
tacqu
July 1994
acquisition time
BL = 60 kHz; note 4
7
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
SYMBOL
Vi IF
Iloop
PARAMETER
TDA9800
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IF input signal sensitivity
(RMS value, pins 1 and 2)
for PLL still locked
maximum IF gain;
note 5
−
50
90
µV
for C/N = 10 dB
note 6
−
100
140
µV
note 7
−
−
±4.5
µA
0.9
1.0
1.1
V
FPLL loop offset current at pin 6
Composite video amplifier (pin 13)
sound carrier off
V0 vid
output signal (peak-to-peak value)
see Fig.7
V13
sync level
1.4
1.5
1.6
V
zero carrier level
−
2.6
−
V
upper video clipping level
VP − 1.1 VP − 1.0 −
V
lower video clipping level
−
0.3
0.4
V
sound carrier on; note 8 −
V0 FM
IF intercarrier level (RMS value)
R13
output resistance
Iint13
internal bias current for emitter
follower
DC
I13
maximum output sink current
DC and AC
maximum output source current
170
−
mV
−
−
10
Ω
1.8
2.5
−
mA
1.4
−
−
mA
2.0
−
−
mA
B
−3 dB video bandwidth
C13 < 50 pF; RL >1 kΩ
7
10
−
MHz
αH
suppression of video signal
harmonics
C13 < 50 pF; RL >1 kΩ;
note 9
35
40
−
dB
RR
ripple rejection on pin 13
see Fig.9
32
35
−
dB
CVBS buffer amplifier and noise clipper (pins 7 and 14)
R14
input resistance
2.6
3.3
4.0
kΩ
C14
input capacitance
1.4
2
3.0
pF
V14
DC voltage at input
pin 14 not connected
1.5
1.8
2.1
V
Gv
voltage gain
note 10
6
7
7.5
dB
Vo CVBS
CVBS output signal on pin 7
(peak-to-peak value)
sound carrier off;
see Fig.3
1.7
2.0
2.3
V
CVBS output level
upper video clipping
3.9
4.0
−
V
lower video clipping
−
1.0
1.1
V
sync level
−
1.35
−
V
−
−
10
Ω
1.8
2.5
−
mA
R7
output resistance
Iint7
internal bias current for emitter
follower
DC
I7
maximum output sink current
DC and AC
maximum output source current
B
July 1994
−3 dB video bandwidth
C7 < 20 pF; RL > 1 kΩ
8
1.4
−
−
mA
2.4
−
−
mA
8
11
−
MHz
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
SYMBOL
PARAMETER
TDA9800
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Measurements from IF input to CVBS output (pin 7) 330 Ω between pins 13 and 14, sound carrier off
Vo CVBS
CVBS output signal on pin 7
(peak-to-peak value)
∆Vo
deviation of CVBS output signal at
B/G
1.7
2.0
2.3
V
50 dB gain control
−
−
0.5
dB
30 dB gain control
−
−
0.1
dB
black level tilt
note 11
−
−
1
%
∆G
differential gain
−
2
5
%
∆ϕ
differential phase
CCIR line 330 or
NTC-7 Composite
−
1
3
deg
B
−3 dB video bandwidth
CL < 20 pF; RL > 1 kΩ
6
8
−
MHz
S/N(W)
signal-to-noise ratio; weighted
see Fig.5 and note 12
56
59
−
dB
α0.92/1.1
intermodulation at ‘blue’
f = 0.92 or 1.1 MHz;
see Fig.6 and note 13
56
62
−
dB
58
64
−
dB
f = 2.76 or 3.3 MHz;
see Fig.6 and note 13
56
62
−
dB
intermodulation at ‘yellow’
57
63
−
dB
αC
residual vision carrier (RMS value)
fundamental wave
−
1
10
mV
harmonics
−
1
10
mV
αH
suppression of video signal
harmonics
note 9
35
40
−
dB
RR
ripple rejection on pin 7
see Fig.9
25
28
−
dB
response to an increasing amplitude
step of 50 dB in input signal
−
1
10
ms
response to a decreasing amplitude
step of 50 dB in input signal
−
50
100
ms
0.85
1.1
1.35
mA
17
22
27
µA
maximum gain
0
see
Fig.4
−
V
minimum gain
−
see
Fig.4
VP − 0.7 V
intermodulation at ‘yellow’
α2.76/3.3
intermodulation at ‘blue’
AGC detector (pin 19)
tresp
I19
charging current
note 11
discharging current
V19
July 1994
AGC voltage
9
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
SYMBOL
PARAMETER
TDA9800
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Tuner AGC (pin 12)
Vi
V12
IF input signal for minimum starting
point of tuner take over (RMS value)
input at pins 1 and 2;
RTOP = 22 kΩ
−
−
5
mV
IF input signal for maximum starting
point of tuner take over (RMS value)
input at pins 1 and 2;
RTOP = 0 Ω
50
−
−
mV
allowable voltage
from external source
−
−
13.2
V
saturation voltage
I12 = 1.7 mA
−
−
0.2
V
∆V12
variation of take over point by
temperature
I12 = 0.4 mA
−
0.02
0.06
dB/K
I12
sink current
see Fig.4
no tuner gain reduction
−
0.1
0.3
µA
maximum tuner gain
reduction
1.7
2.0
2.6
mA
tuner gain current from
20 to 80%
−
6
8
dB
38.9 MHz
−0.6
−0.72
−0.84
µA/kHz
45.75 MHz
−0.45
−0.6
−0.75
µA/kHz
58.75 MHz
−0.38
−0.5
−0.62
µA/kHz
−
−
±20
ppm/K
∆GIF
IF slip by automatic gain control
AFC circuit (pin 15)
S
control steepness ∆I15/∆f
see Fig.8 and note 14
note 15
∆fIF
frequency variation by temperature
IAFC = 0; note 3
V15
output voltage upper limit
see Fig.8
I15
∆I15
VP − 0.5 VP − 0.3 −
V
output voltage lower limit
−
0.3
0.5
V
output current source
160
200
240
µA
output current sink
160
200
240
µA
residual video modulation current
(peak-to-peak value)
−
20
30
µA
Sound mute switch (pin 5)
note 16
VIL
input voltage for MUTE-ON
0
−
0.8
V
VIH
input voltage for MUTE-OFF
1.5
−
VP
V
IIL
LOW level input current
V5 = 0 V
−
−300
−360
µA
αmute
audio attenuation
V5 = 0 V
70
80
−
dB
∆V5
DC offset voltage at switching (plop)
switching to MUTE-ON
−
100
500
mV
July 1994
10
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
SYMBOL
PARAMETER
FM sound limiter amplifier (pin 11)
Vi FM
input signal (RMS value, pin 11)
TDA9800
CONDITIONS
MIN.
TYP.
MAX.
UNIT
note 17
CCIR468-4
for S/N = 40 dB
see Fig.11
−
200
300
µV
for AM suppression αAM = 40 dB
AM: f = 1 kHz; m = 0.3
−
1
−
mV
200
−
−
mV
46
50
−
dB
480
600
720
Ω
3.5
−
10
MHz
2.3
2.6
2.9
V
catching range of PLL
4
−
7
MHz
holding range of PLL
3.5
−
8
MHz
tacqu
acquisition time
−
−
4
µs
Vo AF
AF output signal (RMS value, pin 9)
∆fAF = ±27 kHz;
see Fig.11
280
350
420
mV
maximum output signal handling
THD < 1.5%
0.8
−
−
V
−
3
7
10-3 dB/K
maximum input signal handling
(RMS value)
αAM
AM suppression
R11
input resistance
B
−3 dB IF frequency response of
sound IF
V11
DC voltage
see Fig.10;
AM: f = 1 kHz; m = 0.3
lower and upper
cut-off frequency
FM-PLL sound demodulator and AF output (pin 9) note 17
fi FM
∆Vo
temperature drift of AF output signal
∆fAF
frequency deviation
THD < 1.5%; note 18
−
−
±50
kHz
V10
DC voltage at decoupling capacitor
voltage dependent on
VCO frequency;
note 19
1.2
−
2.2
V
R9
output resistance
−
100
−
Ω
RL
load resistance (pin 9)
2.2
−
−
kΩ
V9
DC voltage
1.6
2.0
2.4
V
B
−3 dB audio frequency bandwidth
95
120
−
kHz
THD
total harmonic distortion
without ceramic filter
−
0.1
0.5
%
S/N (W)
signal-to-noise ratio, weighted
CCIR468-4; see Fig.11
50
55
−
dB
VSC
residual sound carrier and
harmonics (RMS value)
−
−
75
mV
RR
ripple rejection on pin 9
26
30
−
dB
see Fig.9
Measurements from IF input to audio output (pin 9) 560 Ω between pins 13 and 11; note 20
S/N (W)
July 1994
weighted signal-to-noise ratio
27 kHz FM deviation; CCIR468-4; 50 µs (75 µs at standard M)
de-emphasis; with offset alignment on pin 4
6 kHz sinusoidal waveform
black-to-white
39
46
−
dB
black picture
sync only
40
48
−
dB
white picture
39
46
−
dB
colour bar
39
46
−
dB
11
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
Notes
1. Values of video and sound parameters are decreased at VP = 4.5 V.
2. Loop bandwidth BL = 60 kHz (natural frequency fn = 15 kHz; damping factor d = 2 calculated with grey level and
FPLL input signal level). Resonance circuit of VCO: Qo > 50; Cext = 8.2 pF; Cint ≈ 8.5 pF (loop voltage about 2.7 V).
3. Temperature coefficient of external LC-circuit is equal to zero.
4. Vi IF = 10 mV (RMS value); ∆f = 1 MHz (VCO frequency offset related to picture carrier frequency); white picture
video modulation.
5. Vi IF signal for nominal video signal.
6. Transformer at IF input (Fig.3). The C/N ratio at IF input for ‘lock-in’ is defined as the vision IF input signal (sync level,
RMS value) in relation to a superimposed, 5 MHz band-limited white noise signal (RMS value); video modulation:
white picture.
7. Offset current measured between pin 6 and half of supply voltage (V = 2.5 V) under the following conditions: no input
signal at IF input (pins 1 and 2) and IF amplifier gain at minimum (V19 = VP), pin 4 (phase adjust) open-circuit.
8. The intercarrier output signal is superimposed to the video signal at pin 13 and can be calculated by the following
V iSC
V iSC
 V 13 interc. ( p-p ) 
formula: 20 log  ----------------------------------------  = ------------ dB + 6.9 dB ± 2 dB with ------------ dB = sound to picture carrier ratio at IF
V iPC
V iPC
1V ( p-p )
input (pins 1 and 2 in dB and ±2 dB = tolerance of intercarrier output amplitude Vo FM.
9. Measurements taken with SAW filter G1962; modulation: VSB, fvideo > 0.5 MHz, loop bandwidth BL = 60 kHz.
10. The 7 dB buffer gain accounts for 1 dB loss in the sound trap. Buffer output signal is typical 2 V (p-p). If no sound
trap is applied a 330 Ω resistor must be connected from output to input (from pin 13 to pin 14).
11. The leakage current of the AGC capacitor has to be < 1 µA to avoid larger tilt.
12. S/N is the ratio of black-to-white amplitude to the black level noise voltage (RMS value, pin 7). B = 5 MHz weighted
in accordance with CCIR-567 at a source impedance of 50 Ω.
13. α0.92/1.1 = 20 log (Vo at 4.4 (3.58) MHz / Vo at 0.92 (1.1) MHz) + 3.6 dB; α0.92/1.1 value at 0.92 (1.1) MHz related to
black/white signal.
α2.76/3.3 = 20 log (Vo at 4.4 (3.58) MHz / Vo at 2.76 (3.3) MHz); α2.76/3.3 value at 2.76 (3.3) MHz related to colour
carrier.
14. To match the AFC output signal to different tuning systems a current source output is provided (Fig.8).
15. Depending on the ratio ∆C/Co of the LC resonance circuit of VCO (Qo > 50; Co = Cint + Cext; Cext = 8.2 pF;
Cint ≈ 8.5 pF).
16. No mute state is also valid for pin not connected.
17. Input level for second IF from an external generator with 50 Ω source impedance, AC coupled with 10 nF capacitor,
fmod = 1 kHz, 27 kHz (54% FM deviation) of audio reference. A VIF/SIF input signal is not permitted. Pin 19 has to
be connected to positive supply voltage. S/N and THD measurements are taken at 50 µs (75 µs at standard M)
de-emphasis.
18. To allow higher frequency deviation, the resistor Rx on pin 10 (see Fig.12) has to be increased to a value which does
not exceed the AF output signal of nominally 0.35 V for THD = 0.1% (Rx = 4.7 kΩ provides −6 dB amplification).
19. The leakage current of the 2.2 µF capacitor is < 100 nA.
20. For all S/N measurements the used vision IF modulator has to meet the following specification:
- Incidental phase modulation for black-to-white jump less than 0.5 degree.
July 1994
12
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
Table 1
TDA9800
Input frequencies and carrier ratios.
B/G STANDARD
M/N STANDARD
M STANDARD
UNIT
picture carrier
fPC
38.9
45.75
58.75
MHz
sound carrier
fSC
33.4
41.25
54.25
MHz
picture to sound carrier ratio
SC
13
7
7
dB
22 kΩ
(62 kΩ)
VP = 5 V (9 V)
10 µF
22 kΩ
(62 kΩ)
10 nF
0.1 µF
20
1 V (p-p)
video and intercarrier
tuner AGC
CAGC
19
330 Ω
see
(1)
table
2.2 µF
VP
AFC
VCO2
GND
VCO1
17
18
560 Ω
16
Vi(vid)
AFC
15
Vo(vid)
14
13
7
8
TAGC
12
Vi IC
11
TDA9800
1
1:1
vision
IF
50 Ω
2
Vi VIF1
3
Vi VIF2
4
TOP
5
CCS
MUTE
TPLL
390 Ω
13 kΩ
takeover
point
6
Vo CVBS
9
n.c.
Vo AF
10
CAF
2.2 µF
0.1 µF
Vo AF
sound
mute
MED331
Fig.3 Test circuit.
July 1994
13
CVBS
2 V (p-p)
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
MED332
70
handbook, full pagewidth
GIF
60
I12
(mA)
(dB)
50
0
0.2
40
(1) (2) (3)
(4)
30
0.6
20
1.0
10
1.4
0
1.8
2.0
−10
0
1
2
3
4
V19 (V)
5
Fig.4 IF AGC (dashed) and tuner AGC as a function of take over point adjustment.
−3.2 dB
handbook, halfpage
MED333
80
handbook, halfpage
−13.2 dB
S/N
(dB)
−13.2 dB
−24 dB
60
−24 dB
SC CC
40
−10 dB
PC
BLUE
SC CC
PC
YELLOW
MED334
20
0
−60
−40
−20
0
SC = sound carrier level
; with respect to TOP sync level.
CC = chrominance carrier level ; with respect to TOP sync level.
PC = picture carrier level
; with respect to TOP sync level.
20
Vi IF(rms)(dB)
0.06
0.6
6
10
Fig.5
July 1994
Sound shelf attenuation: 17 dB.
60
600
Vi IF(rms)(mV)
Typical signal-to-noise ratio as a function of
IF input signal.
Fig.6
14
Input conditions for intermodulation
measurements.
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
2.6 V
zero carrier
level
2.5 V
white level
handbook, halfpage
TDA9800
1.8 V
sync level
1.5 V
MED335
Fig.7 Video signal levels on output pin 13.
Fig.8 Measurement conditions and typical AFC characteristic.
handbook, full pagewidth
VP
100 mV
(fripple = 70 Hz)
VP = 5 V
TDA9800
MED337
t
Fig.9 Ripple rejection condition.
July 1994
15
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
MED338
0
handbook, full pagewidth
αAM
(dB)
−20
−40
−60
−80
−100
10−1
1
102
10
Vi IC (mV)
103
Fig.10 Typical AM suppression of FM sound demodulator.
MED339
handbook, full pagewidth
60
370
Vo AF
(1)
S/N (W)
(dB)
(mV RMS)
360
50
(2)
350
40
340
30
330
20
10−1
1
10
102
Fig.11 Typical AF output signal and signal-to-noise ratio.
July 1994
16
Vi FM (mV)
103
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
handbook, full pagewidth
22 kΩ
(62 kΩ)
AFC
VP = 5 V (9 V)
10 µF
22 kΩ
(62 kΩ)
10 nF
0.1 µF
20
CAGC
19
sound
trap
GND
VCO2
17
18
video and intercarrier
tuner AGC
560
Ω
(2)
15
µH
see
(1)
table
2.2 µF
VP
330 Ω 1 V (p-p)
(2)
12 V (9 V)
sound
filter
VCO1
AFC
15
16
Vi(vid)
Vo(vid)
(2)
TAGC
Vi IC
14
13
12
11
7
8
9
10
TDA9800
1
2
Vi VIF1
vision
IF
50 Ω
SAW
filter
3
Vi VIF2
4
TOP
CCS
5
6
MUTE
TPLL
Vo CVBS n.c.
390 Ω
13 kΩ
CAF
2.2
kΩ
Rx
(3)
IF input
0.1 µF
G1962
takeover
point
CAF
sound
mute
2.2 µF
CVBS
2 V (p-p)
(1) depends on tuner
Vo AF
22 nF
Fig.12 Application circuit.
July 1994
Vo AF
17
MED340
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
handbook, full pagewidth
TDA9800
120
IF gain range
64 (<70) dB
antenna input
(dBµV)
100
(1)
video
1 V (p-p)
IF signals
(RMS value)
10−1
(V)
0.66 × 10−1
SAW insertion
loss 20 dB
tuner gain
control range
6 dB IF slip
80
10−2
64 dB
IF AGC
60
TOP
10−3
0.66 × 10−3
SAW insertion
loss 20 dB
10−4
40
0.66 × 10−4
40 dB
RF gain
10−5
20
0.66 × 10−5
VHF/UHF
IF
IF amplifier, demodulator
and video
tuner
SAW filter
TDA9800
MED341
(1) depends on TOP
Fig.13 Front end level diagram.
July 1994
18
July 1994
19
Vi VIF2
Vi VIF1
VP
2
1
20
+
+
1
kΩ
CCS
+
TOP
9 kΩ
20
kΩ
3.6 V
3.6 V
+
+
4
+
+
+
3V
+
+
3.65 V
16 kΩ
18
kΩ
5 kΩ
MUTE
5
+
mute
1
kΩ
+
+
1
kΩ
200 µA
50 µA
1
kΩ
14
Vi(vid)
+
TPLL
6
5
kΩ
+
10
pF
20
kΩ
13
VCO
+
TDA9800
40 µA
+
2 kΩ
6.6
kΩ
3.6 V
Vo(vid)
7
5.5
kΩ
670
Ω
n.c.
8
100 Ω
2 mA
+
5 kΩ
57 kΩ
15
pF
5.5
kΩ
190 µA
2.5 kΩ
3.6 V
1.5 pF
2
kΩ
2.5 mA
Vo CVBS
+
6.4
kΩ
11.5 kΩ
2.5 mA
+
9
10
11
MED342
+
+
+
2
mA
12
TAGC
Vo AF
CAF
Vi IC
VIF-PLL demodulator and FM-PLL
detector
Fig.14 Internal circuits.
25 µA
2.5 µA
+
15
16
17
18
VCO1 AFC
GND VCO2
full pagewidth
3
1.1
kΩ
1.1
kΩ
1 mA
19 +
CAGC
Philips Semiconductors
Preliminary specification
TDA9800
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
PACKAGE OUTLINES
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
w M
(e 1)
b
MH
11
20
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
inches
0.17
0.020
0.13
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
D
e
e1
L
ME
MH
w
Z (1)
max.
6.40
6.22
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2.0
0.25
0.24
0.10
0.30
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.078
(1)
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT146-1
July 1994
REFERENCES
IEC
JEDEC
EIAJ
SC603
20
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-05-24
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
11
20
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
e
bp
detail X
w M
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.419
0.043
0.050
0.055
0.394
0.016
inches
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013AC
July 1994
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
21
o
8
0o
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
July 1994
TDA9800
22
Philips Semiconductors
Preliminary specification
VIF-PLL demodulator and FM-PLL detector
TDA9800
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
July 1994
23