INTEGRATED CIRCUITS DATA SHEET TDA9802 Multistandard VIF-PLL demodulator and FM-PLL detector Preliminary specification File under Integrated Circuits, IC02 November 1992 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector TDA9802 • AGC output voltage for tuner; adjustable take-over point (TOP) FEATURES • Suitable for negative and positive vision modulation • AFC detector without extra reference circuit • Gain controlled 3-stage IF amplifier; suitable for VIF frequencies up to 60 MHz • Alignment-free FM-PLL detector with high linearity • Stabilizer circuit for ripple rejection and to achieve constant output signals • True synchronous demodulation with active carrier regeneration (ultra-linear demodulation, good intermodulation figures, reduced harmonics and excellent pulse response) • 5 to 8 V positive supply voltage range, low power consumption (300 mW at +5 V supply voltage) • Peak sync AGC for negative modulation, e.g. B/G standard GENERAL DESCRIPTION • Peak white AGC for positive modulation, e.g. L standard The TDA9802 is a monolithic integrated circuit for vision and sound IF signal processing in multistandard TV and VTR sets. • Video amplifier to match sound trap and sound filter QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VP positive supply voltage (pin 20) 4.5 5 8.8 V IP supply current 51 60 69 mA Vi IF vision IF input signal sensitivity (RMS value, pins 1 and 2) − 50 90 µV maximum vision IF input signal (RMS value, pins 1 and 2) 70 150 − mV Gv IF gain control range 70 73 dB Vo CVBS CVBS output signal on pin 7 (peak-to-peak value) 1.7 2.0 2.3 V B −3 dB video bandwidth on pin 7 6 8 − MHz S/N (W) signal-to-noise ratio weighted; for video 56 59 − dB α1.1 intermodulation attenuation 64 α3.3 56 62 − dB 56 62 − dB αH suppression of harmonics in video signal 35 40 − dB Vo AF maximum AF output signal for THD < 1.5% (RMS value, pin 9) 0.8 − − V Tamb operating ambient temperature range 0 − +70 °C ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS TDA9802 TDA9802T PIN POSITION MATERIAL 20 DIL plastic SOT146(1) 20 mini-pack plastic SOT163A(2) Note 1. SOT146-1; 1996 November 19. 2. SOT163-1; 1996 November 19. November 1992 2 CODE Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector Fig.1 Block diagram. November 1992 3 TDA9802 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector TDA9802 PINNING SYMBOL Vi IF PIN 1 DESCRIPTION vision IF differential input signal 2 TADJ 3 tuner AGC take-over adjust (TOP) φADJ 4 phase detector adjust CBL 5 black level capacitor, mute switch input TPLL 6 PLL time constant of phase detector Vo CVBS 7 CVBS (positive) output signal STD 8 standard switch (negative = HIGH, positive = LOW) Vo AF 9 audio frequency output signal CAF 10 decoupling capacitor of audio frequency amplifier Vi IC 11 sound intercarrier input signal TAGC 12 tuner AGC output Vo VID 13 video and sound intercarrier output signal Vi VID 14 video input signal to buffer amplifier AFC 15 automatic frequency control output VCO1 16 VCO reference circuit for 2 fPC VCO2 17 GND 18 ground (0 V) CAGC 19 AGC capacitor VP 20 positive supply voltage November 1992 Fig.2 Pin configuration. 4 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector TDA9802 FUNCTIONAL DESCRIPTION VCO and travelling wave divider Vision IF input The VCO operates with a symmetrically-connected reference LC-circuit, operating at double vision carrier frequency. Frequency control is performed by an internal varicap diode. The voltage to set the VCO frequency to the actual frequency of double vision carrier frequency, is also amplified and converted for the AFC output current. The VCO signal is divided-by-two in a travelling wave divider, which generates two differential output signals with 90 degree phase difference independent of frequency. The vision IF amplifier consists of three AC-coupled differential amplifier stages; each stage comprises a controlled feedback network by means of emitter degeneration. IF and tuner AGC The automatic control voltage to maintain the video output signal at a constant level is generated according to the transmission standard. For negative modulation the peak-sync level is detected, for positive modulation the peak white level is detected. The AGC detector charges and discharges the capacitor on pin 19 to set the IF gain and the tuner gain. The standard is switched by the voltage on pin 8. To reduce the response time for positive modulation (which needs a very long time constant) a black level detector (CBL) increases the AGC capacitor discharge current for low-level video signals. The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the tuner AGC to generate the tuner AGC output current on pin 12 (open-collector output). The tuner AGC voltage take over point is adjusted on pin 3. This allows the tuner and the IF SAW filter to be matched to achieve the optimum IF input level. Video amplifier, buffer and noise clipping The video amplifier is a wide bandwidth operational amplifier with internal feedback. Dependent on transmission standard, a level shifter provides the same sync level for positive as for negative modulation. A nominal positive modulated video signal of 1 V (p-p) is present on the composite video output (pin 13). The input impedance of the 7 dB wideband buffer amplifier (with internal feedback) is suitable for ceramic sound trap filters. The CVBS output (pin 7) provides a positive video signal of 2 V (p-p). Noise clipping is provided internally. Sound demodulation Frequency detector, phase detector and video demodulator The FM sound intercarrier signal is fed to pin 11 and through a limiter amplifier before it is demodulated. This achieves high sensitivity and high AM suppression. The limiter amplifier consists of seven internal AC-coupled stages, minimizing the DC offset. The FM-PLL demodulator consists of an RC-oscillator, loop filter and phase detector. The oscillator frequency is locked on the FM intercarrier signal from the limiter amplifier. As a result of this locking, the RC-oscillator is frequency-modulated. The modulating signal voltage (AF signal) is used to control the oscillator frequency. By this, the FM-PLL operates as an FM demodulator. The audio frequency amplifier with internal feedback is designed for high gain and high common mode rejection. The low-level AF signal output from the FM-PLL demodulator is amplified and buffered in a low-ohmic audio signal output stage (pin 9). An external decoupling capacitor on pin 10 removes the DC voltage from the audio amplifier input. The IF amplifier output signal is fed to a frequency detector and to a phase detector. The frequency detector is operational before lock-in. A DC current is generated which is proportional to the frequency difference between the input frequency and the VCO frequency. After lock-in, the frequency detector and the phase detector generate a DC current proportional to the phase difference between VCO and input signals. The control signal for the VCO is provided by the phase detector. The video demodulator is a linear multiplier, designed for low distortion and wide bandwidth. The vision IF input signal is multiplied by the in-phase component of the VCO output. The demodulated output signal is fed via an integrated low-pass filter (fg = 12 MHz) to the video amplifier for suppression of the carrier harmonics. The polarity of the video signal is switched in the demodulator stage according to the TV standard. November 1992 5 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector TDA9802 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134) SYMBOL PARAMETER MIN. MAX. UNIT supply voltage (pin 20) for a maximum chip temperature (note 1) VP SOT146 at + 120 °C 0 8.8 V SO163A at + 100 °C 0 5.5 V VI voltage on pins 1, 2, 7, 8, 11, 13, 14, 15 and 19 0 VP V ts max short-circuit time − 10 s V12 tuner AGC output voltage − 13.2 V Tstg storage temperature range −25 +150 °C VESD electrostatic handling for all pins (note 2) − ±300 V Notes to the Limiting Values 1. Supply current IP = 69 mA at Tamb = +70 °C. 2. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor (negative and positive voltage). THERMAL RESISTANCE SYMBOL Rth j-a November 1992 PARAMETER THERMAL RESISTANCE from junction to ambient in free air SOT146 73 K/W SOT163A 85 K/W 6 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector TDA9802 CHARACTERISTICS VP = 5 V; Tamb = +25 °C; fPC = 38.9 MHz; fSC = 33.4 MHz with VPC/VSC = 13 dB (B/G); ViIF = 10 mV RMS value (sync level at B/G; peak-white level at L); video modulation DSB; residual carrier: B/G = 10%, L = 3%; video signal in accordance with CCIR line 17; measurements taken in Fig.3 unless otherwise specified SYMBOL PARAMETER VP supply voltage range (pin 20) IP supply current CONDITIONS MIN. TYP. 4.5 5 8.8 V 51 60 69 mA see note 2 1.5 − VP V 0 − 0.8 V V8 = 0 V − −300 −360 µA see note 1 MAX. UNIT Standard switch input (pin 8) VIH input voltage for negative modulation VIL input voltage for positive modulation IIL LOW level input current Vision IF input (pins 1 and 2) Vi B/G standard input signal sensitivity (RMS value) −1 dB video at output − 50 90 µV maximum input signal (RMS value) +1 dB video at output 70 150 − mV 1 dB ∆Vi IF amplitude difference between picture and within AGC range sound carrier − 0.7 GIF IF gain control range see Fig.4 64 70 73 dB B −3 dB IF bandwidth upper cut-off frequency 70 100 − MHz Ri input resistance 1.7 2.2 2.7 kΩ Ci input capacitance 1.2 1.7 2.5 pF V1, 2 DC input voltage 3.0 3.4 3.8 V True synchronous video demodulator see note 3 fVCO maximum oscillator frequency for carrier regeneration f = 2fPC 125 130 − MHz ∆fVCO oscillator drift (free running) as a function of temperature see note 4; ∆T = 0 to+70 °C − − ±1300 10−6 Vo ref oscillator swing at pins 16 and 17 (RMS value) tbn 120 tbn mV vision carrier capture range (negative) 1.5 2 − MHz vision carrier capture range (positive) 1.5 2 − MHz see note 5; BL = 60 kHz − − 30 ms for PLL still locked see note 6; maximum IF gain − 70 100 µV for C/N = 10 dB see note 7 − 100 140 µV FPLL loop offset current at pin 6 see note 8 − − ±4.5 µA ∆fPC tacqu acquisition time Vi IF IF input signal sensitivity (RMS value, pins 1 and 2) Iloop November 1992 7 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector SYMBOL PARAMETER Composite video amplifier (pin 13) TDA9802 CONDITIONS MIN. TYP. MAX. UNIT sound carrier off V0 vid output signal (peak-to-peak value) see Fig.7 0.9 1.0 1.1 V V13 sync level B/G and L 1.4 1.5 1.6 V zero carrier level B/G 2.5 2.6 2.7 V L 1.37 1.47 1.57 V upper video clipping level VP − 1.1 VP − 1.0 − V lower video clipping level − 0.3 0.4 V tbn 140 tbn mV − − 10 Ω 1.8 2.5 − mA V0 FM IF intercarrier level (RMS value) R13 output resistance Iint13 internal bias current for emitter follower DC I13 maximum output sink current DC and AC sound carrier on; see note 9 maximum output source current 1.4 tbn − mA 2.0 tbn − mA B −3 dB video bandwidth C13 < 50 pF; RL > 1 kΩ 7 10 − MHz αH suppression of video signal harmonics see note 10; C13 < 50 pF; RL > 1 kΩ 35 40 − dB RR ripple rejection on pin 13 see Fig.9 32 35 − dB CVBS buffer amplifier and noise clipper (pins 7 and 14) R14 input resistance 2.6 3.3 4.0 kΩ C14 input capacitance 1.4 2 3.0 pF V14 DC voltage at input pin 14 not connected 1.5 1.8 2.1 V Gv voltage gain see note 11 6 7 7.5 dB Vo CVBS CVBS output signal on pin 7 (peak-to-peak value) sound carrier off; see Fig.3 1.7 2.0 2.3 V CVBS output level upper video clipping tbn 4.0 − V lower video clipping − 1.0 tbn V sync level R7 output resistance Iint7 internal bias current for emitter follower DC I7 maximum output sink current DC and AC maximum output source current B −3 dB video bandwidth November 1992 C7 < 20 pF; RL > 1 kΩ 8 1.25 1.35 1.45 V − − 10 Ω 1.8 2.5 − mA 1.4 tbn − mA 2.4 tbn − mA 8 11 − MHz Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector SYMBOL PARAMETER TDA9802 CONDITIONS MIN. TYP. MAX. UNIT Measurements from IF input to CVBS output (pin 7) 330 Ω between pins 13 and 14, sound carrier off Vo CVBS CVBS output signal on pin 7 (peak-to-peak value) 1.7 2.0 2.3 V ∆Vo deviation of CVBS output signal at B/G 50 dB gain control − − 0.5 dB 30 dB gain control − − 0.1 dB black level tilt B/G standard; see note 12 − − 1 % vertical tilt for worst case in L standard vision carrier modulated by test line (VITS) only; see note 12 − − 1.5 % − 2 5 % ∆G differential gain ∆ϕ differential phase − 1 3 deg B −3 dB video bandwidth CL < 20 pF; RL > 1 kΩ 6 8 − MHz S/N(W) signal-to-noise ratio; weighted see Fig.5 and note 13 56 59 − dB α1.1 intermodulation at ‘blue’ see Fig.6 and note 14; f = 1.1 MHz 56 62 − dB 58 64 − dB 56 62 − dB intermodulation at ‘yellow’ see Fig.6 and note 14; f = 3.3 MHz 57 63 − dB residual vision carrier (RMS value) fundamental wave − 1 10 mV harmonics − 1 10 mV intermodulation at ‘yellow’ α3.3 αC intermodulation at ‘blue’ αH suppression of video signal harmonics see note 10 35 40 − dB RR ripple rejection on pin 7 see Fig.9 25 28 − dB response to an increasing amplitude step of 50 dB in input signal B/G and L − 1 10 ms response to a decreasing amplitude step of 50 dB in input signal B/G − 50 100 ms L − 100 150 ms charging current B/G and L; see note 12 0.85 1.1 1.35 mA additional charging current L in case of missing VITS pulses and no white video content 2.0 2.7 3.5 µA discharging current B/G 17 22 27 µA normal mode L 0.24 0.33 0.42 µA fast mode L 31 44 57 µA maximum gain 0 tbn − V minimum gain − tbn VP − 0.7 V AGC detector (pin 19) tresp I19 V19 V13 AGC voltage see Fig.4 threshold voltage level see Fig.7 for additional charging current L 1.9 1.95 2.0 V for fast L mode L 1.6 1.65 1.7 V November 1992 9 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector SYMBOL PARAMETER TDA9802 CONDITIONS MIN. TYP. MAX. UNIT Tuner AGC (pin 12) Vi V12 IF input signal for minimum starting point of tuner take over (RMS value) input at pins 1 and 2; RTOP = 22 kΩ − − 5 mV IF input signal for maximum starting point of tuner take over (RMS value) input at pins 1 and 2; RTOP = 0 Ω 50 − − mV allowable voltage from external source − − 13.2 V saturation voltage I12 = 1.7 mA − − 0.2 V ∆V12 variation of take over point by temperature ∆T = 0 to +50 °C − 1 3 dB I12 sink current see Fig.4 no tuner gain reduction − 0.1 0.3 µA maximum tuner gain reduction 1.7 2.0 2.6 mA tuner gain current from 20 to 80% − 6 8 dB ∆GIF IF slip by automatic gain control AFC circuit (pin 15) see Fig.8 and note 15 S control steepness ∆I15/∆f see note 16 0.6 0.72 0.84 µA/kHz ∆fIF frequency variation by temperature ∆T = 0 to +70 °C; see note 4 − − ±1300 10−6 V15 output voltage upper limit see Fig.8 VP − 0.5 VP − 0.3 − V output voltage lower limit − 0.3 0.5 V output current source 160 200 240 µA I15 output current sink ∆I15 residual video modulation current (peak-to-peak value) Sound mute switch (pin 5) B/G and L 160 200 240 µA − 20 30 µA see note 17 VIL input voltage for MUTE-ON 0 − 0.8 V VIH input voltage for MUTE-OFF 1.5 − VP V IIL LOW level input current V5 = 0 V − −300 −360 αmute audio attenuation V5 = 0 V 70 80 − dB ∆V5 DC offset voltage at switching (plop) switching to MUTE-ON − 100 500 mV FM sound limiter amplifier (pin 11) Vi FM µA FM 5.5 MHz input signal (RMS value, pin 11) CCIR468-4 for S/N = 40 dB see Fig.11 − 200 300 µV for AM suppression αAM = 40 dB AM: f = 1 kHz; m = 0.3 − 1 − mV maximum input signal handling (RMS value) 200 − − mV R11 input resistance 480 600 720 Ω B −3 dB IF frequency response of sound IF 3.5 − 10 MHz V11 DC voltage 2.3 2.6 2.9 V November 1992 lower and upper cut-off frequency 10 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector SYMBOL PARAMETER TDA9802 MIN. TYP. catching range of PLL 4 − 7 MHz holding range of PLL 3.5 − 8 MHz tacqu acquisition time − − 4 µs ∆fAF frequency deviation THD < 1.5%; see note 19 − − ±50 kHz V10 DC voltage at decoupling capacitor voltage dependent on VCO frequency; see note 20 1.2 − 2.2 V Vo AF AF output signal (RMS value, pin 9) ∆fAF = ±27 kHz; see Fig.11 280 350 420 mV FM−PLL sound demodulator and AF output (pin 9) fi FM CONDITIONS MAX. UNIT see note 18 maximum output signal handling THD < 1.5% 0.8 − − V ∆Vo temperature drift of AF output signal ∆T = 0 to+70 °C − 0.2 0.5 dB R9 output resistance − 100 − Ω RL load resistance (pin 9) 2.2 − − kΩ V9 DC voltage 1.6 2.0 2.4 V B −3 dB audio frequency bandwidth 95 120 − kHz − 0.1 0.5 % 50 55 − dB − − 75 mV THD total harmonic distortion S/N (W) signal-to-noise ratio, weighted VSC residual sound carrier and harmonics (RMS value) αAM AM suppression see Fig.10; AM: f = 1 kHz; m = 0.3 46 50 − dB RR ripple rejection on pin 9 see Fig.9 26 30 − dB CCIR468-4; see Fig.11 Measurements from IF input to audio output (pin 9) 560 Ω between pins 13 and 11 S/N (W) weighted signal-to-noise ratio referred to 54% FM modulation CCIR468-4; with offset alignment on pin 4 6 kHz sinusoidal waveform black-to-white 39 46 − dB black level sync only 39 48 − dB 39 46 − dB white picture November 1992 11 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector TDA9802 Notes to the characteristics 1. Typical values of video and sound parameters are decreased at VP = 4.5 V. 2. The input voltage for negative modulation has to be V8 > 1.5 V, or pin 8 open-circuit. 3. Loop bandwidth BL = 60 kHz (natural frequency fn = 15 kHz; damping factor d = 2 calculated with grey level and FPLL input signal level). Resonance circuit of VCO: Qo > 50; Cext = 8.2 pF; Cint ≈ 8.5 pF (loop voltage about 2.7 V). 4. The oscillator drift is related to the picture carrier frequency (at external temperature-compensated LC-circuit). 5. Vi IF = 10 mV (RMS value); ∆f = 1 MHz (VCO frequency offset related to picture carrier frequency); white picture video modulation. 6. Vi IF for 0.9 V CVBS (peak-to-peak value) at composite video output pin 13; PLL is still locked. 7. Transformer at IF input (Fig.3). The C/N ratio at IF input for ‘lock-in’ is defined as the vision IF input signal (sync level, RMS value) in relation to a superimposed, 5 MHz band-limited white noise signal (RMS value); video modulation: white picture. 8. Offset current measured between pin 6 and half of supply voltage (V = 2.5 V) under the following conditions: no input signal at IF input (pins 1 and 2) and IF-amplifier gain at minimum (V19 = VP), pin 4 (phase adjust) open-circuit. 9. The intercarrier output signal is superimposed to the video signal at pin 13 and can be calculated by the following formula: V iSC V 13 interc. ( p – p ) 20 log ------------------------------------------ = ------------ dB + 6.9 dB ± 2 dB V 1V ( p – p ) iPC with V iSC ------------ dB = sound to picture carrier ratio at IF input (pins 1 and 2) in dB V iPC and ±2 dB = tolerance of intercarrier output amplitude Vo FM. 10. Measurements taken with SAW filter G1956; modulation: VSB, fvideo > 0.5 MHz, loop bandwidth BL = 60 kHz. 11. The 7 dB buffer gain accounts for 1 dB loss in the sound trap. Buffer output signal is typical 2 V (p-p). If no sound trap is applied a 330 Ω resistor must be connected from output to input (from pin 13 to pin 14). 12. The leakage current of the AGC capacitor has to be < 1 µA in B/G mode (< 30 nA in L mode) to avoid larger tilt. 13. S/N is the ratio of black-to-white amplitude to the black level noise voltage (RMS value, pin 7). B = 5 MHz weighted in accordance with CCIR-567 at a source impedance of 50 Ω. 14. α1.1 = 20 log (Vo at 4.4 MHz / Vo at 1.1 MHz) + 3.6 dB; α1.1 value at 1.1 MHz related to black/white signal α3.3 = 20 log (Vo at 4.4 MHz / Vo at 3.3 MHz); α3.3 value at 3.3 MHz related to colour carrier. 15. To match the AFC output signal to different tuning systems a current source output is provided (Fig.8). 16. Depending on the radio ∆C/Co of the LC resonance circuit of VCO (Qo > 50; Co = Cint+Cext; Cext = 8.2 pF; Cint ≈ 8.5 pF). 17. No mute state is also valid for pin not connected. For switching on the L-standard no external load is allowed at pin 5 except capacitor CBL. 18. A 5.5 MHz signal for second IF with 10 mV (RMS value) input level, fmod = 1 kHz and frequency deviation with 54% FM modulation of audio reference is fed directly to pin 11. Audio measurements are taken at 50 µs de-emphasis. 19. To allow higher frequency deviation, the resistor Rx on pin 10 (see Fig.12) has to be increased to a value which does not exceed the AF output signal of nominally 0.35 V for THD = 0.1% (Rx = 4.7 kΩ provides −6 dB amplification). 20. The leakage current of the 2.2 µF capacitor is < 100 nA. November 1992 12 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector Fig.3 Test circuit. November 1992 13 TDA9802 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector TDA9802 MED332 70 handbook, full pagewidth GIF 60 I12 (mA) (dB) 50 0 0.2 40 (1) (2) (3) (4) 30 0.6 20 1.0 10 1.4 0 1.8 2.0 −10 0 1 2 3 4 V19 (V) 5 Fig.4 IF AGC (dashed) and tuner AGC as a function of take over point adjustment. MED333 80 handbook, halfpage −3.2 dB handbook, halfpage S/N (dB) −13.2 dB 60 −13.2 dB −24 dB −10 dB −24 dB 40 SC CC PC BLUE SC CC PC YELLOW MED334 20 SC = sound carrier level 0 −60 −40 −20 0 ; with respect to TOP sync level. CC = chrominance carrier level ; with respect to TOP sync level. PC = picture carrier level ; with respect to TOP sync level. 20 Vi IF(rms)(dB) 0.06 0.6 6 10 Fig.5 60 600 Vi IF(rms)(mV) Sound shelf attenuation: 17 dB. Typical signal-to-noise ratio as a function of IF input signal. November 1992 Fig.6 14 Input conditions for intermodulation measurements. Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector Fig.7 Video signal levels on output pin 13. Fig.8 Measurement conditions and typical AFC characteristic. Fig.9 Ripple rejection condition. November 1992 15 TDA9802 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector TDA9802 MED338 0 handbook, full pagewidth αAM (dB) −20 −40 −60 −80 −100 10−1 1 102 10 Vi IC (mV) 103 Fig.10 Typical AM suppression of FM sound demodulator. MED339 handbook, full pagewidth 60 370 Vo AF (1) S/N (W) (dB) (mV RMS) 360 50 (2) 350 40 340 30 330 20 10−1 1 10 102 Fig.11 Typical AF output signal and signal-to-noise ratio. November 1992 16 Vi FM (mV) 103 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector (1) depends on tuner Fig.12 Application circuit. November 1992 17 TDA9802 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector (1) depends on TOP Fig.13 Front end level diagram. November 1992 18 TDA9802 Philips Semiconductors Preliminary specification TDA9802 Fig.14 Internal circuits. Multistandard VIF-PLL demodulator and FM-PLL detector November 1992 19 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector TDA9802 PACKAGE OUTLINE DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.020 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 D e e1 L ME MH w Z (1) max. 6.40 6.22 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.0 0.25 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.078 (1) E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 November 1992 REFERENCES IEC JEDEC EIAJ SC603 20 EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-05-24 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector TDA9802 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.419 0.043 0.050 0.055 0.394 0.016 inches 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC November 1992 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 21 o 8 0o Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. November 1992 TDA9802 22 Philips Semiconductors Preliminary specification Multistandard VIF-PLL demodulator and FM-PLL detector TDA9802 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 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