Philips Semiconductors Product specification N-channel TrenchMOS transistor FEATURES PSMN030-150P SYMBOL QUICK REFERENCE DATA • ’Trench’ technology • Very low on-state resistance • Fast switching • Low thermal resistance d VDSS = 150 V ID = 55.5 A g RDS(ON) ≤ 30 mΩ s GENERAL DESCRIPTION SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:• d.c. to d.c. converters • switched mode power supplies The PSMN030-150P is supplied in the SOT78 (TO220AB) conventional leaded package. PINNING SOT78 (TO220AB) PIN DESCRIPTION tab 1 gate 2 drain 3 source tab drain 1 23 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 150 150 ± 20 55.5 39 222 250 175 V V V A A A W ˚C June 2000 Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C 1 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PSMN030-150P AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS EAS Non-repetitive avalanche energy Unclamped inductive load, IAS = 35 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; IAS Non-repetitive avalanche current MIN. MAX. UNIT - 300 mJ - 35 A TYP. MAX. UNIT - 0.6 K/W 60 - K/W THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS SOT78 package, in free air ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; VGS(TO) Drain-source breakdown voltage Gate threshold voltage Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) IGSS IDSS Drain-source on-state VGS = 10 V; ID = 25 A resistance Gate source leakage current VGS = ±10 V; VDS = 0 V Zero gate voltage drain VDS = 150 V; VGS = 0 V; current Tj = 175˚C Tj = 175˚C MIN. TYP. MAX. UNIT 150 133 2.0 1.0 - 3.0 24 2 0.05 - 4.0 6 30 81 100 10 500 V V V V V mΩ mΩ nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 55.5 A; VDD = 120 V; VGS = 10 V - 98 16 38 50 nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 75 V; RD = 1.5 Ω; VGS = 10 V; RG = 5.6 Ω Resistive load - 18 71 97 76 - ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 3680 470 220 - pF pF pF June 2000 2 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PSMN030-150P REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge ISM June 2000 CONDITIONS MIN. TYP. MAX. UNIT - - 55.5 A - - 222 A IF = 25 A; VGS = 0 V - 0.85 1.2 V IF = 20 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V - 109 610 - ns nC 3 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PSMN030-150P Normalised Power Derating, PD (%) Transient thermal impedance, Zth j-mb (K/W) 1 100 D = 0.5 90 80 0.2 0.1 70 0.1 60 0.05 50 0.02 40 P D 0.01 D = tp/T tp 30 single pulse 20 T 10 0.001 1E-06 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 1E-03 1E-02 1E-01 1E+00 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating, ID (%) Drain Current, ID (A) 100 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 90 80 70 60 50 40 30 20 10 0 25 1E-04 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 0 1E-05 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 Tj = 25 C VGS = 10 V 6V 8V 5.4 V 5.2 V 5V 4.8 V 4.6 V 4.4 V 0 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb) 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS Peak Pulsed Drain Current, IDM (A) 1000 Drain-Source On Resistance, RDS(on) (Ohms) RDS(on) = VDS/ ID 0.07 100 4.4 V 0.06 tp = 10 us 4.6 V V 4.8 V 5V Tj = 25 C 5.2 V 0.05 D.C. 10 100 us 0.04 1 ms 0.03 5.4 V 6V 0.02 10 ms VGS = 10V 8V 0.01 100 ms 1 0 1 10 100 Drain-Source Voltage, VDS (V) 1000 0 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp June 2000 5 10 15 20 25 30 Drain Current, ID (A) 35 40 45 50 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(VGS) 4 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PSMN030-150P Drain current, ID (A) 4.5 50 VDS > ID X RDS(ON) 45 Threshold Voltage, VGS(TO) (V) 4 maximum 3.5 40 35 3 30 2.5 175 C 25 typical minimum 2 Tj = 25 C 20 1.5 15 10 1 5 0.5 0 0 0 1 2 3 4 5 6 7 8 9 10 -60 -40 -20 Gate-source voltage, VGS (V) 40 60 80 100 120 140 160 180 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Transconductance, gfs (S) 1.0E-01 VDS > ID X RDS(ON) 50 20 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj 55 0 Drain current, ID (A) Tj = 25 C 45 1.0E-02 40 175 C 35 minimum 1.0E-03 30 typical 25 1.0E-04 20 maximum 15 1.0E-05 10 5 1.0E-06 0 0 5 10 15 20 25 30 35 Drain current, ID (A) 40 45 0 50 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 0.5 1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V) 4 4.5 5 Fig.11. Sub-threshold drain current. ID = f(VGS); Tj = 25 ˚C Normalised On-state Resistance 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 Capacitances, Ciss, Coss, Crss (pF) 10000 Ciss 1000 Coss Crss 100 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 0.1 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) June 2000 1 10 Drain-Source Voltage, VDS (V) 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 5 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PSMN030-150P Maximum Avalanche Current, IAS (A) 100 Gate-source voltage, VGS (V) 16 ID = 55.5A 14 Tj = 25 C 12 25 C VDD = 30 V 10 8 10 VDD =120 V 6 Tj prior to avalanche = 150 C 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 1 0.001 Gate charge, QG (nC) 0.01 0.1 1 10 Avalanche time, tAV (ms) Fig.13. Typical turn-on gate-charge characteristics VGS = f(QG) Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load Source-Drain Diode Current, IF (A) 50 VGS = 0 V 45 40 35 175 C 30 Tj = 25 C 25 20 15 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Source-Drain Voltage, VSDS (V) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj June 2000 6 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PSMN030-150P MECHANICAL DATA Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 E SOT78 A A1 P q D1 D L1 L2(1) Q b1 L 1 2 e e 3 c b 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) (1) UNIT A A1 b b1 c D D1 E mm 4.5 4.1 1.39 1.27 0.9 0.7 1.3 1.0 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 e L L1 2.54 15.0 13.5 3.30 2.79 L2 max. P q Q 3.0 3.8 3.6 3.0 2.7 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 TO-220 Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g) Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8". June 2000 7 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PSMN030-150P DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 2000 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. June 2000 8 Rev 1.000