INTEGRATED CIRCUITS DATA SHEET 74AHC541; 74AHCT541 Octal buffer/line driver; 3-state Product specification Supersedes data of 1998 Sep 21 File under Integrated Circuits, IC06 1999 Nov 24 Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 FEATURES DESCRIPTION • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V The 74AHC/AHCT541 is a high-speed Si-gate CMOS device. The 74AHC/AHCT541 are octal non-inverting buffer/line drivers with 3-state bus compatible outputs. • Balanced propagation delays The 3-state outputs are controlled by the output enable inputs OE0 and OE1. • All inputs have a Schmitt-trigger action • Inputs accepts voltages higher than VCC A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 °C and −40 to +125 °C. QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT AHC AHCT tPHL/tPLH propagation delay An to Yn CL = 15 pF; VCC = 5 V 3.5 3.5 ns CI input capacitance VI = VCC or GND 3 3 pF CO output capacitance 4.0 4.0 pF CPD power dissipation capacitance 10 12 pF CL = 50 pF; f = 1 MHz; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. 1999 Nov 24 2 Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 FUNCTION TABLE See note 1. INPUT OUTPUT OE0 OE1 An Yn L L L L L L H H X H X Z H X X Z Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGES OUTSIDE NORTH AMERICA NORTH AMERICA PINS PACKAGE MATERIAL CODE 74AHC541D 74AHC541D 20 SO plastic SOT163-1 74AHC541PW 74AHC541PW DH 20 TSSOP plastic SOT360-1 74AHCT541D 74AHCT541D 20 SO plastic SOT163-1 74AHCT541PW 7AHCT541PW DH 20 TSSOP plastic SOT360-1 PINNING PIN SYMBOL DESCRIPTION 1 OE0 output enable input 2, 3, 4, 5, 6, 7, 8 and 9 A0 to A7 data inputs 10 GND ground (0 V) 11, 12, 13, 14, 15, 16, 17 and 18 Y7 to Y0 data inputs/outputs 19 OE1 output enable input 20 VCC DC supply voltage 1999 Nov 24 3 Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 handbook, halfpage OE0 1 20 VCC A0 2 19 OE1 A1 3 18 Y0 A2 4 17 Y1 16 Y2 A3 5 A4 6 541 15 Y3 A5 7 14 Y4 A6 8 13 Y5 A7 9 12 Y6 GND 10 11 Y7 MNA178 Fig.1 Pin configuration. handbook, halfpage 2 3 A0 Y0 A1 Y1 A2 Y2 A3 Y3 18 17 handbook, halfpage 4 5 6 7 8 A4 Y4 A5 Y5 A6 Y6 A7 Y7 1 19 & EN 16 15 14 13 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 12 MNA180 9 1 19 11 OE0 OE1 MNA179 Fig.2 Logic symbol. 1999 Nov 24 Fig.3 IEEE/IEC logic symbol. 4 Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL PARAMETER 74AHCT CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. 4.5 5.0 5.5 V VCC DC supply voltage 2.0 5.0 5.5 VI input voltage 0 − 5.5 0 − 5.5 V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature −40 +25 +85 −40 +25 +85 °C −40 +25 +125 −40 +25 +125 °C tr,tf (∆t/∆f) input rise and fall times see DC and AC characteristics per device VCC = 3.3 ±0.3 V − − 100 − − − VCC = 5 ±0.5 V − − 20 − − 20 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK DC input diode current VI < −0.5 V; note 1 − −20 mA VO < −0.5 V or VO > VCC + 0.5 V; note 1 IOK DC output diode current − ±20 mA IO DC output source or sink current −0.5 V < VO < VCC + 0.5 V − ±25 mA ICC DC VCC or GND current − ±75 mA Tstg storage temperature PD power dissipation per package for temperature range: −40 to +125 °C; note 2 −65 +150 °C − 500 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO-package: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP-package: above 60 °C the value of PD derates linearly with 5.5 mW/K. 1999 Nov 24 5 mW Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 DC CHARACTERISTICS Family 74AHC Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL OTHER VIH VIL VOH VOL −40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. 2.0 1.5 − − 1.5 − 1.5 − 3.0 2.1 − − 2.1 − 2.1 − 5.5 3.85 − − 3.85 − 3.85 − 2.0 − − 0.5 − 0.5 − 0.5 3.0 − − 0.9 − 0.9 − 0.9 5.5 − − 1.65 − 1.65 − 1.65 2.0 1.9 2.0 − 1.9 − 1.9 − 3.0 2.9 3.0 − 2.9 − 2.9 − 4.5 4.4 4.5 − 4.4 − 4.4 − VI = VIH or VIL; IO = −4.0 mA 3.0 2.58 − − 2.48 − 2.40 − VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − VI = VIH or VIL; IO = 50 µA 2.0 − 0 0.1 − 0.1 − 0.1 3.0 − 0 0.1 − 0.1 − 0.1 4.5 − 0 0.1 − 0.1 − 0.1 VI = VIH or VIL; IO = 4.0 mA 3.0 − − 0.36 − 0.44 − 0.55 VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 − 1.0 − 2.0 ±2.5 − ±10.0 µA LOW-level input voltage LOW-level output voltage VCC (V) MIN. HIGH-level input voltage HIGH-level output voltage −40 to +85 25 PARAMETER VI = VIH or VIL; IO = −50 µA V V V V V V II input leakage current VI = VCC or GND 5.5 − − 0.1 IOZ 3-state output OFF-state current VI = VIH or VIL; 5.5 VO = VCC or GND − − ±0.25 − ICC quiescent supply current VI = VCC or GND; 5.5 IO = 0 − − 4.0 − 40 − 80 µA CI input capacitance − 3 10 − 10 − 10 pF 1999 Nov 24 − 6 µA Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 Family 74AHCT Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 OTHER VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − 2.0 − 2.0 − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 − 0.8 − 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; IO = −50 µA 4.5 4.4 4.5 − 4.4 − 4.4 − V VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V VI = VIH or VIL; IO = 50 µA 4.5 − 0 0.1 − 0.1 − 0.1 V VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 V − 1.0 − 2.0 µA ±2.5 − ±10.0 µA VOL LOW-level output voltage II input leakage current VI = VIH or VIL 5.5 − − 0.1 IOZ 3-state output OFF-state current VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 − − ±0.25 − ICC quiescent supply current VI = VCC or GND; 5.5 IO = 0 − − 4.0 − 40 − 80 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.35 − 1.5 − 1.5 mA CI input capacitance − 3 10 − 10 − 10 pF 1999 Nov 24 − 7 Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 AC CHARACTERISTICS Type 74AHC541 Ground = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 WAVEFORMS CL MIN. −40 to +125 TYP. MAX. MIN. MAX. MIN. MAX. UNIT VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay An to Yn see Figs 4 and 6 15 pF − 5.0 7.0 1.0 8.5 1.0 9.0 ns tPZL/tPZH propagation delay OEn to Yn see Figs 5 and 6 − 5.5 10.5 1.0 11.0 1.0 13.5 ns tPLZ/tPHZ propagation delay OEn to Yn − 6.0 11.0 1.0 12.0 1.0 14.0 ns tPHL/tPLH propagation delay An to Yn see Figs 4 and 6 50 pF − 7.0 10.5 1.0 12.0 1.0 13.5 ns tPZL/tPZH propagation delay OEn to Yn see Figs 5 and 6 − 7.5 14.0 1.0 16.0 1.0 17.5 ns tPLZ/tPHZ propagation delay OEn to Yn − 9.5 15.4 1.0 17.5 1.0 19.5 ns VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay An to Yn see Figs 4 and 6 15 pF − 3.5 5.0 1.0 6.0 1.0 6.5 ns tPZL/tPZH propagation delay OEn to Yn see Figs 5 and 6 − 3.5 7.2 1.0 8.5 1.0 9.0 ns tPLZ/tPHZ propagation delay OEn to Yn − 4.5 7.5 1.0 8.0 1.0 9.5 ns tPHL/tPLH propagation delay An to Yn see Figs 4 and 6 50 pF − 5.0 7.0 1.0 8.0 1.0 9.0 ns tPZL/tPZH propagation delay OEn to Yn see Figs 5 and 6 − 5.0 9.2 1.0 10.5 1.0 11.5 ns tPLZ/tPHZ propagation delay OEn to Yn − 6.5 8.8 1.0 10.0 1.0 11.0 ns Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. 1999 Nov 24 8 Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 Type 74AHCT541 Ground = 0 V; tr = tf ≤ 3.0 ns. Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER WAVEFORMS CL MIN. −40 to +125 TYP. MAX. MIN. MAX. MIN. MAX. UNIT VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay An to Yn see Figs 4 and 6 15 pF − 3.5 5.5 1.0 6.5 1.0 7.0 ns tPZL/tPZH propagation delay OEn to Yn see Figs 5 and 6 − 4.0 7.0 1.0 8.0 1.0 9.0 ns tPLZ/tPHZ propagation delay OEn to Yn − 5.0 7.0 1.0 8.0 1.0 9.0 ns tPHL/tPLH propagation delay An to Yn see Figs 4 and 6 50 pF − 5.0 8.5 1.0 9.5 1.0 11.0 ns tPZL/tPZH propagation delay OEn to Yn see Figs 5 and 6 − 5.5 10.0 1.0 12.0 1.0 12.5 ns tPLZ/tPHZ propagation delay OEn to Yn − 7.0 10.0 1.0 12.0 1.0 12.5 ns Note 1. Typical values at VCC = 5.0 V. AC WAVEFORMS handbook, halfpage VI An input VM VM GND tPLH tPHL VOH VM Yn output VOL FAMILY VI INPUT REQUIREMENTS VM INPUT VM MNA181 VM OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.4 The input (An) to output (Yn) propagation delays. 1999 Nov 24 9 Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 VI handbook, full pagewidth VM OEn input GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCC VM VOL + 0.3 V VOL tPHZ tPZH VOH VOH − 0.3 V output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled MNA182 VI INPUT REQUIREMENTS FAMILY VM INPUT VM OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.5 The 3-state output enable and disable times. S1 handbook, full pagewidth VCC PULSE GENERATOR VI 1000 Ω VO VCC open GND D.U.T. CL RT MNA183 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit. CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”). RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.6 Load circuitry for switching times. 1999 Nov 24 10 Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC 1999 Nov 24 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 11 Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 1999 Nov 24 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-06-16 95-02-04 MO-153AC 12 o Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Nov 24 13 Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Nov 24 14 Philips Semiconductors Product specification Octal buffer/line driver; 3-state 74AHC541; 74AHCT541 NOTES 1999 Nov 24 15 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 245002/02/pp16 Date of release: 1999 Nov 24 Document order number: 9397 750 06301