PHILIPS 74AHCT126D

INTEGRATED CIRCUITS
DATA SHEET
74AHC126; 74AHCT126
Quad buffer/line driver; 3-state
Product specification
Supersedes data of 1999 Jan 12
File under Integrated Circuits, IC06
1999 Sep 29
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
FUNCTION TABLE
See note 1.
INPUTS
• Inputs accepts voltages higher than
VCC
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Specified from
−40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT126 are
high-speed Si-gate CMOS devices
and are pin compatible with low
power Schottky TTL (LSTTL). They
are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT126 are four
non-inverting buffer/line drivers with
3-state outputs. The 3-state outputs
(nY) are controlled by the output
enable input (nOE) A LOW at nOE
causes the outputs to assume a
HIGH-impedance OFF state.
OUTPUT
nOE
nA
nY
H
L
L
H
H
H
L
X
Z
• Balanced propagation delays
• All inputs have Schmitt-trigger
actions
74AHC126; 74AHCT126
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF state.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay
nA to nY
CL = 15 pF;
VCC = 5 V
3.3
3.0
ns
CI
input capacitance
VI = VCC or GND
3.0
3.0
pF
CO
output capacitance
4.0
4.0
pF
CPD
power dissipation
capacitance
10
12
pF
CL = 50 pF;
f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
The ‘126’ is identical to the ‘125’ but
has active HIGH enable inputs.
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
PINNING
PIN
1999 Sep 29
SYMBOL
DESCRIPTION
1, 4, 10 and 13
1OE to 4OE
output enable inputs (active HIGH)
2, 5, 9 and 12
1A to 4A
data inputs
3, 6, 8 and 11
1Y to 4Y
data outputs
7
GND
ground (0 V)
14
VCC
DC supply voltage
2
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
PACKAGES
NORTH AMERICA
PINS
PACKAGE
MATERIAL
CODE
74AHC126D
74AHC126D
14
SO
plastic
SOT108-1
74AHC126PW
74AHC126PW DH
14
TSSOP
plastic
SOT402-1
74AHCT126D
74AHCT126D
14
SO
plastic
SOT108-1
74AHCT126PW
7AHCT126PW DH
14
TSSOP
plastic
SOT402-1
1OE
1
14 VCC
1A
2
13 4OE
1Y
3
12 4A
2OE
4
2A
5
10 3OE
2Y
6
9
GND
7
8 3Y
handbook, halfpage
nY
nA
11 4Y
126
nOE
3A
MNA234
MNA233
Fig.1 Pin configuration.
Fig.2 Logic diagram.
handbook, halfpage
2
1A
1
1OE
1Y
3
handbook, halfpage
2
1
5
2A
4
2OE
9
3A
2Y
6
1
3
EN1
5
10
3OE
12
4A
13
4OE
6
4
3Y
8
9
8
10
4Y
11
12
11
13
MNA235
MNA236
Fig.3 Functional diagram.
1999 Sep 29
Fig.4 IEC logic symbol.
3
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
RECOMMENDED OPERATING CONDITIONS
74AHC
SYMBOL
PARAMETER
74AHCT
CONDITIONS
UNIT
MIN.
TYP. MAX. MIN.
TYP. MAX.
4.5
5.0
5.5
V
VCC
DC supply voltage
2.0
5.0
5.5
VI
input voltage
0
−
5.5
0
−
5.5
V
VO
output voltage
0
−
VCC
0
−
VCC
V
Tamb
operating ambient temperature
range
−40
+25
+85
−40
+25
+85
°C
−40
+25
+125 −40
+25
+125 °C
tr,tf (∆t/∆f) input rise and fall rates
see DC and AC
characteristics per
device
VCC = 3.3 V ±0.3 V −
−
100
−
−
−
VCC = 5 V ±0.5 V
−
20
−
−
20
−
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
VCC
DC supply voltage
−0.5
+7.0
V
VI
input voltage range
−0.5
+7.0
V
IIK
DC input diode current
VI < −0.5 V; note 1
−
−20
mA
VO < −0.5 V or VO > VCC + 0.5 V; note 1
IOK
DC output diode current
−
±20
mA
IO
DC output source or sink current −0.5 V < VO < VCC + 0.5 V
−
±25
mA
ICC
DC VCC or GND current
−
±75
mA
Tstg
storage temperature range
PD
power dissipation per package
for temperature range: −40 to +125 °C; note 2
−65
+150 °C
−
500
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Sep 29
4
mW
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
DC CHARACTERISTICS
74AHC family
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb (°C)
TEST CONDITIONS
SYMBOL
OTHER
VIH
VIL
VOH
VOL
−40 to +85
25
PARAMETER
HIGH-level input
voltage
LOW-level input
voltage
VCC (V)
−40 to +125 UNIT
MIN.
TYP.
MAX. MIN. MAX. MIN. MAX.
2.0
1.5
−
−
1.5
−
1.5
−
3.0
2.1
−
−
2.1
−
2.1
−
5.5
3.85 −
−
3.85 −
3.85 −
2.0
−
−
0.5
−
0.5
−
0.5
3.0
−
−
0.9
−
0.9
−
0.9
5.5
−
−
1.65
−
1.65
−
1.65
2.0
1.9
2.0
−
1.9
−
1.9
−
3.0
2.9
3.0
−
2.9
−
2.9
−
4.5
4.4
4.5
−
4.4
−
4.4
−
V
V
HIGH-level output
voltage; all
outputs
VI = VIH or VIL;
IO = −50 µA
V
HIGH-level output
voltage
VI = VIH or VIL;
IO = −4.0 mA
3.0
2.58 −
−
2.48 −
2.40 −
VI = VIH or VIL;
IO = −8.0 mA
4.5
3.94 −
−
3.8
−
3.70 −
LOW-level output
voltage; all
outputs
VI = VIH or VIL;
IO = 50 µA
2.0
−
0
0.1
−
0.1
−
0.1
3.0
−
0
0.1
−
0.1
−
0.1
4.5
−
0
0.1
−
0.1
−
0.1
LOW-level output
voltage
VI = VIH or VIL;
IO = 4 mA
3.0
−
−
0.36
−
0.44
−
0.55
VI = VIH or VIL;
IO = 8 mA
4.5
−
−
0.36
−
0.44
−
0.55
−
1.0
−
2.0
±2.5
−
±10.0 µA
V
V
V
II
input leakage
current
VI = VCC or GND
5.5
−
−
0.1
IOZ
3-state output
OFF current
VI = VIH or VIL;
5.5
VO = VCC or GND
−
−
±0.25 −
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
5.5
−
−
2.0
−
20
−
40
µA
CI
input capacitance
−
−
3
10
−
10
−
10
pF
1999 Sep 29
5
µA
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
74AHCT family
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
Tamb (°C)
PARAMETER
−40 to +85
25
OTHER
VCC (V)
−40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH
HIGH-level input
voltage
4.5 to 5.5 2.0
−
−
2.0
−
2.0
−
V
VIL
LOW-level input
voltage
4.5 to 5.5 −
−
0.8
−
0.8
−
0.8
V
VOH
HIGH-level output VI = VIH or VIL;
voltage; all outputs IO = −50 µA
4.5
4.4
4.5
−
4.4
−
4.4
−
V
HIGH-level output
voltage
VI = VIH or VIL;
IO = −8.0 mA
4.5
3.94 −
−
3.8
−
3.70 −
V
LOW-level output VI = VIH or VIL;
voltage; all outputs IO = 50 µA
4.5
−
0
0.1
−
0.1
−
0.1
V
LOW-level output
voltage
VI = VIH or VIL;
IO = 8 mA
4.5
−
−
0.36
−
0.44
−
0.55
V
II
input leakage
current
VI = VIH or VIL
5.5
−
−
0.1
−
1.0
−
2.0
µA
IOZ
3-state output
OFF current
VI = VIH or VIL;
5.5
VO = VCC or GND
per input pin;
other inputs at
VCC or GND;
IO = 0
−
−
±0.25 −
±2.5
−
±10.0 µA
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
−
−
2.0
−
20
−
40
µA
∆ICC
additional
quiescent supply
current per input
pin
VI = VCC − 2.1 V
other inputs at
VCC or GND;
IO = 0
4.5 to 5.5 −
−
1.35
−
1.5
−
1.5
mA
CI
input capacitance
−
3
10
−
10
−
10
pF
VOL
1999 Sep 29
−
6
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
AC CHARACTERISTICS
Type 74AHC126
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
SYMBOL
Tamb (°C)
PARAMETER
−40 to +85
25
WAVEFORMS
CL
MIN.
−40 to +125
TYP.
MAX. MIN. MAX.
MIN.
MAX.
UNIT
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH
propagation delay
nA to nY
see Figs 5 and 7 15 pF −
4.7
8.0
1.0
9.5
1.0
10.0
ns
tPZH/tPZL
propagation delay
nOE to nY
see Figs 6 and 7
−
5.3
8.0
1.0
9.5
1.0
10.0
ns
tPHZ/tPLZ
propagation delay
nOE to nY
−
6.6
9.7
1.0
11.5
1.0
12.5
ns
tPHL/tPLH
propagation delay
nA to nY
see Figs 5 and 7 50 pF −
6.7
11.5
1.0
13.0
1.0
14.5
ns
tPZH/tPZL
propagation delay
nOE to nY
see Figs 6 and 7
−
7.6
11.5
1.0
13.0
1.0
14.5
ns
tPHZ/tPLZ
propagation delay
nOE to nY
−
9.4
13.2
1.0
15.0
1.0
16.5
ns
VCC = 4.5 to 5.5 V; note 2
tPHL/tPLH
propagation delay
nA to nY
see Figs 5 and 7 15 pF −
3.3
5.5
1.0
6.5
1.0
7.0
ns
tPZH/tPZL
propagation delay
nOE to nY
see Figs 6 and 7
−
3.6
5.3
1.0
6.1
1.0
7.0
ns
tPHZ/tPLZ
propagation delay
nOE to nY
−
4.7
6.8
1.0
8.0
1.0
8.5
ns
tPHL/tPLH
propagation delay
nA to nY
see Figs 5 and 7 50 pF −
4.7
7.5
1.0
8.5
1.0
9.5
ns
tPZH/tPZL
propagation delay
nOE to nY
see Figs 6 and 7
−
5.1
7.6
1.0
8.7
1.0
9.5
ns
tPHZ/tPLZ
propagation delay
nOE to nY
−
6.7
8.8
1.0
10.0
1.0
11.0
ns
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
1999 Sep 29
7
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
Type 74AHCT126
GND = 0 V; tr = tf ≤ 3.0 ns.
Tamb (°C)
TEST CONDITIONS
SYMBOL
−40 to +85
25
PARAMETER
WAVEFORMS
CL
MIN.
−40 to +125
TYP.
MAX. MIN.
MAX.
MIN.
MAX.
UNIT
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH
propagation delay
nA to nY
see Figs 5 and 7 15 pF −
3.0
5.5
1.0
6.5
1.0
7.0
ns
tPZH/tPZL
propagation delay
nOE to nY
see Figs 6 and 7 15 pF −
3.3
5.1
1.0
6.0
1.0
6.5
ns
tPHZ/tPLZ
propagation delay
nOE to nY
15 pF −
4.8
6.8
1.0
8.0
1.0
8.5
ns
tPHL/tPLH
propagation delay
nA to nY
see Figs 5 and 7 50 pF −
4.3
7.5
1.0
8.5
1.0
9.5
ns
tPZH/tPZL
propagation delay
nOE to nY
see Figs 6 and 7 50 pF −
4.7
7.1
1.0
8.0
1.0
9.0
ns
tPHZ/tPLZ
propagation delay
nOE to nY
50 pF −
6.9
8.9
1.0
10.0
1.0
11.5
ns
Note
1. Typical values at VCC = 5.0 V.
AC WAVEFORMS
VI
handbook, halfpage
VM(1)
nA INPUT
GND
tPHL
tPLH
VOH
VM(1)
nY OUTPUT
VOL
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
MNA237
VM(1)
OUTPUT
AHC
GND to VCC
50% VCC
50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
Fig.5 The input (nA) to output (nY) propagation delays.
1999 Sep 29
8
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
VI
handbook, full pagewidth
VM(1)
nOE INPUT
GND
tPLZ
OUTPUT
LOW-to-OFF
OFF-to-LOW
tPZL
VCC
VM(1)
VOL +0.3 V
VOL
tPHZ
tPZH
VOH
VOH −0.3 V
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
VM(1)
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA238
VI INPUT
REQUIREMENTS
FAMILY
VM(1)
INPUT
VM(1)
OUTPUT
AHC
GND to VCC
50% VCC
50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
Fig.6 The 3-state enable and disable times.
S1
handbook, full pagewidth
VCC
PULSE
GENERATOR
VI
1000 Ω
VO
D.U.T.
CL
RT
MNA239
TEST
S1
tPLH/tPHL
open
tPLZ/tPZL
VCC
tPHZ/tPZH
GND
Fig.7 Load circuitry for switching times.
1999 Sep 29
9
VCC
open
GND
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.050
0.028
0.024
0.01
0.01
0.004
0.028
0.012
inches 0.069
0.244
0.039
0.041
0.228
0.016
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06S
MS-012AB
1999 Sep 29
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
10
o
8
0o
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
1999 Sep 29
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
94-07-12
95-04-04
MO-153
11
o
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Sep 29
12
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 29
13
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
NOTES
1999 Sep 29
14
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74AHC126; 74AHCT126
NOTES
1999 Sep 29
15
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Internet: http://www.semiconductors.philips.com
SCA 68
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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Printed in The Netherlands
245002/02/pp16
Date of release: 1999
Sep 29
Document order number:
9397 750 06293