INTEGRATED CIRCUITS DATA SHEET UDA1351H 96 kHz IEC 958 audio DAC Preliminary specification File under Integrated Circuits, IC01 2000 Feb 18 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC UDA1351H CONTENTS 9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 CHARACTERISTICS 12 TIMING CHARACTERISTICS 13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING 15.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 1 FEATURES 1.1 1.2 1.3 1.4 1.5 General Control IEC 958 input Digital output and input interfaces Digital sound processing and DAC 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 16 DEFINITIONS 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.6 8.6.1 8.6.2 8.7 8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 8.7.6 8.7.7 8.7.8 8.7.9 Operating modes Clock regeneration and lock detection Mute Auto mute Data path IEC 958 input Digital data output and input interface Audio feature processor Interpolator Noise shaper The Filter Stream DAC (FSDAC) Control Static pin control mode L3 control mode L3 interface General Device addressing Register addressing Data write mode Data read mode Initialization string Overview of L3 interface registers Writable registers Readable registers 17 LIFE SUPPORT APPLICATIONS 2000 Feb 18 15.2 15.3 15.4 15.5 2 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 1 UDA1351H FEATURES 1.1 General • 2.7 to 3.6 V power supply • Integrated digital filter and Digital-to-Analog Converter (DAC) • Master-mode data output interface for off-chip sound processing • 256fs system clock output 1.5 • 20-bit data-path in interpolator Digital sound processing and DAC • Pre-emphasis information of IEC 958 input bitstream available in L3 interface register and on pins • High performance • No analog post filtering required for DAC • Supports sampling frequencies from 28 up to 100 kHz • Automatic de-emphasis when using IEC 958 input with 32.0, 44.1 and 48.0 kHz audio sample frequencies • The UDA1351H is fully pin and function compatible with the UDA1350AH. • Soft mute by means of a cosine roll-off circuit selectable via pin MUTE or the L3 interface 1.2 • Interpolating filter (fs to 128fs) by means of a cascade of a recursive filter and a FIR filter Control • Controlled either by means of static pins or via the L3 microcontroller interface. • Third-order noise shaper operating at 128fs generates bitstream for the DAC 1.3 • Filter stream digital-to-analog converter. IEC 958 input • On-chip amplifier for converting IEC 958 input to CMOS levels 2 • Selectable IEC 958 input channel, one out of two • Digital audio systems. APPLICATIONS • Lock indication signal available on pin LOCK • Lock indication signal combined on-chip with the Pulse Code Modulation (PCM) status bit; in case non-PCM has been detected pin LOCK indicates out-of-lock 3 The UDA1351H is a single chip IEC 958 audio decoder with an integrated stereo digital-to-analog converter employing bitstream conversion techniques. • Key channel-status bits available via L3 interface (lock, pre-emphasis, audio sample frequency, 2 channel PCM indication and clock accuracy). 1.4 Besides the UDA1351H, which is the full featured version in QFP44 package, there also exists the UDA1351TS. The UDA1351TS has IEC 958 input to the DAC only and is in SSOP28 package. Digital output and input interfaces • When the UDA1351H is clock master of the data output interfaces: The UDA1351H can operate in various operating modes: • IEC 958 input to the DAC including on-chip signal processing – BCKO and WSO signals are output – I2S-bus or LSB-justified 16, 20 and 24 bits formats are supported. • IEC 958 input via the digital data output interface to the external Digital Signal Processor (DSP) • When the UDA1351H is clock slave of the data input interface: • IEC 958 input to the DAC and a DSP • IEC 958 input via a DSP to the DAC including on-chip signal processing – BCK and WS signals are input – I2S-bus or LSB-justified 16, 20 and 24 bits formats are supported. 2000 Feb 18 GENERAL DESCRIPTION • External source data input to the DAC including on-chip signal processing. 3 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC UDA1351H The IEC 958 input audio data including the accompanying pre-emphasis information is available on the output data interface. By default the DAC output and the data output interface are muted when the decoder is out-of-lock. However, this setting can be overruled in the L3 control mode. A lock indication signal is available on pin LOCK indicating that the IEC 958 decoder is locked. 4 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDD digital supply voltage 2.7 3.0 3.6 V VDDA analog supply voltage 2.7 3.0 3.6 V IDDA(DAC) analog supply current of DAC power-on − 8.0 − mA power-down − 750 − µA IDDA(PLL) analog supply current of PLL at 48 kHz − 0.7 − mA at 96 kHz − 1.0 − mA IDDD(C) digital supply current of core IDDD digital supply current P power consumption at 48 kHz power consumption at 96 kHz at 48 kHz − 16.0 − mA at 96 kHz − 24.5 − mA at 48 kHz − 2.0 − mA at 96 kHz − 3.0 − mA DAC in playback mode − 80 − mW DAC in Power-down mode − 58 − mW 109 − mW 87 − mW DAC in playback mode − DAC in Power-down mode − General trst reset active time − 250 − µs Tamb ambient temperature −40 − +85 °C Digital-to-analog converter Vo(rms) output voltage (RMS value) − 900 − mV (THD + N)/S total harmonic distortion-plus-noise to fi = 1.0 kHz tone at 48 kHz signal ratio at 0 dB − −90 −85 dB − −60 −55 dB at 0 dB − −85 −80 dB at −40 dB; A-weighted note 1 at −40 dB; A-weighted fi = 1.0 kHz tone at 96 kHz − −58 −53 dB signal-to-noise ratio at 48 kHz fi = 1.0 kHz tone; code = 0; A-weighted 95 100 − dB signal-to-noise ratio at 96 kHz fi = 1.0 kHz tone; code = 0; A-weighted 95 100 − dB αcs channel separation fi = 1.0 kHz tone − 96 − dB ∆Vo unbalance of output voltages fi = 1.0 kHz tone 0.4 0.1 − dB S/N Note 1. The DAC output voltage is proportionally to the DAC power supply voltage. 2000 Feb 18 4 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 5 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UDA1351H 6 UDA1351H DESCRIPTION QFP44 VERSION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 BLOCK DIAGRAM handbook, full pagewidth VDDA(DAC) CLKOUT VDDA(PLL) VSSA(PLL) TEST1 VDDD(C) VSSD(C) TC 29 32 23 TEST2 RTCB 39 VSSA VDDA 26 44 VOUTL 27 Vref VSSA(DAC) 18 17 25 VOUTR 24 22 31 DAC CLOCK AND TIMING CIRCUIT 34 UDA1351H 2 DAC NOISE SHAPER 4 INTERPOLATOR L3MODE L3CLOCK L3DATA SELSTATIC 10 6 5 L3 INTERFACE AUDIO FEATURE PROCESSOR 12 MUTE 35 SLICER SPDIF0 SPDIF1 SELCHAN VDDD VSSD 15 DATA OUTPUT INTERFACE IEC 958 DECODER 16 DATA INPUT INTERFACE 1 13 43 3 11, 14, 28, 38, 40, 41 21 30 42 33 36 37 8 7 9 19 20 MGL976 n.c. PREEM1 LOCK BCKO WSO DATAO BCKI DATAI PREEM0 Fig.1 Block diagram. 2000 Feb 18 5 SELCLK WSI SELSPDIF RESET Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 7 UDA1351H PINNING PIN TYPE(1) RESET 1 DISD VDDD(C) 2 DS VSSD 3 DGND VSSD(C) 4 DGND digital ground for core L3DATA 5 DIOS L3 interface data input and output L3CLOCK 6 DIS DATAI 7 DISD I2S-bus data input BCKI 8 DISD I2S-bus bit clock input WSI 9 DISD I2S-bus word select input L3MODE 10 DIS n.c. 11 − MUTE 12 DID mute control input SELCHAN 13 DID IEC 958 channel selection input n.c. 14 − not connected SPDIF0 15 AI IEC 958 channel 0 input SPDIF1 16 AI IEC 958 channel 1 input SYMBOL DESCRIPTION reset input digital supply voltage for core digital ground L3 interface clock input L3 interface mode input not connected VDDA(DAC) 17 AS analog supply voltage for DAC VOUTL 18 AO DAC left channel analog output SELCLK 19 DID clock source for PLL selection input SELSPDIF 20 DIU IEC 958 data selection input LOCK 21 DO SPDIF and PLL lock indicator output VOUTR 22 AO DAC right channel analog output TC 23 DID Vref 24 A DAC reference voltage VSSA(DAC) 25 AGND analog ground for DAC VSSA 26 AGND analog ground VDDA 27 AS n.c. 28 − CLKOUT 29 DO test pin; must be connected to digital ground (VSSD) analog supply voltage not connected clock output (256fs) PREEM1 30 DO VSSA(PLL) 31 AGND VDDA(PLL) 32 AS analog supply voltage for PLL BCKO 33 DO I2S-bus bit clock output TEST1 34 DIU test pin 1: must be connected to digital supply voltage (VDDD) SELSTATIC 35 DIU static pin control selection input DATAO 36 DO I2S-bus data output WSO 37 DO I2S-bus word select output n.c. 38 − TEST2 39 DISD n.c. 40 − 2000 Feb 18 IEC 958 input pre-emphasis output 1 analog ground for PLL not connected test pin 2; must be connected to digital ground (VSSD) not connected 6 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC UDA1351H PIN TYPE(1) n.c. 41 − PREEM0 42 DO IEC 958 input pre-emphasis output 0 VDDD 43 DS digital supply voltage RTCB 44 DID test pin; must be connected to digital ground (VSSD) SYMBOL DESCRIPTION not connected Note 1. See Table 1. Table 1 Pin type references PIN TYPE DESCRIPTION DS digital supply DGND digital ground AS analog supply AGND analog ground DI digital input DIS digital Schmitt-triggered input DID digital input with internal pull-down resistor DISD digital Schmitt-triggered input with internal pull-down resistor DIU digital input with internal pull-up resistor DO digital output DIO digital input and output DIOS digital Schmitt-triggered input and output A analog reference voltage AI analog input AO analog output 2000 Feb 18 7 Philips Semiconductors Preliminary specification 36 DATAO 37 WSO 38 n.c. 39 TEST2 40 n.c. 41 n.c. 42 PREEM0 43 VDDD 44 RTCB handbook, full pagewidth 34 TEST1 UDA1351H 35 SELSTATIC 96 kHz IEC 958 audio DAC 33 BCKO RESET 1 VDDD(C) 2 32 VDDA(PLL) VSSD 3 31 VSSA(PLL) VSSD(C) 4 30 PREEM1 L3DATA 5 29 CLKOUT L3CLOCK 6 28 n.c. UDA1351H DATAI 7 27 VDDA BCKI 8 26 VSSA 25 VSSA(DAC) WSI 9 24 Vref L3MODE 10 23 TC Fig.2 Pin configuration. 2000 Feb 18 8 VOUTR 22 LOCK 21 SELCLK 19 SELSPDIF 20 VOUTL 18 SPDIF1 16 VDDA(DAC) 17 SPDIF0 15 n.c. 14 SELCHAN 13 MUTE 12 n.c. 11 MGL977 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8 8.1 FUNCTIONAL DESCRIPTION Operating modes MODE 1 UDA1351H DESCRIPTION SCHEMATIC IEC 958 input to the DAC input IEC 958 DAC CLOCK DSP MGS758 2 IEC 958 input via the data output interface to the DSP input IEC 958 CLOCK DSP MGS759 3 IEC 958 input to the DAC and via the data output interface to the DSP input IEC 958 DAC CLOCK DSP MGS760 4 IEC 958 input via the data output interface to the external DSP and via the data input interface to the DAC input IEC 958 DAC CLOCK DSP MGS761 5 Data input interface signal to the DAC DAC DSP MGS762 The UDA1351H is a low cost multi-purpose IEC 958 decoder DAC with a variety of operating modes. In modes 1, 2, 3 and 4 the UDA1351H is clock master; it generates the clock for both the outgoing and incoming digital data streams. Consequently, any device providing data for the UDA1351H via the data input interface in mode 4 will be slave to the clock generated by the UDA1351H. In mode 5 the UDA1351H locks to signal WSI from the digital data input interface. Conforming to IEC 958, the audio sample frequency of the data input interface must be between 28.0 and 100.0 kHz. 2000 Feb 18 9 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.2 UDA1351H 8.3 Clock regeneration and lock detection Mute The UDA1351H is equipped with a cosine roll-off mute in the DSP data path of the DAC part. Muting the DAC, by pin MUTE (in static mode) or via bit MT (in L3 mode) will result in a soft mute as presented in Fig.3. The cosine roll-off soft mute takes 32 × 32 samples = 24 ms at a sampling frequency of 44.1 kHz. The UDA1351H contains an on-board PLL for regenerating a system clock from the IEC 958 input bitstream or the incoming digital data stream via the data input interface. In addition to the system clock for the on-board digital sound processing the PLL also generates a 256fs clock output for use in the application. In the absence of an input signal the clock will generate a minimum frequency to warrant system functionality. Note: in case of no input signal, the PLL generates a minimum frequency and the output spectrum shifts accordingly. Since the analog output does not have a analog mute, this means noise which is out of band noise under normal operation conditions, can move into the audio band. MGS755 1 handbook, halfpage mute factor 0.8 0.6 When the on-board clock has locked to the incoming frequency the lock indicator bit will be set and can be read via the L3 interface. Internally the PLL lock indication is combined with the PCM status bit of the input data stream. When both the IEC 958 decoder and the on-board clock have locked to the incoming signal and the input data stream is PCM data, then pin LOCK will be asserted. However, when the IC is locked but the PCM status bit reports non-PCM data then pin LOCK is returned to LOW level. 0.4 0.2 0 0 The lock indication output can be used, for example, for muting purposes. The lock signal can be used to drive an external analog muting circuit to prevent out of band noise to become audible in case the PLL runs at its minimum frequency (e.g. when there is no SPDIF input signal). 1 2 t (ms) 3 Fig.3 Mute as a function of raised cosine roll-off. When operating in the L3 control mode the device will mute on start-up. In L3 mode it is necessary to explicitly switch off the mute for audio output by means of the MT bit in the L3 register. In the L3 mode pin MUTE does not have any function (the same holds for several other pins) and can either be left open-circuit (since it has an internal pull-down resistor) or be connected to ground. 2000 Feb 18 10 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.4 UDA1351H The extracted key parameters are: Auto mute • Pre-emphasis By default the outputs of the digital data output interface and the DAC will be muted until the IC is locked, regardless the level on pin MUTE (in static mode) or the state of bit MT of the sound feature register (in L3 mode). In this way only valid data will be passed to the outputs. This mute is done in the SPDIF interface and is a hard mute, not a cosine roll-off mute. • Audio sample frequency • Two-channel PCM indicator • Clock accuracy. Both the lock indicator and the key channel status bits are accessible via the L3 interface. If needed this muting can be bypassed by setting bit AutoMT to logic 0 via the L3 interface. As a result the IC will no longer mute during out-of-lock situations. The UDA1351H supports the following sample frequencies and data bit rates: 8.5 • fs = 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s • fs = 32.0 kHz, resulting in a data rate of 2.048 Mbits/s Data path • fs = 48.0 kHz, resulting in a data rate of 3.072 Mbits/s The UDA1351H data path consists of the slicer and the IEC 958 decoder, the digital data output and input interfaces, the audio feature processor, digital interpolator and noise shaper and the digital-to-analog converters. 8.5.1 • fs = 64.0 kHz, resulting in a data rate of 4.096 Mbits/s • fs = 88.2 kHz, resulting in a data rate of 5.6448 Mbits/s • fs = 96.0 kHz, resulting in a data rate of 6.144 Mbits/s. The UDA1351H supports timing level I, II and III as specified by the IEC 958 standard. IEC 958 INPUT The UDA1351H IEC 958 decoder can select 1 out of 2 IEC 958 input channels. An on-chip amplifier with hysteresis amplifies the IEC 958 input signal to CMOS level (see Fig.4). handbook, halfpage 10 nF 75 Ω SPDIF0, 15, SPDIF1 16 180 pF UDA1351H MGL975 Fig.4 IEC 958 input circuit and typical application. All 24 bits of data for left and right are extracted from the input bitstream as well as several of the IEC 958 key channel-status bits. 2000 Feb 18 11 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.5.2 UDA1351H • Mode selection of the sound processing bass boost and treble filters: flat, minimum and maximum DIGITAL DATA OUTPUT AND INPUT INTERFACE The digital data interface enables the exchange of digital data to and from an external signal processing device. • Soft mute control with raised cosine roll-off The digital output and input formats are identical by design. The possible formats are (see Fig.5): • De-emphasis selection of the incoming data stream for fs = 32.0, 44.1 and 48.0 kHz. • I2S-bus with a word length of up to 24 bits 8.5.4 • LSB-justified with a word length of 16 bits INTERPOLATOR The UDA1351H includes an on-board interpolating filter which converts the incoming data stream from 1fs to 128fs by cascading a recursive filter and a FIR filter. • LSB-justified with a word length of 20 bits • LSB-justified with a word length of 24 bits. Important: the edge of the WS signal must fall on the negative edge of the BCK signal at all times for proper operation of the input and output interface (see Fig.8). Table 2 In the static pin control mode the format is selected by means of pins L3MODE and L3DATA. In the L3 control mode the format defaults to the I2S-bus settings and is programmable via the L3 interface. Interpolator characteristics PARAMETER CONDITIONS VALUE (dB) Pass-band ripple 0fs to 0.45fs ±0.03 >0.65fs −50 0fs to 0.45fs 115 − −3.5 Stop band Dynamic range DC gain The IEC 958 decoder provides the pre-emphasis information from the IEC 958 input bitstream to pins PREEM0 and PREEM1 and to the L3 interface register. 8.5.5 NOISE SHAPER The third-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. Controlling the de-emphasis is different for the 2 modes: • Static pin control mode: – For IEC 958 input de-emphasis is automatically done, but for I2S-bus input de-emphasis is not possible. • L3 control mode: 8.5.6 – IEC 958 input: bit SPDSEL must be set to logic 1 and de-emphasis is done automatically THE FILTER STREAM DAC (FSDAC) The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. – I2S-bus input: bit SPDSEL must be set to logic 0 and de-emphasis can be controlled via bits DE0 and DE1. The audio feature processor automatically provides de-emphasis for the IEC 958 data stream in the static pin control mode and default mute at start-up in the L3 control mode. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. When used in the L3 control mode it provides the following additional features: The output voltage of the FSDAC is scaled proportionally with the power supply voltage. 8.5.3 AUDIO FEATURE PROCESSOR • Volume control using 6 bits • Bass boost control using 4 bits • Treble control using 2 bits 2000 Feb 18 12 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1 2 >=8 3 2 3 MSB B2 1 >=8 BCK DATA MSB B2 MSB I2S-BUS FORMAT WS LEFT Philips Semiconductors 96 kHz IEC 958 audio DAC handbook, full pagewidth 2000 Feb 18 RIGHT LEFT WS RIGHT 16 15 1 16 B15 LSB MSB 2 15 2 1 BCK DATA MSB B2 B2 B15 LSB 13 LSB-JUSTIFIED FORMAT 16 BITS WS LEFT 20 RIGHT 19 18 17 16 15 1 20 B19 LSB MSB 2 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS WS LEFT 24 23 22 21 20 RIGHT 19 18 17 16 15 2 1 24 B23 LSB MSB 23 22 21 20 19 18 17 16 15 2 1 BCK MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB Fig.5 Digital data interface formats. UDA1351H MGS752 LSB-JUSTIFIED FORMAT 24 BITS Preliminary specification DATA Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.6 UDA1351H Control The UDA1351H can be controlled by means of static pins or via the L3 interface. For optimum use of the features of the UDA1351H the L3 control mode is recommended since only basic functions are available in the static pin control mode. It should be noted that the static pin control mode and L3 control mode are mutual exclusive. In the static pin control mode pins L3MODE and L3DATA are used to select the format for the data output and input interface. 8.6.1 STATIC PIN CONTROL MODE The default values for all non-pin controlled settings are identical to the default values at start-up in the L3 control mode. Table 3 Pin description of static pin control mode PIN NAME VALUE FUNCTION Mode selection pin 35 SELSTATIC 1 select static pin control mode; must be connected to VDDD 1 RESET 0 normal operation 1 reset 6 L3CLOCK 0 must be connected to VSSD L3MODE and L3DATA 00 select I2S-bus format for digital data interface 01 select LSB-justified format 16 bits for digital data interface 10 select LSB-justified format 20 bits for digital data interface 11 select LSB-justified format 24 bits for digital data interface 0 normal operation 1 mute active 0 select input SPDIF0 (channel 0) 1 select input SPDIF1 (channel 1) 0 slave to fs from IEC 958; master on data output and input interfaces 1 slave to fs from digital data input interface 0 select data from digital data interface to DAC output 1 select data from IEC 958 decoder to DAC output 0 clock regeneration or IEC 958 decoder out-of-lock or non-PCM data detected 1 clock regeneration and IEC 958 decoder locked plus PCM data detected 00 IEC 958 input: no pre-emphasis Input pins 10 and 5 12 MUTE 13 SELCHAN 19 SELCLK 20 SELSPDIF Status pins 21 LOCK 30 and 42 PREEM1 and PREEM0 01 IEC 958 input: fs = 32.0 kHz with pre-emphasis 10 IEC 958 input: fs = 44.1 kHz with pre-emphasis 11 IEC 958 input: fs = 48.0 kHz with pre-emphasis Test pins 23 TC 0 must be connected to digital ground (VSSD) 34 TEST1 1 must be connected to digital supply voltage (VDDD) 39 TEST2 0 must be connected to digital ground (VSSD) 44 RTCB 0 must be connected to digital ground (VSSD) 2000 Feb 18 14 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.6.2 UDA1351H L3 CONTROL MODE The L3 control mode allows maximum flexibility in controlling the UDA1351H. It should be noted that in the L3 control mode several base-line functions are still controlled by pins on the device and that on start-up in the L3 control mode the output is explicitly muted by bit MT via the L3 interface. Also it should be noted that in using the L3 control mode, an initialization string is needed after power-up of the device for reliable operation. Table 4 Pin description in the L3 control mode PIN NAME VALUE FUNCTION Mode selection pin 35 SELSTATIC 0 select L3 control mode; must be connected to VSDD 1 RESET 0 normal operation 1 reset 5 L3DATA − must be connected to the L3-bus 6 L3CLOCK − must be connected to the L3-bus 10 L3MODE − must be connected to the L3-bus 0 clock regeneration or IEC 958 decoder out-of-lock Input pins Status pins 21 LOCK 30 and 42 PREEM1 and PREEM0 1 clock regeneration and IEC 958 decoder locked 00 IEC 958 input: no-pre-emphasis 01 IEC 958 input: fs = 32.0 kHz with pre-emphasis 10 IEC 958 input: fs = 44.1 kHz with pre-emphasis 11 IEC 958 input: fs = 48.0 kHz with pre-emphasis Test pins 23 TC 0 must be connected to ground (VSSD) 34 TEST1 1 must be connected to supply voltage (VDDD) 39 TEST2 0 must be connected to ground (VSSD) 44 RTCB 0 must be connected to ground (VSSD) 2000 Feb 18 15 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.7 8.7.1 UDA1351H L3 interface Basically 2 types of data transfers can be defined: • Write action: data transfer to the device GENERAL • Read action: data transfer from the device. The UDA1351H has an L3 microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. Remark: when the device is powered up, at least one L3CLOCK pulse must be given to the L3 interface to wake-up the interface before starting sending to the device (see Fig.6). This is only needed once after the device is powered up. The controllable settings are: • Restoring L3 defaults • Power-on 8.7.2 DEVICE ADDRESSING • Selection of input channel, clock source, DAC input and external input format The device address consists of 1 byte with: • Selection of filter mode and settings of treble and bass boost • Bits 0 and 1 (called DOM bits) representing the type of data transfer (see Table 5) • Volume settings • Bits 2 to 7 (address bits) representing a 6-bit device address. • Selection of soft mute via cosine roll-off (only effective in L3 control mode) and bypass of auto mute Table 5 • Selection of de-emphasis. Selection of data transfer DOM The readable settings are: TRANSFER • Mute status of interpolator BIT 0 BIT 1 • PLL locked 0 0 not used • SPDIF input signal locked 1 0 not used • Audio Sample Frequency (ASF) 0 1 write data or prepare read • Valid PCM data detected 1 1 read data • Pre-emphasis of the IEC 958 input signal 8.7.3 • ACcuracy of the Clock (ACC). REGISTER ADDRESSING • L3DATA: data line After sending the device address, including Data Operating Mode (DOM) bits indicating whether the information is to be read or written, 1 data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. • L3MODE: mode line Basically there are 3 methods for register addressing: The exchange of data and control information between the microcontroller and the UDA1351H is LSB first and is accomplished through a serial hardware L3 interface comprising the following pins: • L3CLK: clock line. 1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Fig.6) The exchange of bytes via the L3 interface is LSB first. The L3 format has 2 modes of operation: 2. Addressing for prepare read: bit 0 is logic 1 indicating that data will be read from the register (see Fig.7) • Address mode • Data transfer mode. 3. Addressing for data read action: in this case the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; in case bit 0 is logic 1 the register address is invalid. The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.6). The data transfer mode is characterized by L3MODE being HIGH and is used to transfer one or more bytes representing a register address, instruction or data. 2000 Feb 18 16 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... L3CLOCK L3MODE register address device address 0 L3DATA 1 data byte 1 data byte 2 0 MGS753 DOM bits write Philips Semiconductors 96 kHz IEC 958 audio DAC 2000 Feb 18 L3 wake-up pulse after power-up Fig.6 Data write mode (for L3 version 2). 17 L3CLOCK L3MODE register address device address L3DATA 1 DOM bits read 1 1 register address data byte 1 data byte 2 0/1 valid/non-valid send by the device Fig.7 Data read mode. MGS754 UDA1351H prepare read Preliminary specification 0 1 device address Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.7.4 UDA1351H For reading data from a device, the following 6 bytes are involved (see Table 7): DATA WRITE MODE The data write mode is explained in the signal diagram of Fig.6. For writing data to a device, 4 bytes must be sent (see Table 6): 1. One byte with the device address including ‘01’ for signalling the write action to the device 2. One byte is sent with the register address from which data needs to be read; this byte starts with a ‘1’, which indicates that there will be a read action from the register, followed again by 7 bits for the destination address in binary format with A6 being the MSB and A0 being the LSB 1. One byte starting with ‘01’ for signalling the write action to the device, followed by the device address (‘011000’ for the UDA1351H) 2. One byte starting with a ‘0’ for signalling the write action, followed by 7 bits indicating the destination address in binary format with A6 being the MSB and A0 being the LSB 3. One byte with the device address including ‘11’ is sent to the device; the ‘11’ indicates that the device must write data to the microcontroller 3. Two data bytes with D15 being the MSB and D0 being the LSB. 4. One byte, sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1) Note: each time a new destination register address needs to be written, the device address must be sent again. 8.7.5 DATA READ MODE 5. Two bytes, sent by the device to the bus, with the data information in binary format with D15 being the MSB and D0 being the LSB. For reading data from the device, first a prepare read must be done and then data read. The data read mode is explained in the signal diagram of Fig.7. Table 6 L3 write data FIRST IN TIME BYTE L3 MODE LATEST IN TIME ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 1 address device address 2 data transfer register address 0 A6 A5 A4 A3 A2 A1 A0 3 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 4 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0 Table 7 0 1 0 1 1 0 0 0 L3 read data FIRST IN TIME BYTE L3 MODE LATEST IN TIME ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 1 address device address 0 1 0 1 1 0 0 0 2 data transfer register address 1 A6 A5 A4 A3 A2 A1 A0 3 address device address 1 1 0 1 1 0 0 0 4 data transfer register address 0 or 1 A6 A5 A4 A3 A2 A1 A0 5 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 6 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0 2000 Feb 18 18 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.7.6 UDA1351H INITIALIZATION STRING For proper and reliable operation it is needed that the UDA1351H is initialized in the L3 control mode. This is needed to have the PLL start up after power-up of the device under all conditions. The initialization string is given in Table 8. Table 8 L3 init string and set defaults after power-up. FIRST IN TIME BYTE L3 MODE LATEST IN TIME ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 1 address 2 3 device address 0 1 0 1 1 0 0 0 data transfer register address 0 1 0 0 0 0 0 0 data transfer data byte 1 0 0 0 0 0 0 0 0 4 data transfer data byte 2 0 0 0 0 0 0 1 1 5 address 0 1 0 1 1 0 0 0 6 data transfer register address 0 1 1 1 1 1 1 1 7 data transfer data byte 1 0 0 0 0 0 0 0 0 8 data transfer data byte 2 0 0 0 0 0 0 0 0 2000 Feb 18 init string set defaults device address 19 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... UDA1351H register map BIT ADDR FUNCTION D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DE1 DE0 MT Writable settings 00H 10H 11H 40H system parameters PON CHAN IIS sel sel SPD sel SFOR1 SFOR0 default 1 0 1 0 0 sound features M1 M0 BB3 BB2 BB1 BB0 TR1 TR0 default 0 0 0 0 0 0 0 0 0 0 0 1 volume control DAC VC5 VC4 VC3 VC2 VC1 VC0 default 0 0 0 0 0 0 Auto MT RST PLL 1 0 multiplex parameters 0(1) 20 default 7FH 0(1) 0(1) 0(1) Philips Semiconductors Table 9 OVERVIEW OF L3 INTERFACE REGISTERS 96 kHz IEC 958 audio DAC 2000 Feb 18 8.7.7 restore L3 defaults Readable settings 18H interpolator parameters 38H SPDIF input and lock parameters MT stat PLL lock SPD lock ASF1 ASF0 PCM stat PRE ACC1 ACC0 Note 1. When writing new settings via the L3 interface, these bits should always remain logic 0 (default value) to warrant correct operation. Preliminary specification UDA1351H Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.7.8 UDA1351H Table 13 DAC input selection WRITABLE REGISTERS 8.7.8.1 Restoring L3 defaults SPD sel By writing to the 7FH register, all L3 control values are restored to their default values. Only the L3 interface is affected, the system will not be reset. Consequently readable registers, which are not reset, can be affected. 8.7.8.2 8.7.8.6 A 1-bit value to switch the DAC on and off. input from data input interface 1 input from IEC 958 (default setting) Serial format selection Table 14 Serial format settings Table 10 Power-on setting SFOR1 SFOR0 FUNCTION 0 power-down 1 power-on (default setting) 8.7.8.3 0 A 2-bit value to set the serial format for the digital data output and input interfaces. Power-on PON FUNCTION Slicer input selection FUNCTION 0 0 I2S-bus (default settings) 0 1 LSB-justified, 16 bits 1 0 LSB-justified, 20 bits 1 1 LSB-justified, 24 bits A 1-bit value to select an IEC 958 input channel. 8.7.8.7 Table 11 Slicer input selection A 2-bit value to program the mode for the sound processing filters of bass boost and treble. CHAN sel FUNCTION 0 IEC 958 input from pin SPDIF0 (default setting) 1 IEC 958 input from pin SPDIF1 8.7.8.4 Table 15 Filter mode settings Clock source selection A 1-bit value to select the source for clock regeneration, either from the IEC 958 input or digital data input interface. In the event that the IEC 958 input is used as a clock source the UDA1351H is clock master on the digital data output and input interfaces. slave to audio sampling frequency of IEC 958 input (default setting) 1 slave to audio sampling frequency of digital data input interface 8.7.8.5 FUNCTION 0 0 flat (default setting) 0 1 minimum 1 0 1 1 maximum Treble Table 16 Treble settings LEVEL TR1 DAC input selection A 1-bit value to select the data source, either the IEC 958 input or the digital data input interface. 2000 Feb 18 M0 A 2-bit value to program the treble setting in combination with the filter mode settings. At fs = 44.1 kHz the −3 dB point for minimum setting is 3.0 kHz and the −3 dB point for maximum setting is 1.5 kHz. The default value is ‘00’. FUNCTION 0 M1 8.7.8.8 Table 12 Clock source selection IIS sel Filter mode selection 21 TR0 FLAT (dB) MIN. (dB) MAX. (dB) 0 0 0 0 0 0 1 0 2 2 1 0 0 4 4 1 1 0 6 6 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.7.8.9 UDA1351H Bass boost 8.7.8.11 A 4-bit value to program the bass boost setting in combination with the filter mode settings. At fs = 44.1 kHz the −3 dB point for minimum setting is 250 Hz and the −3 dB point for maximum setting is 300 Hz. The default value is ‘0000’. A 1-bit value to enable the digital mute. Table 19 Soft mute selection MT Table 17 Bass boost settings LEVEL BB3 BB2 BB1 BB0 Soft mute FUNCTION 0 no muting 1 muting (default setting) 8.7.8.12 FLAT (dB) MIN. (dB) MAX. (dB) Volume control A 6-bit value to program the left and right channel volume attenuation. The range is from 0 to −60 dB and −∞ dB in steps of 1 dB. 0 0 0 0 0 0 0 0 0 0 1 0 2 2 0 0 1 0 0 4 4 0 0 1 1 0 6 6 VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB) 0 1 0 0 0 8 8 0 0 0 0 0 0 0 0 1 0 1 0 10 10 0 0 0 0 0 1 0 0 1 1 0 0 12 12 0 0 0 0 1 0 −1 0 1 1 1 0 14 14 0 0 0 0 1 1 −2 1 0 0 0 0 16 16 : : : : : : : 1 0 0 1 0 18 18 1 1 0 0 1 1 1 0 1 0 0 18 20 1 1 0 1 0 0 −51 1 0 1 1 0 18 22 1 1 0 1 0 1 1 1 0 0 0 18 24 1 1 0 1 1 0 1 1 0 1 0 18 24 1 1 0 1 1 1 1 1 1 0 0 18 24 1 1 1 0 0 0 1 1 1 1 0 18 24 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 8.7.8.10 Table 20 Volume settings De-emphasis A 2-bit value to enable the digital de-emphasis filter. Table 18 De-emphasis selection DE1 DE0 0 0 other (default setting) 0 1 fs = 32.0 kHz 1 0 fs = 44.1 kHz 1 1 fs = 48.0 kHz 2000 Feb 18 FUNCTION 22 −52 −54 −57 −60 −∞ Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.7.8.13 UDA1351H Auto mute 8.7.9.2 A 1-bit value to activate mute during out-of-lock. In normal operation the output is automatically hard muted when an out-of-lock situation is detected. Setting this bit to logic 0 will disable that function. A 1-bit value indicating that the clock regeneration is locked. Table 24 PLL lock indication PLL lock Table 21 Auto mute setting Auto MT FUNCTION 0 do not mute output during out-of-lock 1 mute output during out-of-lock (default setting) 8.7.8.14 PLL lock detection FUNCTION 0 out-of-lock 1 locked 8.7.9.3 SPDIF lock detection A 1-bit value indicating the IEC 958 decoder is locked and is decoding correct data. PLL reset A 1-bit value to reset the PLL. This is the bit which is set in the initialization string. When this bit is asserted, the PLL will be reset and the output clock of the PLL will be forced to its lowest value, which is in the area of a few MHz. Table 25 SPDIF lock detection SPD lock FUNCTION 0 not locked or non-PCM data detected 1 locked and PCM data detected Table 22 PLL reset RST PLL 8.7.9 8.7.9.4 FUNCTION 0 normal operation (default) 1 PLL is reset A 2-bit value indicating the audio sample frequency of the IEC 958 input signal. Table 26 Audio sample frequency detection READABLE REGISTERS 8.7.9.1 Mute status A 1-bit value indicating whether the interpolator is muting or not muting. Table 23 Interpolator mute status MT stat FUNCTION 0 no muting 1 muting 2000 Feb 18 Audio sample frequency detection 23 ASF1 ASF0 FUNCTION 0 0 44.1 kHz 0 1 undefined 1 0 48.0 kHz 1 1 32.0 kHz Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 8.7.9.5 UDA1351H PCM detection 8.7.9.7 Clock accuracy detection A 1-bit value which indicates whether the IEC 958 input contains PCM audio data or other binary data. A 2-bit value indicating the timing accuracy of the IEC 958 input signal is conforming to the IEC 958 specification. Table 27 Two-channel PCM input detection Table 29 Input signal accuracy detection PCM stat FUNCTION ACC1 ACC0 FUNCTION 0 input with 2 channel PCM data 0 0 level II 1 input without 2 channel PCM data 0 1 level I 1 0 level III 1 1 undefined 8.7.9.6 Pre-emphasis detection A 1-bit value which indicates whether the pre-emphasis bit was set on the IEC 958 input signal or not set. Table 28 Pre-emphasis detection PRE FUNCTION 0 no pre-emphasis 1 pre-emphasis 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER VDD supply voltage Txtal Tstg CONDITIONS note 1 MIN. MAX. UNIT 2.7 5.0 V crystal temperature −25 +150 °C storage temperature −65 +125 °C Tamb ambient temperature −40 +85 °C Ves electrostatic handling voltage Human Body Model (HBM); note 2 −2000 +2000 V Machine Model (MM) −200 +200 V − 200 mA output short-circuited to VSSA(DAC) − 482 mA output short-circuited to VDDA(DAC) − 346 mA Ilu(prot) latch-up protection current note 3 Isc(DAC) short-circuit current of DAC note 4 Notes 1. All VDD and VSS connections must be made to the same power supply. 2. JEDEC class 2 compliant, except pin VSSA(PLL) which can withstand ESD pulses of −1600 to +1600 V. 3. Latch-up test at Tamb = 125 °C and VDD = 3.6 V. 4. Short-circuit test at Tamb = 0 °C and VDD = 3 V. DAC operation after short-circuiting cannot be warranted. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2000 Feb 18 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 24 VALUE UNIT 63 K/W Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC UDA1351H 11 CHARACTERISTICS VDDD = VDDA = 3.0 V; IEC 958 input with fs = 48.0 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies; note 1 VDDA analog supply voltage 2.7 3.0 3.6 V VDDA(DAC) analog supply voltage for DAC 2.7 3.0 3.6 V VDDA(PLL) analog supply voltage for PLL 2.7 3.0 3.6 V VDDD digital supply voltage 2.7 3.0 3.6 V VDDD(C) digital supply voltage for core IDDA(DAC) analog supply current of DAC IDDA(PLL) analog supply current of PLL IDDD(C) digital supply current of core IDDD P 2.7 3.0 3.6 V power-on − 8.0 − mA power-down − 750 − µA at 48 kHz − 0.7 − mA at 96 kHz − 1.0 − mA at 48 kHz − 16.0 − mA at 96 kHz − 24.5 − mA at 48 kHz − 2.0 − mA at 96 kHz − 3.0 − mA power consumption at 48 kHz DAC in playback mode − 80 − mW DAC in Power-down mode − 58 − mW power consumption at 96 kHz DAC in playback mode − 109 − mW DAC in Power-down mode − 87 − mW digital supply current Digital input pins VIH HIGH-level input voltage 0.8VDD − VDD + 0.5 V VIL LOW-level input voltage −0.5 − +0.2VDD V Vhys(RESET) hysteresis voltage on pin RESET − 0.8 − V ILI input leakage current − − 10 µA Ci input capacitance − − 10 pF Rpu(int) internal pull-up resistance 16 33 78 kΩ Rpd(int) internal pull-down resistance 16 33 78 kΩ Digital output pins VOH HIGH-level output voltage IOH = −2 mA 0.85VDD − − V VOL LOW-level output voltage IOL = 2 mA − − 0.4 V IL(max) maximum load current − 3 − mA Digital-to-analog converter; note 2 Vref reference voltage measured with respect to VSSA 0.45VDDA 0.50VDDA 0.55VDDA V Vo(rms) output voltage (RMS value) note 3 − 2000 Feb 18 25 900 − mV Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC SYMBOL PARAMETER (THD + N)/S total harmonic distortion-plus-noise to signal ratio UDA1351H CONDITIONS MIN. TYP. MAX. UNIT fi = 1.0 kHz tone at 48 kHz at 0 dB − −90 −85 dB at −40 dB; A-weighted − −60 −55 dB at 0 dB − −85 −80 dB at −40 dB; A-weighted − −58 −53 dB fi = 1.0 kHz tone at 96 kHz signal-to-noise ratio at 48 kHz fi = 1.0 kHz tone; code = 0; 95 A-weighted 100 − dB signal-to-noise ratio at 96 kHz fi = 1.0 kHz tone; code = 0; 95 A-weighted 100 − dB αcs channel separation fi = 1.0 kHz tone − 96 − dB ∆Vo unbalance of output voltages fi = 1.0 kHz tone 0.4 0.1 − dB S/N IEC 958 inputs Vi(p-p) AC input voltage (peak-to-peak value) 0.2 0.5 3.3 V Ri input resistance − 6 − kΩ Vhys hysteresis voltage − 40 − mV Notes 1. All supply pins VDD and VSS must be connected to the same external power supply unit. 2. When the DAC must drive a higher capacitive load (above 50 pF), then a series resistor of 100 Ω must be used in order to prevent oscillations in the output stage of the operational amplifier. 3. The output voltage of the DAC is proportional to the DAC power supply voltage. 12 TIMING CHARACTERISTICS VDDD = VDDA = 2.7 to 3.6 V; Tamb = −40 to +85 °C; RL = 5 kΩ; all voltages measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Device reset reset active time trst − 250 − µs PLL lock time time to lock tlock I2S-bus fs = 32.0 kHz − 85.0 − ms fs = 44.1 kHz − 63.0 − ms fs = 48.0 kHz − 60.0 − ms fs = 96.0 kHz − 40.0 − ms Ts = cycle time of sample frequency − − 1⁄ timing (see Fig.8) Tcy(BCK) bit clock cycle time 64Ts s tBCKH bit clock HIGH time 140 − 280 ns tBCKL bit clock LOW time 140 − 280 ns tr rise time − − 20 ns 2000 Feb 18 26 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC SYMBOL PARAMETER UDA1351H CONDITIONS MIN. TYP. MAX. UNIT tf fall time − − 20 ns tsu(WS) set-up time word select 20 − − ns th(WS) hold time word select 10 − − ns tsu(DATAI) set-up time data input 20 − − ns th(DATAI) hold time data input 0 − − ns th(DATAO) hold time data output 0 − − ns td(DATAO-BCK) data output to bit clock delay − − 80 ns td(DATAO-WS) data output to word select delay − − 80 ns 500 − − ns Microcontroller L3 interface timing (see Figs 9 and 10) Tcy(CLK)(L3) L3CLOCK cycle time tCLK(L3)H L3CLOCK HIGH time 250 − − ns tCLK(L3)L L3CLOCK LOW time 250 − − ns tsu(L3)A L3MODE set-up time in address mode 190 − − ns th(L3)A L3MODE hold time in address mode 190 − − ns tsu(L3)D L3MODE set-up time in data transfer mode 190 − − ns th(L3)D L3MODE hold time in data transfer mode 190 − − ns t(stp)(L3) L3MODE stop time in data transfer mode 190 − − ns tsu(L3)DA L3DATA set-up time in address and data transfer mode 190 − − ns th(L3)DA L3DATA hold time in address and data transfer mode 30 − − ns tsu(L3)R L3DATA set-up time in data transfer mode read mode 50 − − ns th(L3)R L3DATA hold time in data transfer mode read mode 360 − − ns 2000 Feb 18 27 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC UDA1351H handbook, full pagewidth WS tr t BCKH t d(DATAO-BCK) t h(WS) tf t su(WS) BCK t BCKL t d(DATAO-WS) Tcy(BCK) t h(DATAO) DATAO t su(DATAI) t h(DATAI) DATAI MGS756 Fig.8 I2S-bus timing of output and input interface. handbook, full pagewidth L3MODE tsu(L3)A th(L3)A tCLK(L3)L tsu(L3)A tCLK(L3)H th(L3)A L3CLOCK Tcy(CLK)(L3) tsu(L3)DA L3DATA th(L3)DA BIT 7 BIT 0 MGL723 Fig.9 Timing for address mode. 2000 Feb 18 28 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC handbook, full pagewidth UDA1351H tstp(L3) tstp(L3) L3MODE tCLK(L3)L Tcy(CLK)L3 tCLK(L3)H tsu(L3)D th(L3)D L3CLOCK th(L3)DA L3DATA write tsu(L3)DA th(L3)DA BIT 7 BIT 0 L3DATA read ten(L3)DA tsu(L3)R Fig.10 Timing for data transfer mode. 2000 Feb 18 tdis(L3)DA MGL889 th(L3)R 29 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... TEST1 X1-27 VDDA L27 C41 100 nF (50 V) X1-26 VSSA X1-2 VDDD(C) X1- 4 VSSD(C) X1-6 L3CLOCK X1-10 L3MODE L3-bus X1-5 VDDD(C) C45 SPDIF1 C5 100 µF (16 V) AGND DGND X1-41 VSSA(DAC) X1-25 X1-40 n.c. VDDA(DAC) X1-17 X1-38 n.c. X1-39 TEST2 n.c. X1-28 n.c. 11 5 14 UDA1351H 35 44 18 22 13 VDDD PREEM1 DATAO X1-30 X1-36 33 7 8 9 R38 1Ω C9 100 µF (16 V) R39 1 kΩ C28 100 nF (50 V) V5 preemphasis indication 19 X1-11 n.c. X1-14 RTCB X1-44 VDDD(C) 3 2 1 X1-23 VDDD(C) 3 2 1 TC VOUTL X1-18 I2S-bus output lock Fig.11 Test and application diagram. I2S-bus input VOUTR X1-22 C15 J26 mute no mute J17 1 RTCB 0 J25 1 TC 0 X18 R44 output left 100 Ω R43 10 kΩ C16 47 µF (16 V) 20 X1-20 SELSPDIF PREEM0 X1-42 37 SELCLK LOCK 36 X1-21 30 VSSD 42 VDDD VDDD(C) 21 WSI 3 3 2 1 n.c. 47 µF (16 V) X1-19 SELCHAN VDDD(C) X1-12 16 BCKI X1-13 VDDD(C) MUTE 15 VDDA VDDD X1-29 10 X1-9 VDDD(C) C40 X13 X19 R46 R45 10 kΩ VDDD(C) 3 2 1 J32 data IEC data I2S-bus VDDD(C) 3 2 1 J31 clock I2S-bus clock IEC output right 100 Ω X14 MGL978 UDA1351H J2 X1-1 Preliminary specification J3 C3 100 µF (16 V) 12 43 J1 RESET C13 10 µF (16 V) 100 nF (50 V) 6 DGND +3 V C44 100 nF (50 V) 4 ground AGND 1 VDDA X1-24 10 nF (50 V) 1 SPDIF0 26 2 23 X1-16 Vref BZN32A07 C14 100 µF (16 V) 27 X1-8 J28 3 SPDIF1 2 25 24 DATAI R42 75 Ω X12 17 X1-7 C49 180 pF (50 V) 41 10 nF (50 V) C46 IEC channel 1 40 WSO X17 SPDIF0 38 BCKO C48 180 pF (50 V) R41 75 Ω X11 X1-15 39 X1-3 IEC channel 0 SELSTATIC 28 X1-33 X16 X1-35 L3DATA 29 C43 100 nF (50 V) 34 X1-43 30 J14 3 static 2 1 L3 32 L29 X1-37 C11 100 µF (16 V) BZN32A07 VDDA 31 CLKOUT X1-31 VSSA(PLL) X1-34 VDDD(C) VDDA(PLL) X1-32 C42 100 nF (50 V) Philips Semiconductors C12 100 µF (16 V) 96 kHz IEC 958 audio DAC BZN32A07 13 APPLICATION INFORMATION L26 VDDA VDDD(C) andbook, full pagewidth 2000 Feb 18 clock output Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC UDA1351H 14 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 10 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT307-2 2000 Feb 18 EUROPEAN PROJECTION 31 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC UDA1351H If wave soldering is used the following conditions must be observed for optimal results: 15 SOLDERING 15.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 15.2 – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.3 15.4 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 2000 Feb 18 Manual soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 32 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC 15.5 UDA1351H Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 16 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 2000 Feb 18 33 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC UDA1351H NOTES 2000 Feb 18 34 Philips Semiconductors Preliminary specification 96 kHz IEC 958 audio DAC UDA1351H NOTES 2000 Feb 18 35 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/25/01/pp36 Date of release: 2000 Feb 18 Document order number: 9397 750 06659