PHILIPS UDA1325

INTEGRATED CIRCUITS
DATA SHEET
UDA1325
Universal Serial Bus (USB) CODEC
Preliminary specification
File under Integrated Circuits, IC01
1999 May 10
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
FEATURES
Audio recording channel
General
• One isochronous input endpoint
• High Quality USB-compliant Audio/HID device
• Supports multiple audio data formats (8, 16 and 24 bits)
• Supports 12 Mbits/s serial data transmission
• Twelve selectable sample rates (4, 8, 16 or 32 kHz;
5.5125, 11.025, 22.05 or 44.1 kHz; 6, 12, 24 or 48 kHz)
via analog PLL (APLL).
• Fully USB Plug and Play operation
• Supports ‘Bus-powered’ and ‘Self-powered’ operation
• 3.3 V power supply
• Selectable sample rate between 5 to 55 kHz via a
second oscillator (optional)
• Low power consumption with optional efficient power
control
• One slave 20-bit I2S digital stereo recording input,
I2S and LSB justified serial formats
• On-chip clock oscillator, only an external crystal is
required.
• Programmable Gain Amplifier for left and right channel
Audio playback channel
• High signal-to-noise ratio (typical 90 dB)
• Low total harmonic distortion (typical 85 dB)
• One stereo Line/Microphone input.
• One isochronous output endpoint
• Supports multiple audio data formats (8, 16 and 24 bits)
USB endpoints
• Adaptive sample frequency support from 5 to 55 kHz
• 2 control endpoints
• One master 20-bit I2S digital stereo playback output,
I2S and LSB justified serial formats
• 2 interrupt endpoints
• 1 isochronous data sink endpoint
• One slave 20-bit I2S digital stereo playback input,
I2S and LSB justified serial formats
• 1 isochronous data source endpoint.
• Selectable volume control for left and right channel
Document references
• Soft mute control
• “USB Specification”
• Digital bass and treble tone control
• “USB Device Class Definition for Audio Devices”
• Selectable on-chip digital de-emphasis
• “Device Class Definition for Human Interface Devices
(HID)”
• Low total harmonic distortion (typical 90 dB)
• High signal-to-noise ratio (typical 95 dB)
• “USB HID Usage Table”.
• One stereo Line output.
1999 May 10
• “USB Common Class Specification”.
2
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
All I2S inputs and I2S outputs support standard I2S-bus
format and the LSB justified serial data format with word
lengths of 16, 18 and 20 bits.
APPLICATIONS
• USB monitors
• USB speakers
Via the digital I/O module with its I2S input and output, an
external DSP can be used for adding extra sound
processing features for the audio playback channel.
• USB microphones
• USB headsets
• USB telephone/answering machines
The microcontroller is responsible for handling the
high-level USB protocols, translating the incoming control
requests and managing the user interface via general
purpose pins and an I2C-bus.
• USB links in consumer audio devices.
GENERAL DESCRIPTION
The ADAC enables the wide and continuous range of
playback sampling frequencies. By means of a Sample
Frequency Generator (SFG), the ADAC is able to
reconstruct the average sample frequency from the
incoming audio samples. The ADAC also performs the
playback sound processing. The ADAC consists of a
FIFO, an unique audio feature processing DSP, the SFG,
digital filters, a variable hold register, a Noise Shaper (NS)
and a Filter Stream DAC (FSDAC) with line output drivers.
The audio information is applied to the ADAC via the USB
processor or via the digital I2S input of the digital I/O
module.
The UDA1325 is a single chip stereo USB codec
incorporating bitstream converters designed for
implementation in USB-compliant audio peripherals and
multimedia audio applications. It contains a USB interface,
an embedded microcontroller, an Analog-to-Digital
Interface (ADIF) and an Asynchronous Digital-to-Analog
Converter (ADAC).
The USB interface consists of an analog front-end and a
USB processor. The analog front-end transforms the
differential USB data into a digital data stream. The USB
processor buffers the incoming and outgoing data from the
analog front-end and handles all low-level USB protocols.
The USB processor selects the relevant data from the
universal serial bus, performs an extensive error detection
and separates control information and audio information.
The control information is made accessible to the
microcontroller. At playback, the audio information
becomes available at the digital I2S output of the digital I/O
module or is fed directly to the ADAC. At recording, the
audio information is delivered by the ADIF or by the digital
I2S input of the I2S-bus interface.
The ADIF consists of an Programmable Gain Amplifier
(PGA), an Analog-to-Digital Converter (ADC) and a
Decimator Filter (DF). An Analog Phase Lock Loop (APLL)
or oscillator is used for creating the clock signal of the
ADIF. The clock frequency for the ADIF can be controlled
via the microcontroller. Several clock frequencies are
possible for sampling the analog input signal at different
sampling rates.
The wide dynamic range of the bitstream conversion
technique used in the UDA1325 for both the playback and
recording channel guarantees a high audio sound quality.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
UDA1325PS
SDIP42
plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
UDA1325H
QFP64
plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm
SOT319-2
1999 May 10
3
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDE
supply voltage periphery
4.75
5.0
5.25
V
VDDI
supply voltage core
3.0
3.3
3.6
V
IDD(tot)
total supply current
−
60
tbf
mA
IDD(tot)(ps)
total supply current in power-saving note 1
mode
−
360
−
µA
−
−90
−80
dB
−
0.0032
0.01
%
−
−30
−20
dB
−
3.2
10
%
95
−
dBA
0.66
−
V
Dynamic performance DAC
(THD + N)/S
total harmonic distortion plus
noise-to-signal ratio
fs = 44.1 kHz; RL = 5 kΩ
fi = 1 kHz (0 dB)
fi = 1 kHz (−60 dB)
S/N
signal-to-noise ratio at bipolar zero
A-weighted at code 0000H 90
Vo(FS)(rms)
full-scale output voltage
(RMS value)
VDD = 3.3 V
−
Dynamic performance PGA and ADC
(THD + N)/S
S/N
total harmonic distortion plus
noise-to-signal ratio
signal-to-noise ratio
fs = 44.1 kHz;
PGA gain = 0 dB
fi = 1 kHz; (0 dB);
Vi = 1.0 V (RMS)
−
−85
−80
dB
−
0.0056
0.01
%
fi = 1 kHz (−60 dB)
−
−30
−20
dB
Vi = 0.0 V
−
3.2
10.0
%
90
95
−
dBA
General characteristics
fi(s)
audio input sample frequency
5
−
55
kHz
Tamb
operating ambient temperature
0
25
70
°C
Note
1. Exclusive the IDDE current which depends on the components connected to the I/O pins.
1999 May 10
4
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
BLOCK DIAGRAM
handbook, full pagewidth
VSSX
24 (19)
XTAL1b
25 (20)
XTAL2b
VDDX
26 (21)
VDDA3
52 (39)
XTAL2a
53 (40)
XTAL1a
54 (41)
VSSA3
55 (42)
GP2/DO
63 (4)
D+
D−
P0.7 to P0.0
P2.0 to P2.7
8 (9)
6 (8)
7, 5, 3, 64,
62, 60, 58, 56
14, 16, 18, 20,
22, 23, 29, 30
OSC
48 MHz
ANALOG FRONT-END
1 (5)
GP4/BCKO
2 (6)
GP1/DI
13 (14)
GP0/BCKI
17 (16)
GP5/WSI
15 (15)
OSC
ADC
DA
57 (1)
59 (2)
BCK
61 (3)
ANALOG
PLL
USB-PROCESSOR
48
ALE
50
VSSI
(12) 11
VSSE
VDDE
(24) 33
VDDO
VSSO
(29) 38
VDDA1
(30) 39
VSSA1
(33) 42
VDDA2
VSSA2
(35) 44
DIGITAL I/O
MUX
(17) 19
SCL
MICROCONTROLLER
(18) 21
SDA
TEST
CONTROL
BLOCK
(26) 35
TC
(27) 36
RTCB
(25) 34
VOUTL
(28) 37
VOUTR
FIFO
SAMPLE
FREQUENCY
GENERATOR
I2S-BUS
INTERFACE
AUDIO FEATURE
PROCESSING DSP
DECIMATOR
FILTER
EA
VDDI
(23) 32
31
WS
(10) 9
(11) 10
(13) 12
TIMING
28 (22)
GP3/WSO
PSEN
CLK
27
(7) 4
UPSAMPLE FILTERS
SHTCB
VARIABLE HOLD REGISTER
VINL
43 (34)
VINR
47 (36)
VRN
49 (37)
VRP
51 (38)
PGA
LEFT
Σ∆ ADC
PGA
RIGHT
Σ∆ ADC
3rd-ORDER NOISE SHAPER
UDA1325
LEFT
DAC
−
+
+
REFERENCE VOLTAGE
45, 46
41 (32)
40 (31)
n.c.
Vref(AD)
Vref(DA)
RIGHT
DAC
The pin numbers given in parenthesis refer to the SDIP42 version.
Fig.1 Block diagram (QFP64 package).
1999 May 10
5
−
MGM108
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
PINNING
PIN
QFP64
PIN
SDIP42
I/O
DESCRIPTION
GP3/WSO
1
5
I/O
general purpose pin 3 or word select output
GP4/BCKO
2
6
I/O
general purpose pin 4 or bit clock output
P0.5
3
−
I/O
Port 0.5 of the microcontroller
SHTCB
4
7
I
P0.6
5
−
I/O
Port 0.6 of the microcontroller
D−
6
8
I/O
negative data line of the differential data bus, conforms to the USB
standard
P0.7
7
−
I/O
Port 0.7 of the microcontroller
D+
8
9
I/O
positive data line of the differential data bus, conforms to the USB
standard
VDDI
9
10
−
digital supply voltage for core
SYMBOL
shift clock of the test control block (active HIGH)
VSSI
10
11
−
digital ground for core
VSSE
11
12
−
digital ground for I/O pads
VDDE
12
13
−
digital supply voltage for I/O pads
GP1/DI
13
14
I/O
general purpose pin 1 or data input
P2.0
14
−
I/O
Port 2.0 of the microcontroller
GP5/WSI
15
15
I/O
general purpose pin 5 or word select input
P2.1
16
−
I/O
Port 2.1 of the microcontroller
GP0/BCKI
17
16
I/O
general purpose pin 0 or bit clock input
P2.2
18
−
I/O
Port 2.2 of the microcontroller
SCL
19
17
I/O
serial clock line I2C-bus
P2.3
20
−
I/O
Port 2.3 of the microcontroller
SDA
21
18
I/O
serial data line I2C-bus
P2.4
22
−
I/O
Port 2.4 of the microcontroller
P2.5
23
−
I/O
VSSX
24
19
−
crystal oscillator ground (48 MHz)
XTAL1b
25
20
I
crystal input (analog; 48 MHz)
XTAL2b
26
21
O
crystal output (analog; 48 MHz)
CLK
27
−
O
48 MHz clock output signal
VDDX
28
22
−
supply crystal oscillator (48 MHz)
P2.6
29
−
I/O
Port 2.6 of the microcontroller
P2.7
30
−
I/O
Port 2.7 of the microcontroller
PSEN
31
−
I/O
program store enable (active LOW)
VDDO
32
23
−
Port 2.5 of the microcontroller
supply voltage for operational amplifier
VSSO
33
24
−
operational amplifier ground
VOUTL
34
25
O
voltage output left channel
TC
35
26
I
test control input (active HIGH)
RTCB
36
27
I
asynchronous reset input of the test control block (active HIGH)
VOUTR
37
28
O
voltage output right channel
1999 May 10
6
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
PIN
QFP64
PIN
SDIP42
I/O
VDDA1
38
29
−
analog supply voltage 1
VSSA1
39
30
−
analog ground 1
Vref(DA)
40
31
O
reference voltage output DAC
Vref(AD)
41
32
O
reference voltage output ADC
VDDA2
42
33
−
analog supply voltage 2
VINL
43
34
I
input signal left channel PGA
VSSA2
44
35
−
analog ground 2
n.c.
45
−
−
not connected
n.c.
46
−
−
not connected
VINR
47
36
I
input signal right channel PGA
EA
48
−
−
external access (active LOW)
VRN
49
37
I
negative reference input voltage ADC
ALE
50
−
−
address latch enable (active HIGH)
VRP
51
38
I
positive reference input voltage ADC
SYMBOL
DESCRIPTION
VDDA3
52
39
−
supply voltage for crystal oscillator and analog PLL
XTAL2a
53
40
O
crystal output (analog; ADC)
XTAL1a
54
41
I
crystal input (analog; ADC)
VSSA3
55
42
−
crystal oscillator and analog PLL ground
P0.0
56
−
I/O
DA
57
1
I
P0.1
58
−
I/O
WS
59
2
I
P0.2
60
−
I/O
BCK
61
3
I
P0.3
62
−
I/O
Port 0.3 of the microcontroller
GP2/DO
63
4
I/O
general purpose pin 2 or data output
P0.4
64
−
I/O
Port 0.4 of the microcontroller
1999 May 10
Port 0.0 of the microcontroller
data Input (digital)
Port 0.1 of the microcontroller
word select Input (digital)
Port 0.2 of the microcontroller
bit clock Input (digital)
7
Philips Semiconductors
Preliminary specification
52 VDDA3
53 XTAL2a
54 XTAL1a
55 VSSA3
56 P0.0
57 DA
UDA1325
58 P0.1
59 WS
60 P0.2
61 BCK
62 P0.3
64 P0.4
handbook, full pagewidth
63 GP2/DO
Universal Serial Bus (USB) CODEC
GP3/WSO 1
51 VRP
GP4/BCKO 2
50 ALE
P0.5 3
49 VRN
SHTCB 4
48 EA
P0.6 5
47 VINR
D− 6
46 n.c.
P0.7 7
45 n.c.
D+ 8
44 VSSA2
VDDI 9
43 VINL
UDA1325H
VSSI 10
42 VDDA2
VSSE 11
41 Vref(AD)
VDDE 12
40 Vref(DA)
GP1/DI 13
39 VSSA1
P2.0 14
38 VDDA1
GP5/WSI 15
37 VOUTR
36 RTCB
P2.1 16
35 TC
GP0/BCKI 17
Fig.2 Pin configuration (QFP64 package).
1999 May 10
8
VDDO 32
PSEN 31
P2.7 30
P2.6 29
VDDX 28
CLK 27
XTAL2b 26
XTAL1b 25
VSSX 24
P2.5 23
33 VSSO
P2.4 22
SCL 19
SDA 21
34 VOUTL
P2.3 20
P2.2 18
MGL349
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
FUNCTIONAL DESCRIPTION
The Universal Serial Bus (USB)
Data and power is transferred via the USB over a 4-wire
cable. The signalling occurs over two wires and
point-to-point segments. The signals on each segment are
differentially driven into a cable of 90 Ω intrinsic
impedance. The differential receiver features input
sensitivity of at least 200 mV and sufficient common mode
rejection.
handbook, halfpage
DA
1
42 VSSA3
WS
2
41 XTAL1a
BCK
3
40 XTAL2a
GP2/DO
4
39 VDDA3
GP3/WSO
5
38 VRP
GP4/BCKO
6
37 VRN
SHTCB
7
36 VINR
The USB processor
D−
8
35 VSSA2
D+
9
34 VINL
The USB processor forms the interface between the
analog front-end, the ADIF, the ADAC and the
microcontroller. The USB processor consists of:
VDDI 10
VSSI 11
The analog front-end
The analog front-end is an on-chip generic USB
transceiver. It is designed to allow voltage levels up to VDD
from standard or programmable logic to interface with the
physical layer of the USB. It is capable of receiving and
transmitting serial data at full speed (12 Mbits/s).
33 VDDA2
• A bit clock recovery circuit
32 Vref(AD)
• The Philips Serial Interface Engine (PSIE)
VSSE 12
31 Vref(DA)
• The Memory Management Unit (MMU)
VDDE 13
30 VSSA1
• The Audio Sample Redistribution (ASR) module.
GP1/DI 14
29 VDDA1
GP5/WSI 15
28 VOUTR
UDA1325
GP0/BCKI 16
Bit clock recovery
The bit clock recovery circuit recovers the clock from the
incoming USB data stream using four times over-sampling
principle. It is able to track jitter and frequency drift
specified by the USB specification.
27 RTCB
SCL 17
26 TC
SDA 18
25 VOUTL
VSSX 19
24 VSSO
Philips Serial Interface Engine (PSIE)
XTAL1b 20
23 VDDO
XTAL2b 21
22 VDDX
The Philips SIE implements the full USB protocol layer.
It translates the electrical USB signals into data bytes and
control signals. Depending upon the USB device address
and the USB endpoint address, the USB data is directed
to the correct endpoint buffer. The data transfer could be
of bulk, isochronous, control or interrupt type.
MGM106
The functions of the PSIE include: synchronization pattern
recognition, parallel/serial conversion, bit
stuffing/de-stuffing, CRC checking/generation, PID
verification/generation, address recognition and
handshake evaluation/generation.
The amount of bytes/packet on all endpoints is limited by
the PSIE hardware to 8 bytes/packet, except for both
isochronous endpoints (336 bytes/packet).
Fig.3 Pin configuration (SDIP42 package).
1999 May 10
9
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Memory Management Unit (MMU) and integrated RAM
The Analog-to-Digital Interface (ADIF)
The MMU and integrated RAM handle the temporary data
storage of all USB packets that are received or sent over
the bus.
The ADIF is used for sampling an analog input signal from
a microphone or line input and sending the audio samples
to the USB interface. The ADIF consists of a stereo
Programmable Gain Amplifier (PGA), a stereo
Analog-to-Digital Converter (ADC) and Decimation Filters
(DFs). The sample frequency of the ADC is determined by
the ADC clock (see Section “The clock source of the
analog-to-digital interface”). The user can also select a
digital serial input instead of an analog input. In this event
the sample frequency is determined by the continuous WS
clock with a range between 5 to 55 kHz. Digital serial input
is possible with four formats (I2S-bus, 16, 18 or 20 bits
LSB-justified).
The MMU and integrated RAM handle the differences
between data rate of the USB and the application allowing
the microcontroller to read and write USB packets at its
own speed.
The audio data is transferred via an isochronous data sink
endpoint or source endpoint and is stored directly into the
RAM. Consequently, no handshaking mechanism is used.
Audio Sample Redistribution (ASR)
The ASR reads the audio samples from the MMU and
integrated RAM and distributes these samples equidistant
over a 1 ms frame period. The distributed audio samples
are translated by the digital I/O module to standard I2S-bus
format or 16, 18 or 20 bits LSB-justified I2S-bus format.
The ASR generates the bit clock output (BCKO) and the
Word Select Output signal (WSO) of the I2S output.
Programmable Gain Amplifier circuit (PGA)
This circuit can be used for a microphone or line input.
The input audio signals can be amplified by seven different
gains (−3 dB, 0 dB, 3 dB, 9 dB, 15 dB, 21 dB and 27 dB).
The gain settings are given in Table 17.
The Analog-to-Digital Converter (ADC)
The 80C51 microcontroller
The stereo ADC of the UDA1325 consists of two 3rd-order
Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 128.
Both ADCs can be switched off in power saving mode (left
and right separate). The ADC clock is generated by the
analog PLL or the ADC oscillator.
The microcontroller receives the control information
selected from the USB by the USB processor. It can be
used for handling the high-level USB protocols and the
user interfaces. The microcontroller does not handle the
audio stream.
The major task of the software process that is mapped
upon the microcontroller, is to control the different modules
of the UDA1325 in such a way that it behaves as a USB
device.
The Decimation Filter (DF)
The decimator filter converts the audio data from 128fs
down to 1fs with a word width of 8, 16 or 24 bits. This data
can be transmitted over the USB as mono or stereo in
1, 2 or 3 bytes/sample. The decimator filters are clocked
by the ADC clock.
The embedded 80C51 microcontroller is compatible with
the 80C51 family of microcontrollers described in the
80C51 family single-chip 8-bit microcontrollers of “Data
Handbook IC20”, which should be read in conjunction with
this data sheet.
The internal ROM size is 12 kbyte. The internal RAM size
is 256 byte. A Watchdog Timer is not integrated.
1999 May 10
10
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
The clock source of the analog-to-digital interface
The clock source of the ADIF is the analog PLL or the ADC oscillator. The preferred clock source can be selected.
The ADC clock used for the ADC and decimation filters is obtained by dividing the clock signal coming from the analog
PLL or from the ADC oscillator by a factor Q.
Using the analog PLL the user can select 3 basic APLL clock frequencies (see Table 1).
By connecting the appropriate crystal the user can choose any clock signal between 8.192 and 14.08 MHz via the ADC
oscillator.
Table 1
The analog PLL clock output frequencies
FCODE (1 AND 0)
APLL CLOCK
FREQUENCY (MHz)
00
11.2896
01
8.1920
10
12.2880
11
11.2896
The dividing factor Q can be selected via the microcontroller. With this dividing factor Q the user can select a range of
ADC clock signals allowing several different sample frequencies (see Table 2).
Table 2
ADC clock frequencies and sample frequencies based upon using the APLL as a clock source
APLL CLOCK
FREQUENCY (MHz)
DIVIDE FACTOR Q
ADC CLOCK FREQUENCY (MHz)
SAMPLE FREQUENCY (kHz)
1
2
4
8
1
2
4
8
1
2
4
8
4.096
2.048
1.024
0.512 (not supported)
5.6448
2.8224
1.4112
0.7056
6.144
3.072
1.536
0.768
32
16
8
4 (not supported)
44.1
22.05
11.025
5.5125
48
24
12
6
8.1920
11.2896
12.2880
Table 3
ADC clock frequencies and sample frequencies based upon using the OSCAD as a clock source
OSCAD CLOCK
FREQUENCY (MHz)
fosc(1)
DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz)
Q(2)
fosc/(2Q)
SAMPLE FREQUENCY (kHz)
fosc/(256Q)(3)
Notes
1. The oscillator frequency (and therefore the crystal) of OSCAD must be between 8.192 and 14.08 MHz.
2. The Q factor can be 1, 2, 4 or 8.
3. Sample frequencies below 5 kHz and above 55 kHz are not supported.
1999 May 10
11
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 4
The Asynchronous Digital-to-Analog Converter
(ADAC)
The ADAC receives audio data from the USB processor or
from the digital I/O-bus. The ADAC is able to reconstruct
the sample clock from the rate at which the audio samples
arrive and handles the audio sound processing. After the
processing, the audio signal is upsampled, noise-shaped
and converted to analog output voltages capable of driving
a line output.
Frequency domains for audio processing by the
DSP
DOMAIN
SAMPLE FREQUENCY (kHz)
1
5 to 12
2
12 to 25
3
25 to 40
4
40 to 55
The ADAC consists of:
The upsampling filters and variable hold function
• A Sample Frequency Generator (SFG)
After the audio feature processing DSP two upsampling
filters and a variable hold function increase the
oversampling rate to 128fs.
• FIFO registers
• An audio feature processing DSP
• Two digital upsampling filters and a variable hold
register
The noise shaper
• A Filter Stream DAC (FSDAC) with integrated filter and
line output drivers.
A 3rd-order noise shaper converts the oversampled data
to a noise-shaped bitstream for the FSDAC. The in-band
quantization noise is shifted to frequencies well above the
audio band.
The Sample Frequency Generator (SFG)
The Filter Stream DAC (FSDAC)
The SFG controls the timing signals for the asynchronous
digital-to-analog conversion. By means of a digital PLL,
the SFG automatically recovers the applied sampling
frequency and generates the accurate timing signals for
the audio feature processing DSP and the upsampling
filters.
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post filter is not needed
because of the inherent filter function of the DAC.
On-board amplifiers convert the FSDAC output current to
an output voltage signal capable of driving a line output.
• A digital Noise Shaper (NS)
The lock time of the digital PLL can be chosen (see
Table 8). While the digital PLL is not in lock, the ADAC is
muted. As soon as the digital PLL is in lock, the mute is
released as described in Section “Soft mute control”.
First-In First-Out (FIFO) registers
The FIFO registers are used to store the audio samples
temporarily coming from the USB processor or from the
digital I/O input. The use of a FIFO (in conjunction with the
SFG) is necessary to remove all jitter present on the
incoming audio signal.
The sound processing DSP
A DSP processes the sound features. The control and
mapping of the sound features is explained in Section
“Controlling the playback features of the ADAC”.
Depending on the sampling rate (fs) the DSP knows four
frequency domains in which the treble and bass are
regulated. The domain is chosen automatically.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
USB ENDPOINT DESCRIPTION
The UDA1325 has following six endpoints:
• USB control endpoint 0
• USB control endpoint 1
• USB status interrupt endpoint 1
• USB status interrupt endpoint 2
• Isochronous data sink endpoint
• Isochronous data source endpoint.
Table 5
Endpoint description
ENDPOINT
NUMBER
0
ENDPOINT
INDEX
0
ENDPOINT TYPE
control (default)
out
in
8
control
out
8
in
8
1
1
2
MAX. PACKET
SIZE (BYTES)
DIRECTION
3
8
2
4
interrupt
in
8
3
5
interrupt
in
8
4
6
isochronous out
out
336
5
7
isochronous in
in
336
CONTROLLING THE PLAYBACK FEATURES
Controlling the playback features of the ADAC
The exchange of control information between the microcontroller and the ADAC is accomplished through a serial
hardware interface comprising the following pins:
L3_DATA: microcontroller interface data line
L3_MODE: microcontroller interface mode line
L3_CLK: microcontroller interface clock line.
See also the description of Port 3 of the 80C51 microcontroller.
Information transfer through the microcontroller bus is organized in accordance with the so-called ‘L3’ format, in which
two different modes of operation can be distinguished; address mode and data transfer mode.
The address mode is required to select a device communicating via the L3-bus and to define the destination registers
for the data transfer mode. Data transfer for the UDA1325 can only be in one direction, from microcontroller to ADAC to
program its sound processing features and other functional features.
ADDRESS MODE
The address mode is used to select a device (in this case the ADAC) for subsequent data transfer and to define the
destination registers. The address mode is characterized by L3_MODE being LOW and a burst of 8 pulses on L3_CLK,
accompanied by 8 data bits on L3_DATA. Data bits 0 and 1 indicate the type of the subsequent data transfer as shown
in Table 6.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
Table 6
UDA1325
Selection of data transfer type
BIT1
BIT0
DATA TRANSFER TYPE
0
0
audio feature registers (volume left, volume right, bass and treble)
0
1
not used
1
0
control registers
1
1
not used
Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the ADAC
is 000101 (bits 7 to 2). In the event that the ADAC receives a different address, it will deselect its microcontroller interface
logic.
DATA TRANSFER MODE
The selection preformed in the address mode remains active during subsequent data transfers, until the ADAC receives
a new address command. The data transfer mode is characterized by L3_MODE being HIGH and a burst of 8 pulses on
L3_CLK, accompanied by 8 data bits. All transfers are bitwise, i.e. they are based on groups of 8 bits. Data will be stored
in the ADAC after the eight bit of a byte has been received. The principle of a multibyte transfer is illustrated in the figure
below.
thalt
ndbook, full pagewidth
L3MODE
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGD018
PROGRAMMING THE SOUND PROCESSING AND OTHER FEATURES
The sound processing and other feature values are stored in independent registers. The first selection of the registers is
achieved by the choice of data transfer type. This is performed in the address mode, bits 1 and 0 (see Table 6).
The second selection is performed by bit 7 and/or bit 6 of the data byte depending of the selected data transfer type.
Data transfer type ‘audio feature registers’
When the data transfer type ‘audio feature registers’ is selected 4 audio feature registers can be selected depending on
bits 7 and 6 of the data byte (see Table 7).
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
Table 7
UDA1325
ADAC audio feature registers
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
REGISTER
0
0
VR5
VR4
VR3
VR2
VR1
VR0
volume right
0
1
VL5
VL4
VL3
VL2
VL1
VL0
volume left
1
0
X
BB4
BB3
BB2
BB1
BB0
bass
1
1
X
TR4
TR3
TR2
TR1
TR0
treble
The sequence for controlling the ADAC audio feature registers via the L3-bus is given in the figure below.
dbook, full pagewidth
DATA_TRANSFER_TYPE
(L3_MODE = LOW)
L3_DATA
0
0
DEVICE ADDRESS = $5
1
0
1
0
0
bit 0
0
bit 7
LEFT VOLUME; TREBLE
RIGHT VOLUME; BASS
REGISTER
ADDRESS
(L3_MODE = HIGH)
L3_DATA
X
X
X
X
X
X
X
X
bit 7
bit 0
L3_CLK
MGS270
Data transfer type ‘control registers’
When the data transfer type ‘control registers’ is selected 2 general control registers can be selected depending on bit 7
of the data byte (see Table 7).
The sequence for controlling the ADAC control registers via the L3-bus is given in the figure below.
DATA_TRANSFER_TYPE
dbook, full pagewidth
DEVICE ADDRESS = $5
(L3_MODE = LOW)
L3_DATA
0
1
1
0
1
0
0
bit 0
0
bit 7
REGISTER
ADDRESS
DATA OF THE CONTROL REGISTER
(L3_MODE = HIGH)
L3_DATA
X
X
X
X
X
X
X
X
bit 7
bit 0
L3_CLK
MGS269
1999 May 10
15
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
Table 8
UDA1325
ADAC general control registers
REGISTER
Control register 0
BIT
DESCRIPTION
VALUE
0
reset ADAC
0 = not reset
1 = reset
1
soft mute control
0 = not muted
1 = mutes
2
synchronous/asynchronous
0 = asynchronous
1 = synchronous
3
channel manipulation
0 = L -> L, R -> R
1 = L -> R, R -> L
4
de-emphasis
0 = de-emphasis off
1 = de-emphasis on
6 and 5 audio mode
7
Control register 1
1 and 0 serial
0
input format
3 and 2 digital PLL mode
4
digital PLL lock mode
6 and 5 digital PLL lock speed
7
select 0
00 = flat mode
01 = min. mode
10 = min. mode
11 = max. mode
selecting bit
I2S-bus
COMMENT
selecting bit
00 = I2S-bus
01 = 16-bit LSB justified
10 = 18-bit LSB justified
11 = 20-bit LSB justified
00 = adaptive
01 = fix state 1
10 = fix state 2
11 = fix state 3
select 00
0 = adaptive
1 = fixed
select 1
00 = lock after 512 samples
01 = lock after 2048 samples
10 = lock after 4096 samples
11 = lock after 16348 samples
select 00
1
Soft mute control
When the mute (bit 1 of control register 0) is active for the playback channel, the value of the sample is decreased
smoothly to zero following a raised cosine curve. There are 32 coefficients used to step down the value of the data, each
one being used 32 times before stepping to the next. This amounts to a mute transition of 23 ms at fs = 44.1 kHz. When
the mute is released, the samples are returned to the full level again following a raised cosine curve with the same
coefficients being used in reversed order.
The mute, on the master channel is synchronized to the sample clock, so that operation always takes place on complete
samples.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Volume control
The volume of the UDA1325 can be controlled from 0 dB down to −60 dB (in steps of 1 dB). Below −60 dB the audio
signal is muted (−∞ dB). The setting of 0 dB is always referenced to the maximum available volume setting. Independant
volume control of the left and right channel is possible (balance control).
Table 9
Volume settings right playback channel
VR5
VR4
VR3
VR2
VR1
VR0
VOLUME (dB)
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
−1
0
0
0
0
1
1
−2
0
0
0
1
0
0
−3
...
...
...
...
...
...
...
1
1
1
1
0
0
−59
1
1
1
1
0
1
−60
1
1
1
1
1
0
−∞
1
1
1
1
1
1
−∞
Table 10 Volume settings left playback channel
VL5
VL4
VL3
VL2
VL1
VL0
VOLUME (dB)
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
−1
0
0
0
0
1
1
−2
0
0
0
1
0
0
−3
...
...
...
...
...
...
...
1
1
1
1
0
0
−59
1
1
1
1
0
1
−60
1
1
1
1
1
0
−∞
1
1
1
1
1
1
−∞
1999 May 10
17
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Treble control
For the playback channel, treble can be regulated in three audio modes: minimum, flat and maximum mode. In flat mode
the audio is not influenced. In minimum and maximum mode, the treble range is from 0 to 6 dB in steps of 2 dB.
The programmable treble filter is implemented digitally and has a fixed corner frequency of 3000 Hz for the minimum
mode and 1500 Hz for the maximum mode. Because of the exceptional amount of programmable gain, treble should be
used with adequate prior attenuation, using volume control.
Table 11 Treble settings
TREBLE (dB)
TR4
TR3
TR2
TR1
TR0
FLAT SET
MIN. SET
MAX. SET
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
2
2
0
0
1
0
1
0
2
2
0
0
1
1
0
0
2
2
0
0
1
1
1
0
2
2
0
1
0
0
0
0
4
4
0
1
0
0
1
0
4
4
0
1
0
1
0
0
4
4
0
1
0
1
1
0
4
4
0
1
1
0
0
0
6
6
0
1
1
0
1
0
6
6
0
1
1
1
0
0
6
6
0
1
1
1
1
0
6
6
...
...
...
...
...
0
6
6
1
1
1
1
1
0
6
6
Bass control
For the playback channel, bass can be regulated in three audio modes: minimum, flat and maximum mode. In flat mode
the audio is not influenced. In minimum mode the bass range is from 0 to approximately 14 dB in steps of 1.5 dB.
In maximum mode, the bass range is from 0 to approximately 24 dB in steps of 2 dB. The programmable bass filters are
implemented digitally and have a fixed corner frequency of 100 Hz for the minimum mode and 75 Hz for the maximum
mode. Because of the exceptional amount of programmable gain, bass should be used with adequate prior attenuation,
using volume control.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 12 Bass boost settings
BASS (dB)
BB4
BB3
BB2
BB1
BB0
FLAT SET
MIN. SET
MAX. SET
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1.1
1.7
0
0
1
0
1
0
1.1
1.7
0
0
1
1
0
0
2.4
3.6
0
0
1
1
1
0
2.4
3.6
0
1
0
0
0
0
3.7
5.4
0
1
0
0
1
0
3.7
5.4
0
1
0
1
0
0
5.2
7.4
0
1
0
1
1
0
5.2
7.4
0
1
1
0
0
0
6.8
9.4
0
1
1
0
1
0
6.8
9.4
0
1
1
1
0
0
8.4
11.3
0
1
1
1
1
0
8.4
11.3
1
0
0
0
0
0
10.2
13.3
1
0
0
0
1
0
10.2
13.3
1
0
0
1
0
0
11.9
15.2
1
0
0
1
1
0
11.9
15.2
1
0
1
0
0
0
13.7
17.3
1
0
1
0
1
0
13.7
17.3
1
0
1
1
0
0
13.7
19.2
1
0
1
1
1
0
13.7
19.2
1
1
0
0
0
0
13.7
21.2
1
1
0
0
1
0
13.7
21.2
1
1
0
1
0
0
13.7
23.2
1
1
0
1
1
0
13.7
23.2
...
...
...
...
...
0
13.7
23.2
1
1
1
1
1
0
13.7
23.2
De-emphasis
De-emphasis is controlled by bit 4 of control register 0. The de-emphasis filter can be switched on or off. The digital
de-emphasis filter is dimensioned to produce the de-emphasis frequency characteristics for the sample rate 44.1 kHz.
De-emphasis is synchronized to the sample clock, so that operation always takes place on complete samples.
1999 May 10
19
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Filter characteristics playback channel
The overall filter characteristic of the UDA1325 in flat mode is given in Fig.4 (de-emphasis off). The overall filter
characteristic of the UDA1325 includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the
FSDAC (fs = 44.1 kHz)
handbook, full pagewidth
MGM110
−0
−20
volume
(dB)
−40
−60
−80
−100
−120
−140
−160
0
10
20
30
40
50
60
70
80
90
f (kHz)
Fig.4 Overall filter characteristics of the UDA1325.
1999 May 10
20
100
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
DSP extension port for enhanced playback audio processing
An external DSP can be used for adding extra sound processing features via the I2S inputs and outputs of the digital I/O
module. The UDA1325 supports the standard I2S-bus data protocol and the LSB-justified serial data input format with
word lengths of 16, 18 and 20 bits. Using the 4-pin digital I/O option the UDA1325 device acts as a master, controlling
the BCKO and WSO signals. Using the 6-pin digital I/O option GP2, GP3 and GP4 are output pins (master) and GP0,
GP1 and GP5 are input pins (slave).
The period of the WSO signal is determined by the number of samples in the 1 ms frame of the USB. This implies that
the WSO signal does not have a constant time period, but is jittery.
The characteristic timing of the I2S-bus signals is illustrated in Figs 5 and 6.
LEFT
handbook, full pagewidth
WS
RIGHT
tr
tBCK(H)
tf
ts;WS
th;WS
tBCK(L)
BCK
Tcy
ts;DAT
th;DAT
DATA
LSB
MSB
MGK003
Fig.5 Timing of digital I/O input signals.
1999 May 10
21
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2
RIGHT
>=8
3
1
2
>=8
3
BCK
DATA
MSB
B2
LSB MSB
B2
LSB MSB
INPUT FORMAT I2S-BUS
WS
RIGHT
LEFT
16
15
1
16
B15 LSB
MSB
2
15
2
1
BCK
MSB
DATA
B2
B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
22
WS
RIGHT
LEFT
18
Philips Semiconductors
1
Universal Serial Bus (USB) CODEC
book, full pagewidth
1999 May 10
LEFT
WS
17
16
15
2
1
18
B17
LSB
MSB
17
16
15
2
1
B17
LSB
2
1
BCK
DATA
MSB
B2
B3
B4
B2
B3
B4
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
20
19
18
RIGHT
17
16
15
2
1
20
B19
LSB
MSB
19
18
17
16
15
BCK
MSB
B2
B3
B4
B5
B6
B2
B3
B4
B5
B6
B19
LSB
MGK002
LSB-JUSTIFIED FORMAT 20 BITS
UDA1325
Fig.6 Input formats.
Preliminary specification
DATA
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
PORT DEFINITION 80C51
Port 1
Table 13 Port 1 of the 80C51 microcontroller
8 BIT PORT 1
BIT
FUNCTION
1.0
ADAC_error
1.1
GP1
1.2
GP2
1.3
GP3
1.4
GP4
1.5
GP5
1.6
SCL
1.7
SDA
LOW
HIGH
no error
COMMENT
error
general purpose pins
I2C-bus
Port 3
Table 14 Port 3 of the 80C51 microcontroller
8 BIT PORT 3
BIT
FUNCTION
LOW
HIGH
COMMENT
3.0
ASR_error
no error
error
3.1
PSIE_MMU_SUSPEND
no suspend
suspend
3.2
GP0 (INT0_N)
general purpose pin
3.3
PSIE_MMU_INT (INT1_N)
interrupt input from USB interface
during normal operation or input from
restart circuit
3.4
PSIE_MMU_READY
3.5
L3_MODE
3.6
L3_CLK
3.7
L3_DATA
1999 May 10
23
suspend input from USB interface
during normal operation or input from
restart circuit
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
MEMORY AND REGISTER SPACE 80C51
ADDRESS
Overview registers
REGISTER
RESET
VALUE
Port registers
Table 15 Register location and recommended values
after Power-on reset
ADDRESS
REGISTER
80h
P0
FFh
RESET
VALUE
90h
P1
FFh
A0h
P2
FFh
B0h
P3
FFh
0800h
PGA gain
09
0801h
ADIF control
5C
1000h
clock shop settings
00
1001h
reset control and APLL settings
00
1002h
IO selection register
01
1003h
power control
00
2000h
ASR settings
8B
4000h
data register PSIE
Interrupts
4001h
command register PSIE
The UDA1325 supports up to five (of maximal 7) interrupt
sources. Each interrupt source corresponds to an interrupt
vector in the CPU program memory address space:
I2C registers (SIO1 registers)
Table 16 Special function register location
ADDRESS
REGISTER
D8h
S1CON
D9h
S1STA
DAh
S1DAT
DBh
S1ADR
00h
Source 0: vector 0003h external interrupt 0 (INT0_N)
RESET
VALUE
Source 1: vector 000Bh Timer 0 interrupt
Source 2: vector 0013h external interrupt 1 (INT1_N)
CPU registers
81h
SP
Source 3: vector 001Bh Timer 1 interrupt
82h
DPL
Source 4: vector 0023h UART interrupt (not present)
83h
DPH
Source 5: vector 002Bh Timer 2 interrupt (not present)
D0h
PSW
Source 6: vector 0033h I2C interrupt.
E0h
ACC
F0h
B
INTERRUPT ENABLE REGISTER (IE)
Each interrupt source can be individually enabled or
disabled by setting or clearing a bit in IE. This register also
contains a global interrupt enable bit (EA) which can be
cleared to disable all interrupts at once.
Interrupt registers
A8h
IE
00h
B8h
IP
00h
Timer 0 and Timer 1 registers
7
88h
T01CON
00h
89h
T01MOD
00h
8Ah
T0L
00h
8Bh
T1L
00h
8Ch
T0h
00h
8Dh
T1h
00h
0
1999 May 10
PCON
0
5
0
4
0
3
0
2
0
1
0
0
0
Power On Value
EX0 (vector 0003h))
ET0 (vector 000Bh))
EX1 (vector 0013h)
ET1 (vector 001Bh)
ES0 (n.a.)
ET2 (n.a.)
ES1 (vector 0033h)
EA
PCON registers
87h
6
00h
24
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Internal registers
Table 17 PGA gain registers
ADDRESS
0800h
REGISTER
PGA gain register
COMMENTS
reserved
PGA input selection
BIT
VALUE
7
X
6
0 (do not change it)
PGA gain right channel
5, 4 and 3 000 = −3 dB
001 = 0 dB
010 = 3 dB
011 = 9 dB
100 = 15 dB
101 = 21 dB
110 = 27 dB
111 = 27 dB
PGA gain left channel
2, 1 and 0 000 = −3 dB
001 = 0 dB
010 = 3 dB
011 = 9 dB
100 = 15 dB
101 = 21 dB
110 = 27 dB
111 = 27 dB
Table 18 ADIF control registers
ADDRESS
0801h
REGISTER
ADIF control register
COMMENTS
reserved
BIT
7
number of bits per audio sample
to be transmitted to the host
6 and 5
VALUE
X
00 = reserved
01 = 8 bits audio samples
10 = 16 bits audio samples
11 = 24 bits audio samples
mono/stereo selection
4
selection audio input recording
channel
3
selection high-pass filter of
ADIF (DC-filter)
2
0 = mono
1 = stereo
I2S-bus input serial input format
recording channel
0 = digital serial audio input
1 = analog input
0 = high-pass filter off
1 = high-pass filter on
1 and 0
00 = I2S-bus
01 = 16-bit LSB justified
10 = 18-bit LSB justified
11 = 20-bit LSB justified
1999 May 10
25
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 19 Clock shop register
ADDRESS
1000h
REGISTER
clock shop settings
COMMENTS
selection ADC clock source
BIT
7
VALUE
0 = ADC clock from APLL
1 = ADC clock from OSCAD
divide factor Q
6 and 5
00 = ADC clock divided-by-1
01 = ADC clock divided-by-2
10 = ADC clock divided-by-4
11 = ADC clock divided-by-8
clock ADAC
4
0 = enable
1 = disable
clock 48 MHz internal
3
0 = enable
1 = disable
clock recovered by PSIE
2
0 = enable
1 = disable
ADC clock
1
0 = enable
1 = disable
OSCAD oscillator
0
0 = power on
1 = power off
Table 20 Reset control and APLL register
ADDRESS
REGISTER
COMMENTS
BIT
1001h
reset control and APLL
settings
fcode (1 and 0)
clock frequency selection APLL
7 and 6
1999 May 10
VALUE
00 = 256 × 44.1 kHz
01 = 256 × 32 kHz
10 = 256 × 48 kHz
11 = 256 × 44.1 kHz
reserved
5
X
reset ADAC
4
0 = reset off
1 = reset on
reset MMU
3
0 = reset off
1 = reset on
reset digital I/O-interface
2
0 = reset off
1 = reset on
reset ADIF
1
0 = reset off
1 = reset on
reserved
0
X
26
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 21 I/O selection register
ADDRESS
1002h
REGISTER
I/O selection register
COMMENTS
microcontroller control on
48 MHz oscillator
BIT
7
VALUE
0 = UPC control disabled
(48 MHz oscillator is enabled)
1 = UPC control enabled
audio format
6 and 5
00 = 4-pins I2S
01 = 6-pins I2S
10 = 3-pins I2S (only input)
11 = 3-pins I2S (only input)
GP4 I/O if BIT0 = 1
4
0 = output
1 = input
GP3 I/O if BIT0 = 1
3
0 = output
1 = input
GP2 I/O if BIT0 = 1
2
0 = output
1 = input
GP1 I/O if BIT0 = 1
1
0 = output
1 = input
GP4 to GP1 function
0
0 = I2S usage
1 = general purpose usage
Table 22 Power control register
ADDRESS
1003h
1999 May 10
REGISTER
power control register
analog modules
COMMENTS
BIT
VALUE
suspend input selection for P3.1
of the microcontroller
7
0 = suspend from USB interface
connected to P3.1 during
normal operation
1 = suspend from restart circuit
connected to P3.1 (e.g. after
power-down)
interrupt input selection for
P3.3 (INT1_N) of the
microcontroller
6
0 = interrupt from USB
interface connected to P3.3
during normal operation
1 = interrupt from restart circuit
connected to P3.3 (e.g. after
power-down)
power APLL
5
0 = power on
1 = power off
power FSDAC
4
0 = power on
1 = power off
power ADC left
3
0 = power on
1 = power off
power ADC right
2
0 = power on
1 = power off
power PGA left
1
0 = power on
1 = power off
power PGA right
0
0 = power on
1 = power off
27
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 23 ASR control register
ADDRESS
2000h
REGISTER
ASR control register
COMMENTS
robust word clock
BIT
7
serial I2S-bus output format
digital I/O interface
6 and 5
VALUE
0 = off (not recommended)
1 = on (recommended)
00 = I2S-bus
01 = 16-bit LSB justified
10 = 18-bit LSB justified
11 = 20-bit LSB justified
phase inversion (on right mono
output)
bits per sample modi
4
0 = mono phase inversal off
1 = mono phase inversal on
3 and 2
00 = reserved
01 = 8-bit audio
10 = 16-bit audio
11 = 24-bit audio
mono or stereo operation
1
ASR register start-up mode
0
0 = mono
1 = stereo
0 = stop (e.g. at alternate
setting with bandwidth equal to
zero)
1 = go
START-UP BEHAVIOUR AND POWER MANAGEMENT
Start-up of the UDA1325
After power-on (of VDDA1), an internal Power-on reset signal becomes HIGH after a certain RC time. This RC time is
created by using the internal resistor (2 × 50 kΩ) divider for creating the reference voltage for the FSDAC in combination
with the capacitor connected externally to the VREFDA pin. The FSDAC and the internal resistor divider are supplied by
VDDA1 and VSSA1. The RC time can be calculated using R = 25000 Ω and C = Cref.
During 20 ms after Power-on reset becomes HIGH the UDA1325 has to initiate the internal registers. During this
initialisation, the user should prevent indicating the ‘connected’ status to the USB-host. This can be done by forcing the
DP-line LOW (i.e. via one of the GP pins).
Power Management
The total current drawn from the USB supply (for i.e. bus-powered operation of the UDA1325 application) must be less
than 500 µA in suspend mode. In order to reach that low current target, the total power dissipation of the UDA1325 can
be reduced by disabling all internal clocks and switching off all internal analog modules.
Important note: In order to make use of power reduction (Power-down mode) and be able to restart after power-down, a
number of precautions must be taken!
1999 May 10
28
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
AT INITIALISATION TIME
• Bit 7of the power control register (mux_ctrl_suspend) must be set to ‘1’, in order to connect the CLK_ON of the USB
processor with P3.1 of the microcontroller
• Bit 6 of the power control register (mux_ctrl_int1) must be set to ‘0’, in order to connect the PSIE_MMU_INT output pin
of the USB processor with P3.3 (INT1_N) of the microcontroller
• Bit 7of the I/O selection register must be set to ‘1’, in order to enable the power-on control of the 48 MHz crystal
oscillator automatically by the microcontroller.
IN NORMAL OPERATION MODE
In normal operation working mode, a suspend can be initiated by the falling edge of the CLK_ON output signal of the
USB processor. This falling edge comes about 2 ms after the rising edge of the PSIE_MMU_SUSPEND output signal of
the USB processor. At this moment, several actions should be taken by the microcontroller:
• All analog modules of the UDA1325 must be switched off; this can be done by setting bits 5 to 0 of the power control
register to ‘1’ and bit 0 of the clock shop register to ‘1’
• Bit 6 of the power control register (mux_ctrl_int1) must be set to ‘1’, in order to awake from power-down by the
CLK_ON signal of the USB processor
• Put all GP pins in the high or low state (depending of how they are used in the UDA1325 application)
• Put the microcontroller in Power-down mode. This can be done via the PCON register of the microcontroller. This
results in an automatically switching off the 48 MHz crystal oscillator and with that all internal clocks (if they are
enabled).
On the rising edge of the CLK_ON output signal, the 48 MHz crystal oscillator will be switched on automatically and with
that all internal clocks (if they are enabled). At the same time, a counter starts counting for 2048 clock cycles (170 µs).
This time is necessary for stabilising the 48 MHz clock of the 48 MHz crystal oscillator.
When the counter reaches its end value (after 2048 cycles), a rising edge will be detected on the P3.3 (INT1_N) of the
microcontroller. At this moment, following actions should be taken by the microcontroller:
• The Power-down mode of the microcontroller must be switched off
• Re-initialise all GP pins
• All analog modules of the UDA1325 must be switched on; this can be done by setting bits 5 to 0 of the power control
register to ‘0’ and bit 0 of the clock shop register to ‘0’
• Bit 6 of the power control register (mux_ctrl_int1) must be set to ‘0’, in order to connect the PSIE_MMU_INT output pin
of the USB processor again with P3.3 (INT1_N) of the microcontroller.
The UDA1325 is now back in its normal operation mode and can be put back in power reduction mode by the falling edge
of the CLK_ON signal of the USB processor.
1999 May 10
29
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
COMMAND SUMMARY
COMMAND NAME
RECIPIENT
CODING
DATA PHASE
Initialization commands
Set address/enable
device
D0h
write 1 byte
Read address/enable
device
D0h
read 1 byte
Set endpoint enable
device
D8h
write 1 byte
Read endpoint enable
device
D8h
read 1 byte
Set mode
device
F3h
write 1 byte
Read interrupt register
device
F4h
read 1 byte
Select endpoint
control OUT
00h
read 1 byte (optional)
control IN
01h
read 1 byte (optional)
other endpoints
00h + endpoint index
read 1 byte (optional)
control OUT
40h
read 1 byte
control IN
41h
read 1 byte
Data flow commands
Get endpoint status
Set endpoint status
other endpoints
40h + endpoint index
read 1 byte
control OUT
40h
write 1 byte
control IN
41h
write 1 byte
other endpoints
40h + endpoint index
write 1 byte
Read buffer
selected endpoint
F0h
read n bytes
Write buffer
selected endpoint
F0h
write n bytes
Acknowledge setup
selected endpoint
F1h
none
Clear buffer
selected endpoint
F2h
none
Validate buffer
selected endpoint
FAh
none
F5h
read 1 or 2 bytes
General commands
Read current frame number
1999 May 10
30
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
COMMAND DESCRIPTIONS
Table 24
Command procedure
BIT
This chapter describes the commands that can be used by
the microcontroller to control the USB processor. There
are three basic types of commands:
DESCRIPTION
Address
the value written becomes
the device address
Enable
a ‘1’ enables this function
• Initialization commands
• Data flow commands
READ ADDRESS/ENABLE
• General commands.
Command: D0h.
A command is represented by an 8 bit code. It can be
followed by one or more data write cycles or one or more
read cycles or a combination. The PSIE_MMU_READY
output connected to Port 3.4 of the microcontroller
indicates that the previous action (command write, data
read or data write) has completed. A new action can only
be initiated if PSIE_MMU_READY is TRUE. The data is
valid from the moment PSIE_MMU_READY becomes
TRUE.
Data: read 1 byte.
The PSIE contains a number of interrupt registers, one for
each endpoint. Every time a transition occurs, the interrupt
flag for the involved endpoint is set. The PSIE_MMU_INT
connected to Port 3.3 is an OR function of all interrupt
registers.
Data: write 1 byte.
The read address/enable command is used to read the
USB assigned address and the enable bit of the device.
The format of the data phase is the same as for the set
address/enable command.
SET ENDPOINT ENABLE
Command: D8h.
The set endpoint enable command is used to set the
enable bits for the non default endpoints.
Initialization commands
Command: D0h.
0
0
0
0
3
2
1
X
X
X
X
X
X
X
0
Power On Value
3
0
2
0
1
0
Command: D8h.
Data: read 1 byte.
The read endpoint enable command is used to read the
enable bit for the non default endpoints of the function.
The format of the data phase is the same as for the set
endpoint enable command.
0
0
Power On Value
Address
Enable
SET MODE
Command: F3h.
Data: write 1 byte.
1999 May 10
0
READ ENDPOINT ENABLE
The set address/enable command is used to set the USB
assigned address and enable the function. The device
always powers up disabled and should be enabled after a
bus reset.
4
4
After bus reset, the enable bit is set to ‘0’.
Data: write 1 byte.
5
5
If the enable bit is ‘1’, the non default endpoints are
enabled, if ‘0’, the non default endpoints are disabled.
The function then only responds to the default control
endpoint.
SET ADDRESS/ENABLE
6
6
Enable
Reserved
Initialization commands are used during the enumeration
process of the USB network. They are used to set the USB
assigned address, enable endpoints and select the
configuration of the device.
7
7
31
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
7
6
5
4
3
2
1
UDA1325
An interrupt is also generated after a bus reset. When the
interrupt register consists of all zeros, and an interrupt was
generated, there was a bus reset. The interrupt is cleared
when the interrupt register is read.
0
0
0
1
1
1
1
1
1
T
T
F
F
T
T
T
T
Reset value
Bus Reset
IsoOut
IsoIn
IntIsoOut
IntIsoIn
ErrorDebugMode
AlwaysPLLClock
Reserved
Reserved
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
Power On Value
Control OUT
Control IN
Endpoint 1 OUT
Endpoint 1 IN
Endpoint 2 IN
Endpoint 3 IN
Endpoint 4 OUT
Endpoint 5 IN
Reset value: gives the value of the bits after Power-on
reset. Bus reset: a ‘F’ indicates that the value of the bit is
not changed during a bus reset. a ‘T’ indicates that during
a bus reset, the bit is reset to its reset value.
SELECT ENDPOINT
Table 25
Command: 00h + endpoint index.
BIT
IsoOut
ISO out endpoint can be
used
IsoIn
ISO in endpoint can be
used
IntIsoOut
allow interrupt from ISO
out endpoint
IntIsoIn
allow interrupt from ISO in
endpoint
ErrorDebugMode
AlwaysPLLClock
Data: optional read 1 byte.
DESCRIPTION
The select endpoint command initializes an internal
pointer to the start of the selected buffer. Optionally, this
command can be followed by a data read. Bit 0 is low if the
buffer is empty and high if the buffer is full. There is one
command for every endpoint.
7
6
5
4
3
2
1
X
X
X
X
X
X
X
0
0
Setting chip in debug
mode
Power On Value
Full/Empty
Reserved
the PLL clock must keep
on running
GET ENDPOINT STATUS
Data flow commands
Command: 40h + endpoint index.
Data flow commands are used to manage the data
transmission between the USB endpoints and the host.
Much of the data flow is initiated via the interrupt to the
microcontroller. The microcontroller uses these
commands to access the endpoint buffers and determine
whether the endpoint buffers have valid data.
Data: read 1 byte.
The get endpoint status command is followed by one data
read that returns the status of the last transaction of the
selected endpoint. This command also resets the
corresponding interrupt flag in the interrupt register, and
clears the status, indicating that it was read. There is one
command for every endpoint.
READ INTERRUPT REGISTER
Command: F4h.
7
6
5
4
3
2
1
0
Data: read 1 byte.
0
The read interrupt register command returns the value of
the interrupt register. Every time a packet is received or
transmitted, an interrupt will be generated and a flag
specific to the physical endpoint will be set in the interrupt
register. Reading the status of the endpoint will clear the
flag.
1999 May 10
0
0
0
0
0
0
0
Power On Value
Data Receive/Transmit
Error Code
Setup Packet
Data 0/1 Packet
Previous Status not Read
32
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 26 Error codes
ERROR
CODE
SET ENDPOINT STATUS
Command: 40h + endpoint index.
RESULT
Data: write 1 byte.
0000
no error
0001
PID encoding error; bits 7 to 4 in the PID
token are not the inversion of bits 3 to 0
0010
PID unknown; PID encoding is valid, but PID
does not exist
This command is used to stall or unstall an endpoint. Only
the least significant bit has a meaning. When the stalled bit
is equal to 1, the endpoint is stalled, when equal to 0, the
endpoint is unstalled. There is one command for every
endpoint.
0011
unexpected packet; packet is not of the type
expected (token, data or acknowledge), or
SETUP token received on non-control
endpoint
A stalled control endpoint is automatically unstalled when
it receives a SETUP token, regardless of the contents of
the packet. If the endpoint should stay in stalled state, the
microcontroller should restall it.
0100
token CRC error
0101
data CRC error
0110
time out error
0111
babble error
1000
unexpected end-of-packet
1001
sent or received NAK
1010
sent stall, a token was received, but the
endpoint was stalled
1011
overflow error, the received data packet was
larger then the buffer size of the selected
endpoint
1100
sent empty packet (ISO only)
READ BUFFER
1101
bitstuff error
Command: F0h.
1110
error in sync
1111
wrong data PID
When a stalled endpoint is unstalled, it is also re-initialized.
This means that its buffer is flushed and the next DATA
PID that will be sent or expected (depending on the
direction of the endpoint) is DATA0.
5
4
3
2
1
X
X
X
X
X
X
X
0
0
Power On Value
Data: read n bytes (max. 10).
The read buffer command is followed by a number of data
reads, which returns the contents of the selected endpoint
data buffer. After each read, the internal buffer pointer is
incremented by 1.
DESCRIPTION
Data receive/transmit
a ‘1’ indicates data has
been received or
transmitted successfully
Error code
see Table 26
Setup packet
a ‘1’ indicates the last
received packet had a
SETUP token (this will
always read ‘0’ for IN
buffers)
Data 0/1 packet
a ‘1’ indicates the last
received packet had a
DATA 1 PID
Previous status not read
a ‘1’ indicates a second
event occurred before the
previous status was read
1999 May 10
6
Stalled
Reserved
Table 27
BIT
7
The buffer pointer is not reset to the buffer start by the read
buffer command. This means that reading a buffer can be
interrupted by any other command (except for select
endpoint).
33
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
acknowledged explicitly that it has seen the SETUP
packet.
The data in the buffer are organized as follows:
Byte 0: transfer successful, number of data bytes (MSB)
If the microcontroller is reading the data from a SETUP
packet, and a new SETUP packet arrives, the device must
accept this new SETUP packet. So the data, currently
being read by the microcontroller, is overwritten with the
new packet. On the arrival of the new packet, the
commands validate buffer and clear buffer are disabled.
If the microcontroller has finished reading the data from
the buffer, it will try to clear the buffer. The device will
ignore this command, so the new SETUP packet in the
buffer is not cleared. The microcontroller will now detect
the interrupt of the new SETUP packet and will start
reading the new data in the buffer.
Byte 1: number of data bytes (LSB)
Byte 2: data byte 0
Byte 3: data byte 1
Byte 4: data byte 2
Byte 5: data byte 3
Byte 6: data byte 4
Byte 7: data byte 5
Byte 8: data byte 6
Byte 9: data byte 7.
Bytes 0 and 1 indicate the number of bytes in the buffer.
Byte 0 is the Most Significant Byte (MSB). Byte 1 is the
Least Significant Byte (LSB). Only bits 1 and 0 of byte 0
are used in the number of bytes indication.
A SETUP token can be followed by an IN token. After the
SETUP token, the microcontroller will start filling the IN
buffer. A SETUP token will clear the IN buffer. This avoids
the following problem: after a SETUP token, the
microcontroller fills the IN buffer. If the SETUP token is
followed by a SETUP token and shortly followed by an IN
token, the device will send the contents of the IN buffer to
the host. The IN buffer was filled after the first SETUP
token. That is why after a SETUP token the IN buffer is
cleared.
Bit 7 of byte 0 indicates if the transaction was successful
(bit 7 is ‘1’ if the transaction was successful). Bits 6 to 2 of
byte 0 are reserved.
WRITE BUFFER
Command: F0h.
If the microcontroller is still filling the buffer when the
second SETUP token arrives, the SETUP token will clear
the IN buffer. If the microcontroller has filled the IN buffer,
it will validate the buffer. So clearing the IN buffer on
receiving a SETUP token is not enough.
Data: write n bytes (max. 10).
The write buffer command is followed by a number of data
writes, which load the endpoint buffer. After each write, the
internal buffer pointer is incremented by 1.
If a SETUP token is received, the device will also disable
the validate buffer command for the IN buffer. If the
microcontroller needs to fill the buffer after a SETUP token,
the command acknowledge setup command must be sent
to enable the validate buffer command.
The buffer pointer is not reset to the buffer start by the write
buffer command. This means that writing a buffer can be
interrupted by any other command (except for select
endpoint).
The data must be organized in the same way as described
in the read buffer command. Bits 7 to 2 of byte 0 are
reserved and must be filled with zeros.
CLEAR BUFFER
Command: F2h.
ACKNOWLEDGE SETUP
Data: none.
Command: F1h.
When a packet is received completely, an internal
endpoint buffer full flag is set. All subsequent packets will
be refused by returning a NACK to the host. When the
microcontroller has read the data, it should free the buffer
by the clear buffer command. When the buffer is cleared,
new packets will be accepted.
Data: none.
The arrival of a SETUP packet flushes the IN buffer and
disables the validate buffer and clear buffer commands for
both IN and OUT endpoints.
The microcontroller needs to re-enable these commands
by the acknowledge setup command. This ensures that
the last SETUP packet stays in the buffer and no packet
can be sent back to the host until the microcontroller has
1999 May 10
34
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
VALIDATE BUFFER
S1CON register
Command: FAh.
The CPU can read from and write to this 8-bit SFR.
Two bits are effected by the SIO1 hardware: the SI bit is
set when a serial interrupt is requested, and the STO bit is
cleared when a STOP condition is present on the I2C-bus.
The STO bit is also cleared when ENS1 = ‘0’. Reset
initializes S1CON to 00h.
Data: none.
When the microcontroller has written data into an IN buffer,
it should set the buffer full flag by the validate buffer
command. This indicates that the data in the buffer are
valid and can be sent to the host when the next IN token is
received.
7
General commands
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Power On Value
0
CR0
CR1
AA
SI
STO
STA
ENS1
CR2
READ CURRENT FRAME NUMBER
Command: F5h.
Data: read 1 or 2 bytes.
This command is followed by one or two data reads and
returns the frame number of the last successfully received
SOF. The frame number is eleven bits wide. The frame
number is returned least significant byte first. In case the
user is only interested in the lower 8 bits of the frame
number only the first byte needs to be read.
CR2, 1 AND 0 - THE CLOCK RATE BITS
These three bits determine the serial clock frequency
when SIO1 is in a master mode.
The various serial rates are shown in Table 28.
I2C MASTER/SLAVE INTERFACE
I2C
Table 28 Serial clock rates (SCL line)
I2C-bus
The
module implements a master/slave
interface with integrated shift register, shift timing
generation and slave address recognition. It is compliant
to the I2C-bus specification IC20/Jan92. I2C standard
mode (100 kHz SCL) and fast mode (400 kHz) are
supported. Low speed mode and extended 10 bit
addressing are unsupported.
Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to VDDE via a pull-up resistor.
The timing definition of the I2C-bus is given in Fig.7.
CR1
CR0
I2C BIT FREQUENCY
(kHz)
0
0
0
1200
0
0
1
600
0
1
0
400
0
1
1
300
1
0
0
150
1
0
1
100
1
1
0
75
1
1
1
3.9 ... 501
When the CR bits are ‘111’, the maximum bit rate for the
data transfer will be derived from the Timer 1 overflow rate
divided by 2 (i.e. every time the Timer 1 overflows, the
SCL signal will toggle).
Programmer’s view
For a detailed description of the I2C-bus protocol refer to
Philips Integrated Circuits Data Handbook IC20, 8XC552.
The programmer’s view of the I2C library function is -with
one exception- identical to that of the 8XC552
microcontroller. Only the bit rate frequency selection in
S1CON and the handling of the Timer 1 overflow
information deviates to accommodate 400 kHz operation.
1999 May 10
CR2
35
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t LOW
t BUF
tr
tf
t HD;STA
t SP
Philips Semiconductors
Universal Serial Bus (USB) CODEC
1999 May 10
SDA
36
SCL
S
t HD;DAT
t SU;DAT
t HIGH
t SU;STA
MBC611
P
Preliminary specification
Fig.7 Definition of timing of the I2C-bus.
t SU;STO
Sr
UDA1325
handbook, full pagewidth
t HD;STA
P
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
All digital I/Os
VI/O
DC input/output voltage range
IO
output current
VDDE = 5.0 V
−0.5
−
VDDE
V
−
−
4
mA
Temperature values
Tj
junction temperature
0
−
125
°C
Tstg
storage temperature
−55
−
+150
°C
Tamb
operating ambient temperature
0
25
70
°C
note 1
−3000
−
+3000
V
note 2
−300
−
+300
V
Electrostatic handling
Ves
electrostatic handling
Notes
1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
2. Equivalent to discharging a 200 pF capacitor through a 2.5 µH series conductor.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
VALUE
UNIT
thermal resistance from junction to ambient
UDA1325PS
in free air
48
K/W
UDA1325H
in free air
48
K/W
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDE
supply voltage periphery (I/O)
4.75
5.0
5.25
V
VDD
supply voltage (core)
3.0
3.3
3.6
V
VI
DC input voltage range
for D+ and D−
0.0
−
VDD
V
for VINL and VINR
−
0.5VDD
−
V
for digital I/Os
0.0
−
VDDE
V
1999 May 10
37
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
DC CHARACTERISTICS
VDDE = 5.0 V; VDD = 3.3 V; Tamb = 25 °C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDE
digital supply voltage periphery
4.75
5.0
5.25
V
VDDI
digital supply voltage core
3.0
3.3
3.6
V
VDDA1
analog supply voltage 1
3.0
3.3
3.6
V
VDDA2
analog supply voltage 2
3.0
3.3
3.6
V
VDDA3
analog supply voltage 3
3.0
3.3
3.6
V
VDDO
operational amplifier supply voltage
3.0
3.3
3.6
V
VDDX
crystal oscillator supply voltage
IDDE
digital supply current periphery
IDDI
3.0
3.3
3.6
V
−
3.7
−
mA
digital supply current core
−
39.0
−
mA
IDDA1
analog supply current 1
−
3.6
−
mA
IDDA2
analog supply current 2
−
8.0
−
mA
IDDA3
analog supply current 3
−
0.9
9.0(2)
mA
note 1
IDDO
operational amplifier supply current
−
3.0
−
mA
IDDX
crystal oscillator supply current
−
1.2
13.0(3)
mA
Ptot
total power dissipation
−
200
−
mW
Pps
total power dissipation in power
saving mode
−
1.2
−
mW
−0.5
−
VDDI
V
−
3.6
V
−
−
0.3
V
note 4
Inputs/outputs D+ and D−
VI
static DC input voltage
VO(H)
static DC output voltage HIGH
RL = 15 kΩ
2.8
connected to GND
VO(L)
static DC output voltage LOW
RL = 1.5 kΩ
connected to VDD
ILO
high impedance data line output
leakage current
−
−
10
µA
VI(diff)
differential input sensitivity
0.2
−
−
V
VCM(diff)
differential common mode range
0.8
−
2.5
V
VSE(R)(th)
single-ended receiver threshold
voltage
0.8
−
2.0
V
CIN
transceiver input capacitance
−
−
20
pF
−
−
0.3VDDE
V
pin to GND
Digital input pins
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.7VDDE
−
VDDE
V
ILI
input leakage current
−
−
1
µA
CI
input capacitance
−
−
5
pF
1999 May 10
38
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
SYMBOL
PARAMETER
UDA1325
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PGA and ADC
Vref(AD)
reference voltage PGA and ADC
−
0.5VDDA2
−
V
Vref(ADC)(pos)
positive reference voltage of the
ADC
−
VDDA2
−
V
Vref(ADC)(neg)
negative reference voltage of the
ADC
−
0.0
−
V
VI(PGA)
DC input voltage VINL and VINR of
the PGA
−
0.5VDDA2
−
V
RI(PGA)
DC input resistance at VINL and
VINR of the PGA
−
12.5
−
kΩ
Filter stream DAC
Vref(DA)
reference voltage DAC
−
0.5VDDA1
−
V
VO(CM)
common mode output voltage
−
0.5VDDA1
−
V
RO(VOUT)
output resistance at VOUTL and
VOUTR
−
11
−
Ω
RO(L)
output load resistance
2.0
−
−
kΩ
CO(L)
output load capacitance
−
−
50
pF
Notes
1. This value depends strongly on the application. The specified value is the typical value obtained using the application
diagram as illustrated in Fig.8.
2. At start-up of the OSCAD oscillator.
3. At start-up of the OSC48 oscillator.
4. Exclusive the IDDE current which depends on the components connected to the I/O pins.
1999 May 10
39
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
AC CHARACTERISTICS
VDDE = 5.0 V; VDDI = 3.3 V; Tamb = 25 °C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Driver characteristics D+ and D− (full-speed mode)
fo(s)
audio sample output frequency
5
−
55
kHz
tr
rise time
CL = 50 pF
4
−
20
ns
tf
fall time
CL = 50 pF
4
−
20
ns
trf(m)
rise/fall time matching (tr/tf)
90
−
110
%
Vcr
output signal crossover voltage
1.3
−
2.0
V
Ro(drive)
driver output resistance
28
−
43
Ω
steady-state drive
Data source timings D+ and D− (full-speed mode)
fi(s)
audio sample input frequency
5
−
55
kHz
ffs(D)
full speed data rate
11.97
12.00
12.03
Mbits/s
tfr(D)
frame interval
0.9995
1.0000
1.0005
ms
tJ1(diff)
source differential jitter to next
transition
−3.5
0.0
+3.5
ns
tJ2(diff)
source differential jitter for paired
transitions
−4.0
0.0
+4.0
ns
tW(EOP)
source end of packet width
160
−
175
ns
tEOP(diff)
differential to end of packet
transition skew
−2.0
−
+5.0
ns
tJR1
receiver data jitter tolerance to next
transition
−18.5
0.0
+18.5
ns
tJR2
receiver data jitter tolerance for
paired transitions
−9.0
0.0
+9.0
ns
tEOPR1
end of packet width at receiver
must reject as end of packet
40
−
−
ns
tEOPR2
end of packet width at receiver
must accept as end of packet
82
−
−
ns
Serial input/output data timing
fs
system clock frequency
−
12
−
MHz
fi(WS)
word selection input frequency
5
−
55
kHz
tr
rise time
−
−
20
ns
tf
fall time
−
−
20
ns
tBCK(H)
bit clock HIGH time
55
−
−
ns
tBCK(L)
bit clock LOW time
55
−
−
ns
ts;DAT
data set-up time
10
−
−
ns
th;DAT
data hold time
20
−
−
ns
ts;WS
word selection set-up time
20
−
−
ns
th;WS
word selection hold time
10
−
−
ns
1999 May 10
40
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
SYMBOL
PARAMETER
UDA1325
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SDA and SCL lines for 100 kHz I2C devices
fSCL
SCL clock frequency
0
−
100
kHz
tBUF
bus free time between a STOP and
START condition
4.7
−
−
µs
tHD;STA
hold time (repeated) START
condition
4.0
−
−
µs
tLOW
LOW period of the SCL clock
4.7
−
−
µs
tHIGH
HIGH period of the SCL clock
4.0
−
−
µs
tSU;STA
set-up time for a repeated START
condition
4.7
−
−
µs
tSU;STO
set-up time for STOP condition
4.0
−
−
µs
tHD;DAT
data hold time
5.0
−
−
µs
tSU;DAT
data set-up time
250
−
−
ns
tr
rise time of both SDA and SCL
signals
−
−
1000
ns
tf
fall time of both SDA and SCL
signals
−
−
300
ns
CL(bus)
capacitive load for each bus line
−
−
400
pF
Oscillator 1 (system clock)
fosc
oscillator frequency
−
48
−
MHz
δ
duty factor
−
50
−
%
gm
transconductance
12.8
22.1
30.2
mS
Ro
output resistance
0.6
1.1
2.3
kΩ
Ci(XTAL1a)
parasitic input capacitance XTAL1a
4.5
4.8
5.2
pF
Ci(XTAL2a)
parasitic input capacitance XTAL2a
4.1
4.6
5.0
pF
Istart
start-up current
3.7
7.6
13.0
mA
Oscillator 2 (for ADC clock)
fosc
oscillator frequency
8.192
−
14.08
MHz
δ
duty cycle
−
50
−
%
gm
transconductance
8.1
13.6
18.1
mA/V
Ro
output resistance
1.3
2.0
4.0
kΩ
Ci(XTAL1b)
parasitic input capacitance XTAL1b
5.0
5.4
5.7
pF
Ci(XTAL2b)
parasitic input capacitance XTAL2b
4.1
4.6
5.0
pF
Istart
start-up current
2.4
5.0
8.4
mA
1999 May 10
41
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
SYMBOL
PARAMETER
UDA1325
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog PLL (for ADC clock)
fclk(PLL)
PLL clock frequency
8.1920
11.2896
12.2880
MHz
δ
duty factor
−
50
−
%
tstrt(PO)
start-up time after power-on
−
−
10
ms
25Cref(2)
−
−
ms
1414(3)
Power-on reset
tsu(PO)
power-on set-up-time
note 1
PGA and ADC
Vi(FS)(rms)
full-scale input voltage (RMS value) PGA gain = −3 dB −
Ci(PGA)
input capacitance of the PGA
(THD + N)/S
total harmonic distortion plus
noise-to-signal ratio
−
mV
PGA gain = 0 dB
−
1000
−
mV
PGA gain = 3 dB
−
708
−
mV
PGA gain = 9 dB
−
355
−
mV
PGA gain = 15 dB −
178
−
mV
PGA gain = 21 dB −
89
−
mV
PGA gain = 27 dB −
44
−
mV
−
−
20
pF
Vi (0 dB)
1.0 V (RMS)
−
−85
−80
dB
−
0.0056
0.01
%
Vi (−60 dB)
−
−30
−20
dB
fs = 44.1 kHz at
input signal of
1 kHz; PGA
gain = 0 dB;
note 4
−
3.2
10.0
%
S/N
signal to noise ratio
Vi = 0.0 V
90
95
−
dBA
αct
crosstalk between channels
PGA gain = 0 dB
−
100
−
dB
fs
sample frequency (128fs)
OL
digital output level
1999 May 10
PGA gain = 0 dB,
Vi = 1 V (RMS)
42
0.640
−
7.04
MHz
−
−2.0
−
dBFS
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
SYMBOL
PARAMETER
UDA1325
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Filter stream DAC
RES
resolution
16
−
−
bits
Vo(FS)(rms)
full-scale output voltage
(RMS value)
VDD = 3.3 V
−
0.66
−
V
SVRR
supply voltage ripple rejection at
VDDA and VDDO
fripple = 1 kHz
Vripple(p-p) = 0.1 V
−
60
−
dB
∆Vo
channel unbalance
maximum volume
−
0.03
−
dB
αct
crosstalk between channels
RL = 5 kΩ
−
95
−
dB
(THD + N)/S
total harmonic distortion plus
noise-to-signal ratio
fs = 44.1 kHz;
RL = 5 kΩ; note 5
at input signal of −
1 kHz (0 dB)
−
−90
−80
dB
0.0032
0.01
%
at input signal of −
1 kHz (−60 dB) −
−30
−20
dB
3.2
10
%
95
−
dB
S/N
signal-to-noise ratio at bipolar zero
A-weighting at
code 0000H
90
Notes
1. Strongly depends on the external decoupling capacitor connected to Vref(DA).
2. Cref in µF.
3. Although a level of 1.414 V (RMS) would be required to optimal drive the ADC in this gain setting, this level can not
be used. Due to the 3.3 V supply voltage input, signals of 1.17 V (RMS) and higher will result in clipping.
4. Measured with the APLL as ADC clock source.
5. Measured with I2S-bus input as digital source.
1999 May 10
43
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
APPLICATION INFORMATION
+VA
handbook, full pagewidth
+VA
R35
1Ω
C34
47 µF
(16 V)
C38
GP0/BCKI
BCKI
GP5/WSI
WSI
GP1/DI
DI
BCK
BCK
digital
input
recording
WS
WS
DA
DA
47 µF
(16 V)
C21
100 nF
(63 V)
100 nF
(63 V)
VSSA1
VDDA1 VSSA2
39
digital
input
playback
R27
1Ω
C32
38
44
VDDA2
42
17
15
13
61
59
57
+VC
L1
X4
1
2
3
4
R48
1.5 kΩ
VUSB
1
2
3
4
8
R7
7
6
5
R16
C16
10 nF
(50 V)
C15
D−
22 Ω
C18
22 pF
(63 V)
22 Ω
C17
22 pF
(63 V)
10 nF
(50 V)
C8
analog
input
recording
D+
VINR
6
UDA1325H
8
47
47 µF (16 V)
C22
VINL
43
47 µF (16 V)
C44
L5
10 nF (63 V)
1.5 µH
1
XTAL2b
26
C38
12 pF (63 V)
X1
48 MHz
C37
XTAL1b
25
12 pF (63 V)
XTAL2a
ADC XTAL
XTAL1a
C5
18 pF
(50 V)
VA(ext)
VD(ext)
L8
+VA
BLM32A07
L7
+VC
BLM32A07
L6
BLM32A07
+VD
C47
100 µF
(16 V)
C46
100 µF
(16 V)
53
54
C6
18 pF
(50 V)
C45
100 µF
(16 V)
10
9
VSSI
100 nF
(63 V)
C24
MGM760
44
VDDE
C26
L2
BLM32A07
R17
1Ω
+VC
Fig.8 Application diagram UDA1325H (continued in Fig.9).
1999 May 10
12
VSSE
C25
100 nF
(63 V)
GND
11
VDDI
100 nF
(63 V)
C27
100 nF
(63 V)
L3
BLM32A07
R25
1Ω
+VD
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
+VA
handbook, full pagewidth
+VA
R10
1Ω
C7
55
R8
1Ω
C11
47 µF
(16 V)
C19
100 nF
(63 V)
VSSA3
UDA1325
100 nF
(63 V)
VDDA3 VRN
52
49
VRP
51
56
58
60
62
64
3
5
7
50
P0.0
D7
P0.1
D6
P0.2
D5
P0.3
D4
P0.4
D3
P0.5
D2
P0.6
D1
P0.7
D0
ALE
LE
OE
18
19
17
16
14
15
13
12
D1
74HCT373D
8
7
9
6
4
5
3
2
20
11
1
10
14
16
18
20
22
23
31
48
41
Q4
A3
Q3
A4
Q2
A5
Q1
A6
Q0
A7
VCC
A8
C24
GND
100 nF
(50 V)
A10
A11
OE
P2.3
CE
P2.4
PGM
P2.5
VPP
PSEN
12
8
13
7
15
6
16
5
17
4
18
3
19
A0
C36
100 nF
(63 V)
1
A1
2
A2
3
8
D4
PCF85116-3
4
7
6
5
VDD
PTC
23
28
2
26
14
22
20
27
1
J3
R38
10 kΩ
+VD
1
R39
10 kΩ
(I2C-bus)
SCL
2
Vref(DA)
Vref(AD)
VOUTR
C29
100 nF
(63 V)
C41
47 µF
(16 V)
C35
C48
VOUTL
C31
47 µF
(16 V)
analog
output
playback
47 µF (16 V)
2
1
63
36
35
4
33
32
VSSO
VSSX
C33
C28
100 nF
(63 V)
100 nF
(63 V)
C39
C18
47 µF
(16 V)
R43
1Ω
+VA
GP3/WSO
GP2/DO
BCKO
WSO
DO
digital
output
playback
RTCB
TC
SHTCB
28
24
VDDO
GP4/BCKO
100 nF
(63 V)
VDDX
L13
BLM32A07
R26
1Ω
+VC
MGM761
Fig.9 Application diagram UDA1325H (continued from Fig.8).
1999 May 10
45
(internal ROM)
2
1
SDA
O1
O2
O3
O4
O5
O6
O7
21
3
+VD
SCL
SDA
O0
25
4.7 kΩ
R20
1Ω
11
9
+VD
R28
EA
10
D2
A9
24 EEPM27128
+VD
P2.2
47 µF (16 V)
34
A2
A13
C28
100 nF
(63 V)
37
Q5
P2.1
VSS
40
A1
A12
UDA1325H
21
A0
Q6
P2.0
+VD
19
Q7
(external ROM)
VCC
C25
GND
+VD
100 nF
(50 V)
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C32
47 µF
(16 V)
C38
47 µF
(16 V)
C21
100 nF
(63 V)
100 nF
(63 V)
+VA
+VA
R10
1Ω
C7
R8
1Ω
C11
47 µF
(16 V)
C19
+VD
100 nF
(63 V)
R20
VDDA1 VSSA2
VSSA1
30
GP0/BCKI
BCKI
digital
input
playback
GP5/WSI
WSI
GP1/DI
DI
BCK
BCK
digital
input
recording
WS
WS
DA
DA
29
35
1Ω
100 nF
(63 V)
VDDA2
VSSA3
42
33
VDDA3 VRN
VRP
37
39
38
A0
C36
100 nF
(63 V)
16
A1
A2
15
VSS
1
2
3
4
1
2
3
4
R48
1.5 kΩ
8
R7
7
6
5
C15
D−
22 Ω
R16
C16
10 nF
(50 V)
C18
22 pF
(63 V)
D+
22 Ω
C17
22 pF
(63 V)
18
3
17
2
31
1
32
46
C8
analog
input
recording
VINR
3
4
7
6
5
+VD
PTC
SCL
R38
10 kΩ
SDA
SDA
1
(I2C-bus)
2
Vref(DA)
Vref(AD)
8
28
VOUTR
VOUTL
C31
47 µF
(16 V)
C29
100 nF
(63 V)
C41
47 µF
(16 V)
C35
47 µF (16 V)
9
25
R39
10 kΩ
SCL
C28
100 nF
(63 V)
UDA1325PS
10 nF
(50 V)
D4
PCF85116-3
2
14
+VC
VUSB
L1
X4
VDD
8
1
C48
analog
output
playback
Philips Semiconductors
C34
R27
1Ω
Universal Serial Bus (USB) CODEC
+VA
R35
1Ω
dbook, full pagewidth
1999 May 10
+VA
47 µF (16 V)
36
47 µF (16 V)
C22
VINL
34
47 µF (16 V)
6
5
C44
L5
10 nF (63 V)
1.5 µH
1
XTAL2b
4
GP4/BCKO
GP3/WSO
GP2/DO
BCKO
WSO
DO
digital
output
playback
21
C38
12 pF (63 V)
X1
48 MHz
C37
XTAL1b
27
20
26
12 pF (63 V)
7
XTAL2a
ADC XTAL
XTAL1a
C5
18 pF
(50 V)
C6
18 pF
(50 V)
RTCB
TC
SHTCB
40
41
11
10
VSSI
12
VDDI
VDDE
C26
100 nF
(63 V)
C24
R17
1Ω
+VC
100 nF
(63 V)
C27
100 nF
(63 V)
L3
BLM32A07
R25
1Ω
+VD
22
19
VDDO
VSSX
C33
C28
100 nF
(63 V)
100 nF
(63 V)
C39
C18
47 µF
(16 V)
R43
1Ω
+VA
100 nF
(63 V)
VDDX
VA(ext)
L13
BLM32A07
VD(ext)
L8
Fig.10 Application diagram UDA1325PS.
+VC
BLM32A07
L6
BLM32A07
R26
1Ω
+VC
+VA
BLM32A07
L7
GND
+VD
C47
100 µF
(16 V)
C46
100 µF
(16 V)
C45
100 µF
(16 V)
MGS271
UDA1325
100 nF
(63 V)
L2
BLM32A07
23
VSSO
Preliminary specification
C25
24
13
VSSE
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
PACKAGE OUTLINES
seating plane
SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
ME
D
A2
L
A
A1
c
e
Z
b1
(e 1)
w M
MH
b
22
42
pin 1 index
E
1
21
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
5.08
0.51
4.0
1.3
0.8
0.53
0.40
0.32
0.23
38.9
38.4
14.0
13.7
1.778
15.24
3.2
2.9
15.80
15.24
17.15
15.90
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
90-02-13
95-02-04
SOT270-1
1999 May 10
EUROPEAN
PROJECTION
47
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
c
y
X
51
A
33
52
32
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
20
64
detail X
19
1
ZD
w M
bp
e
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
3.20
0.25
0.05
2.90
2.65
0.25
0.50
0.35
0.25
0.14
20.1
19.9
14.1
13.9
1
24.2
23.6
18.2
17.6
1.95
1.0
0.6
0.2
0.2
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-02-04
97-08-01
SOT319-2
1999 May 10
EUROPEAN
PROJECTION
48
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
SOLDERING
Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Through-hole mount packages
SOLDERING BY DIPPING OR BY SOLDER WAVE
• For packages with leads on two sides and a pitch (e):
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Surface mount packages
REFLOW SOLDERING
MANUAL SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
1999 May 10
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
49
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
MOUNTING
PACKAGE
WAVE
REFLOW(1)
DIPPING
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
suitable(2)
−
suitable
Surface mount
not suitable
suitable
−
suitable
−
suitable
−
not
recommended(4)(5)
suitable
−
not
recommended(6)
suitable
−
BGA, SQFP
suitable(3)
HLQFP, HSQFP, HSOP, HTSSOP, SMS
not
PLCC(4), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 May 10
50
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 May 10
51
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA 64
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/750/01/pp52
Date of release: 1999 May 10
Document order number:
9397 750 02805