INTEGRATED CIRCUITS DATA SHEET UDA1340 Low-voltage low-power stereo audio CODEC with DSP features Preliminary specification Supersedes data of 1997 May 20 File under Integrated Circuits, IC01 1997 Jul 09 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 FEATURES General • Low power consumption • 3.0 V power supply • 256, 384 and 512fs system clock • Small package size (SSOP28) • ADC plus integrated high pass filter to cancel DC offset • Overload detector for easy record level control GENERAL DESCRIPTION • Separate power control for ADC and DAC The UDA1340 is a single-chip stereo Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with signal processing features employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording and playback functions. • Integrated digital filter plus DAC • No analog post filter required for DAC • Easy application • Functions controllable by microcontroller interface. Multiple format input interface • I2S-bus, MSB-justified and LSB-justified format compatible The UDA1340 supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits and the LSB justified serial data format with word lengths of 16, 18 and 20 bits. • 1fs input and output format data rate. DAC digital sound processing The UDA1340 has special sound processing features in playback mode, de-emphasis, volume, bass boost, treble, and soft mute, which can be controlled via the microcontroller interface. • Digital volume control • Digital tone control, bass boost and treble • dB-linear volume and tone control (low microcontroller load) • Digital de-emphasis for 32, 44.1 and 48 kHz fs • Soft mute. Advanced audio configuration • Stereo single-ended input configuration • Stereo line output (under microcontroller volume control) • Power-down click prevention circuitry • High linearity, dynamic range, low distortion. ORDERING INFORMATION TYPE NUMBER UDA1340M 1997 Jul 09 PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm 2 VERSION SOT341-1 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDDA(ADC) ADC analog supply voltage 2.7 3.0 3.6 V VDDA(DAC) DAC analog supply voltage 2.7 3.0 3.6 V VDDO operational amplifiers supply voltage 2.7 3.0 3.6 V VDDD digital supply voltage 2.7 3.0 3.6 V IDDA(ADC) ADC supply current − 4.5 − mA IDDA(DAC) DAC supply current − 3.5 − mA IDDO operational amplifier supply current − 4 − mA IDDD digital supply current − 6 − mA IPD(ADC) digital ADC power-down supply current − 3 − mA IPD(DAC) digital DAC power-down supply current − 3 − mA Tamb operating ambient temperature −20 − +85 °C Analog-to-digital converter VI(rms) input voltage (RMS value) − 0.8 − V (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB − −85 −80 dB at −60 dB; A-weighted − −35 −30 dBA S/N signal-to-noise ratio Vi = 0 V; A-weighted αcs channel separation − 95 − dBA − 100 − dB − 0.8 − V Digital-to-analog converter Vo(rms) output voltage (RMS value) (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB − −85 −80 dB at −60 dB; A-weighted − −35 − dBA S/N signal-to-noise ratio code = 0; A weighted − 100 − dBA αcs channel separation − 100 − dB Power performance PADDA power consumption in record and playback mode − 54 − mW PDA power consumption in playback only mode − 33 − mW PAD power consumption in record only mode − 27 − mW PPD power consumption in power-down mode − 6 − mW 1997 Jul 09 3 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 BLOCK DIAGRAM VDDA(ADC) VSSA(ADC) handbook, full pagewidth 2 VINL VADCP 1 VADCN 7 Vref(A) 6 4 3 5 ADC ADC 8 VDDD VSSD DATAO BCK WS DATAI 10 21 DECIMATION FILTER UDA1340 20 11 TEST1 TEST2 TEST3 DC-CANCELLATION FILTER 18 13 16 DIGITAL INTERFACE 17 14 L3-BUS INTERFACE 15 19 12 OVERFL VINR 9 L3MODE L3CLOCK L3DATA SYSCLK DSP FEATURES INTERPOLATION FILTER NOISE SHAPER DAC DAC VOUTL 26 24 25 27 VDDO VSSO 23 VDDA(DAC) 22 VSSA(DAC) Fig.1 Block diagram. 1997 Jul 09 4 28 Vref(D) VOUTR MGG839 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 PINNING SYMBOL PIN VSSA(ADC) 1 ADC analog ground VDDA(ADC) 2 ADC analog supply voltage VINL 3 ADC input left Vref(A) 4 ADC reference voltage VINR 5 ADC input right VADCN 6 ADC negative reference voltage VADCP 7 ADC positive reference voltage TEST1 8 test control 1 (pull-down) OVERFL 9 overload flag output VDDD 10 digital supply voltage VSSD 11 digital ground SYSCLK 12 system clock 256, 384 or 512fs L3MODE 13 L3-bus mode input L3CLOCK 14 L3-bus clock input L3DATA 15 L3-bus data input BCK 16 WS Description handbook, halfpage VSSA(ADC) 1 28 Vref(D) VDDA(ADC) 2 27 VSSO 26 VOUTL VINL 3 25 VDDO Vref(A) 4 24 VOUTR VINR 5 23 VDDA(DAC) VADCN 6 VADCP 7 UDA1340 22 VSSA(DAC) TEST1 8 21 TEST2 OVERFL 9 20 TEST3 bit clock input VDDD 10 19 DATAI 17 word selection input VSSD 11 18 DATAO DATAO 18 data output DATAI 19 data input TEST3 20 test output TEST2 21 test control 2 (pull-down) VSSA(DAC) 22 DAC analog ground VDDA(DAC) 23 DAC analog supply voltage VOUTR 24 DAC output right VDDO 25 operational amplifier supply voltage VOUTL 26 DAC output left VSSO 27 operational amplifier ground Vref(D) 28 DAC reference voltage 1997 Jul 09 SYSCLK 12 17 WS L3MODE 13 16 BCK L3CLOCK 14 15 L3DATA MGG838 Fig.2 Pin configuration. 5 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 FUNCTIONAL DESCRIPTION DC cancellation filter (ADC) System clock An optional IIR high-pass filter is provided to remove unwanted DC components. The operation is selected by the microcontroller via the L3-bus. The filter characteristics are given in Table 2. The UDA1340 accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable. The options are 256fs, 384fs and 512fs. The system clock must be locked in frequency to the digital interface input signals. Table 2 DC cancellation filter characteristics ITEM Multiple format input/output interface The UDA1340 supports the following data input/output formats: none Passband gain 0 Attenuation at DC Dynamic range • MSB justified serial format with data word length of up to 20 bits VALUE (dB) Passband ripple Droop • I2S-bus with data word length of up to 20 bits CONDITION at 0.00045fs 0.031 at 0.00000036fs >40 0 − 0.45fs >110 Mute (ADC) • LSB justified serial format with data word lengths of 16, 18 or 20 bits. On recovery from power-down or switching on of the system clock, the serial data output DATAO is held LOW until valid data is available from the decimation filter. This time depends on whether the DC cancellation filter is selected: The formats are illustrated in Fig.3. Left and right data-channel words are time multiplexed. Analog-to-Digital Converter (ADC) 1024 DC cancel off: time = ------------- , t = 23.2 ms when fs The stereo ADC of the UDA1340 consists of two third-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The over-sampling ratio is 128. fs = 44.1 kHz 12288 DC cancel on: time = ---------------- , t = 279 ms when fs Decimation filter (ADC) fs = 44.1 kHz The decimation from 128fs is performed in two stages. Overload detection (ADC) sin x The first stage realizes 3rd-order ------------ characteristic. This x filter decreases the sample rate by 16. The second stage, an FIR filter, consists of 3 half-band filters, each decimating by a factor of 2. Table 1 In practice the output is used to indicate whenever the output data, in either the left or right channel, is greater than −1 dB (actual figure is −1.16 dB) of the maximum possible digital swing. When this condition is detected the OVERFL output is forced HIGH for at least 512fs cycles (11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement. Decimation filter characteristics ITEM Passband Ripple Stop band Dynamic range Gain 1997 Jul 09 CONDITION VALUE (dB) 0 − 0.45fs ±0.05 >0.55fs −60 0 − 0.45fs 108 overall −1.16 6 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 Interpolation filter (DAC) The Filter Stream DAC (FSDAC) The digital filter interpolates from 1fs to 128fs by means of a cascade of a recursive filter and an FIR filter. The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. Table 3 Interpolation filter characteristics ITEM Passband ripple Stop band Dynamic range Gain CONDITION VALUE (dB) 0 − 0.45fs ±0.03 >0.55fs −50 0 − 0.45fs 108 DC −3.5 Noise shaper (DAC) The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. 1997 Jul 09 7 1997 Jul 09 8 MSB B2 2 MSB 2 3 LEFT B2 3 LEFT MSB 20 B2 19 B3 18 LEFT MSB 18 LEFT LEFT B4 17 B2 17 2 1 B5 16 B3 16 MSB 16 B6 15 B4 15 B2 15 3 B15 LSB 1 MSB-JUSTIFIED FORMAT 2 >=8 LSB 1 LSB 1 LSB-JUSTIFIED FORMAT 20 BITS B19 2 LSB-JUSTIFIED FORMAT 18 BITS B17 2 20 MSB B2 LSB MSB LSB MSB INPUT FORMAT I2S-BUS >=8 LSB-JUSTIFIED FORMAT 16 BITS RIGHT B2 3 RIGHT Fig.3 Serial interface formats. B2 2 LSB MSB 1 LSB MSB >=8 >=8 B2 19 B3 18 MSB 18 B4 17 B5 16 RIGHT B2 16 B3 RIGHT 17 16 MSB RIGHT B6 15 B4 15 B2 15 1 B19 2 B17 2 MGG841 LSB 1 LSB 1 B15 LSB 2 Low-voltage low-power stereo audio CODEC with DSP features DATA BCK WS DATA BCK WS DATA BCK WS DATA BCK 1 1 dbook, full pagewidth WS DATA BCK WS Philips Semiconductors Preliminary specification UDA1340 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 L3-Interface Table 4 The UDA1340 has a microcontroller input mode. In the microcontroller mode, all the digital sound processing features and the system controlling features can be controlled by the microcontroller. The controllable features are: • System clock frequency • Data input format • Power control Selection of data transfer BIT 1 BIT 0 TRANSFER 0 0 DATA (volume, bass boost, treble, de-emphasis, mute, mode and power control) 0 1 not used 1 0 STATUS (system clock frequency, data input format and DC-filter) 1 1 not used • DC-filtering • De-emphasis Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the UDA1340 is 000101 (bit 7 to bit 2). In the event that the UDA1340 receives a different address, it will deselect its microcontroller interface logic. • Volume • Flat/min/max switch • Bass boost • Treble • Mute. Data transfer mode The exchange of data and control information between the microcontroller and the UDA1340 is accomplished through a serial hardware interface comprising the following pins: The selection preformed in the address mode remains active during subsequent data transfers, until the UDA1340 receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode, shown in Fig.4. The maximum input clock and data rate is 64fs. All transfers are byte wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1340 after the eighth bit of a byte has been received. A multibyte transfer is illustrated in Fig.6. L3DATA: microcontroller interface data line L3MODE: microcontroller interface mode line L3CLOCK: microcontroller interface clock line. Information transfer via the microcontroller bus is organized in accordance with the so called ‘L3’ format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see Figs 4 and 5). PROGRAMMING THE SOUND PROCESSING AND OTHER FEATURES The address mode is required to select a device communicating via the L3-bus and to define the destination registers for the data transfer mode. Data transfer for the UDA1340 can only be in one direction, input to the UDA1340 to program its sound processing and other functional features. The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode, BIT 1 and BIT 0 (see Table 4). The second selection is performed by the 2 MSBs of the data byte (BIT 7 and BIT 6). The other bits in the data byte (BIT 5 to BIT 0) is the value that is placed in the selected registers. Address mode The address mode is used to select a device for subsequent data transfer and to define the destination registers. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 data bits. The fundamental timing is shown in Fig.4. Data bits 0 to 1 indicate the type of subsequent data transfer as given in Table 4. 1997 Jul 09 When the data transfer of type ‘data’ is selected, the features VOLUME, BASS BOOST, TREBLE, DE-EMPHASIS, MUTE, MODE and POWER CONTROL can be controlled. When the data transfer of type ‘status’ is selected, the features SYSTEM CLOCK FREQUENCY, DATA INPUT FORMAT and DC-FILTER can be controlled. 9 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 handbook, full pagewidth L3MODE t s;MA t h;MA tLC tHC t s;MA t h;MA L3CLOCK Tcy t s;DAT t h;DAT BIT 7 BIT 0 L3DATA MGD016 Fig.4 Timing address mode. handbook, full pagewidth thalt thalt L3MODE tLC t s;MT Tcy tHC t h;MT L3CLOCK t h;DAT L3DATA write t s;DAT t h;DAT BIT 7 BIT 0 MGD017 Fig.5 Timing for data transfer mode. 1997 Jul 09 10 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 thalt handbook, full pagewidth L3MODE L3CLOCK L3DATA address data byte #1 data byte #2 address MGD018 Fig.6 Multibyte transfer. Table 5 Data transfer of type ‘status’; note 1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 X SC1 SC0 IF2 IF1 IF0 DC 1 X X X X X X X REGISTER SELECTED System Clock frequency (1 : 0) data Input Format (2 : 0) DC-filter not used Note 1. X = don’t care. Table 6 Data transfer of type ‘data’; note 1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 VC5 VC4 VC3 VC2 VC1 VC0 Volume Control (5 : 0) 0 1 BB3 BB2 BB1 BB0 TR1 TR0 Bass Boost (3 : 0) Treble (1 : 0) 1 0 X DE1 DE0 MT M1 M0 DE-emphasis (1 : 0) MuTe Mode (1 : 0) 1 1 X X X X PC1 PC0 Power Control (1 : 0) Note 1. X = don’t care. 1997 Jul 09 11 REGISTER SELECTED Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 SYSTEM CLOCK FREQUENCY DC-FILTER A 2-bit value (SC1 and SC0) to select the used external clock frequency (see Table 7). A 1-bit value to enable the digital DC-filter (see Table 9). Table 9 Table 7 DC-filtering System clock frequency settings DC FUNCTION SC1 SC0 FUNCTION 0 no DC-filtering 0 0 512fs 1 DC-filtering 0 1 384fs 1 0 256fs 1 1 not used VOLUME CONTROL A 6-bit value to program the left and right channel volume attenuation (VC5 to VC0). The range is 0 dB to −∞ dB in steps of 1 dB (see Table 10). DATA INPUT FORMAT A 3-bit value (IF2 to IF0) to select the used data format (see Table 8). Table 8 Table 10 Volume settings Data input format settings VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB) 0 IF2 IF1 IF0 FUNCTION 0 0 0 0 0 0 0 0 0 I2S-bus 0 0 0 0 0 1 0 0 0 0 1 0 −1 0 0 0 1 1 −2 0 0 1 LSB justified, 16 bits 0 0 1 0 LSB justified, 18 bits 0 0 1 1 LSB justified, 20 bits : : : : : : : 1 1 0 1 1 −58 1 0 0 MSB justified 1 1 0 1 not used 1 1 1 1 0 0 −59 1 1 0 not used 1 1 1 1 0 1 −60 1 1 1 not used 1 1 1 1 1 0 −∞ 1 1 1 1 1 1 −∞ 1997 Jul 09 12 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 BASS BOOST A 4-bit value to program the bass boost setting. The used set depends on the MODE bits. Table 11 Bass boost settings BASS BOOST BB3 BB2 BB1 BB0 FLAT SET (dB) MIN. SET (dB) MAX. SET (dB) 0 0 0 0 0 0 0 0 0 0 1 0 2 2 0 0 1 0 0 4 4 0 0 1 1 0 6 6 0 1 0 0 0 8 8 0 1 0 1 0 10 10 0 1 1 0 0 12 12 0 1 1 1 0 14 14 1 0 0 0 0 16 16 1 0 0 1 0 18 18 1 0 1 0 0 18 20 1 0 1 1 0 18 22 1 1 0 0 0 18 24 1 1 0 1 0 18 24 1 1 1 0 0 18 24 1 1 1 1 0 18 24 TREBLE A 2-bit value to program the treble setting. The used set depends on the MODE bits. Table 12 Treble settings TREBLE TR1 TR0 FLAT SET (dB) MIN. SET (dB) MAX. SET (dB) 0 0 0 0 0 0 1 0 2 2 1 0 0 4 4 1 1 0 6 6 1997 Jul 09 13 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 DE-EMPHASIS Table 15 The flat/min./max. switch A 2-bit value to enable the digital de-emphasis filter. Table 13 De-emphasis settings FUNCTION M1 M0 FUNCTION 0 0 flat 0 1 min. 1 0 min. 1 1 max. DE1 DE0 0 0 no de-emphasis 0 1 de-emphasis, 32 kHz 1 0 de-emphasis, 44.1 kHz POWER CONTROL 1 1 de-emphasis, 48 kHz A 2-bit value to disable the ADC and/or DAC to reduce power consumption. MUTE Table 16 Power control settings A 1-bit value to enable the digital mute. FUNCTION PC1 Table 14 Mute PC0 ADC DAC MT FUNCTION 0 0 off off 0 no muting 0 1 off on 1 muting 1 0 on off 1 1 on on MODE A 2-bit value to program the mode of the sound processing filters of Bass Boost and Treble. There are three modes: flat, min. and max. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground, VDDD = VDDA = VDDO = 3 V; Tamb = 25 °C; unless otherwise specified. SYMBOL VDDD Txtal(max) Tstg Tamb Ves PARAMETER CONDITIONS supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic handling note 1 note 2 note 3 MIN. MAX. − − −65 −20 −3000 −300 5.0 150 +125 +85 +3000 +300 UNIT V °C °C °C V V Notes 1. All VDD and VSS connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, except pins 24, 26 and 28 which can withstand ESD pulses of −1500 V to +1500 V. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1997 Jul 09 PARAMETER thermal resistance from junction to ambient in free air 14 VALUE UNIT 90 K/W Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 DC CHARACTERISTICS VDDD = VDDA = VDDO = 3 V; Tamb = 25 °C; RL = 5 kΩ; note 1; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDDA(ADC) VDDA(DAC) VDDO VDDD IDDA(ADC) IDDA(DAC) IDDO IDDD ADC analog supply voltage DAC analog supply voltage operational amplifiers supply voltage digital supply voltage ADC supply current operation mode ADC power-down DAC supply current operation mode DAC power-down operational amplifier supply current operation mode DAC power-down digital supply current operation mode DAC power-down ADC power-down 2.7 2.7 2.7 2.7 − − − − − − − − − 3.0 3.0 3.0 3.0 4.5 200 3.5 15 4 15 6 3 3 3.6 3.6 3.6 3.6 − − − − − − − − − V V V V mA µA mA µA mA µA mA mA mA 0.8VDDD −0.5 − − − − − − VDDD + 0.5 +0.2VDDD 10 10 V V µA pF Digital input pins VIH VIL ILI Ci HIGH level input voltage LOW level input voltage input leakage current input capacitance Digital output pins VOH VOL HIGH level output voltage LOW level output voltage IOH = −2 mA IOL = 2 mA 0.85VDDD − − − − 0.4 V V with respect to VSSA pin 4 1 kHz 0.45VDDA − − − 0.5VDDA 24 9.8 20 0.55VDDA − − − V kΩ kΩ pF with respect to VSSA pin 28 0.45VDDA − − − 0.5VDDA 28 0.13 0.22 0.55VDDA − 3.0 − V kΩ Ω mA 3 − − − − 200 kΩ pF Analog-to-digital converter Vref Ro(ref) Ri Ci reference voltage VrefA reference output resistance input resistance input capacitance Digital-to-analog converter Vref Ro(ref) Ro Io(max) reference voltage VrefD reference output resistance DAC output resistance maximum output current RL CL load resistance load capacitance (THD + N)/S < 0.1% RL = 5 kΩ note 2 Notes 1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. When higher capacitive loads must be driven then a 100 Ω resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier. 1997 Jul 09 15 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 AC CHARACTERISTICS (ANALOG) VDDD = VDDA = VDDO = 3 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog-to-digital converter Vi(rms) input voltage (RMS value) ∆Vi unbalance between channels − 0.8 − V − 0.1 − dB (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB − −85 −80 dB at −60 dB; A-weighted − −35 −30 dBA S/N signal-to-noise ratio Vi = 0 V; A-weighted − 95 − dBA αCS channel separation − 100 − dB PSRR power supply rejection ratio − 30 − dB fripple = 1 kHz; Vripple(p-p) = 30 mV Digital-to-analog converter Vo(rms) output voltage (RMS value) − 0.8 − V ∆Vo unbalance between channels − 0.1 − dB (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB − −85 −80 dB at −60 dB; A-weighted − −35 − dBA S/N signal-to-noise ratio code = 0; A-weighted − 100 − dBA αcs channel separation − 80 − dB PSRR power supply rejection ratio − 50 − dB 1997 Jul 09 fripple = 1 kHz; Vripple(p-p) = 100 mV 16 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = VDDO = 2.7 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL Tcy PARAMETER CONDITIONS clock cycle tCWL fsys LOW level pulse width tCWH fsys HIGH level pulse width MIN. TYP. MAX. UNIT fsys = 256fs 78 88 131 ns fsys = 384fs 52 59 87 ns fsys = 512fs 39 44 66 ns fsys < 19.2 MHz 30 − 70 %Tsys fsys ≥ 19.2 MHz 40 − 60 %Tsys fsys < 19.2 MHz 30 − 70 %Tsys fsys ≥ 19.2 MHz 40 − 60 %Tsys − − ns Serial input/output data timing; see Fig.7 tBCK bit clock period 1⁄ tBCK(H) bit clock HIGH time 100 − − ns tBCK(L) bit clock LOW time 100 − − ns tr rise time − − 20 ns tf fall time − − 20 ns ts;DATI data input set-up time 20 − − ns th;DATI data input hold time 0 − − ns td(DATO)(BCK) data output delay time (from BCK falling edge) − − 80 ns td(DATO)(WS) data output delay time (from WS edge) MSB-justified format − − 80 ns th;DATO data output hold time 0 − − ns ts;WS word selection set-up time 20 − − ns th;WS word selection hold time 10 − − ns 64fs Address and data transfer mode timing; see Figs 4 and 5 Tcy L3CLK cycle time 500 − − ns tHC L3CLK HIGH period 250 − − ns tLC L3CLK LOW period 250 − − ns ts;MA L3MODE set-up time address mode 190 − − ns th;MA L3MODE hold time address mode 190 − − ns ts;MT L3MODE set-up time data transfer mode 190 − − ns th;MT L3MODE hold time data transfer mode 190 − − ns ts;DAT L3DATA set-up time data transfer mode and address mode 190 − − ns th;DAT L3DATA hold time data transfer mode and address mode 30 − − ns thalt L3MODE halt time 190 − − ns 1997 Jul 09 17 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 handbook, full pagewidth WS tr tBCK(H) th;WS tf td(DATO)(BCK) ts;WS BCK tBCK(L) td(DATO)(WS) th;DATO Tcy DATAO ts;DATI th;DATI DATAI MGG840 Fig.7 Serial interface timing. 1997 Jul 09 18 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 APPLICATION INFORMATION VDDA 8LM32A07 R21 1Ω L2 VDDD 8LM32A07 C12 100 µF (16 V) ground C2 C11 100 µF (16 V) R24 R30 SYSCLK 47 Ω DATAO BCK WS DATAI OVERFL overload flag left input right input VDDD 100 µF (16 V) C21 C25 C29 100 nF (63 V) 100 nF (63 V) 100 nF (63 V) VSSD 2 1 R28 1Ω C9 100 µF (16 V) VSSA(ADC) VDDA(ADC) system clock handbook, full pagewidth VDDA L1 3V VADCN VADCP 6 7 VDDD 10 11 12 18 4 C22 100 nF (63 V) 16 17 C1 47 µF (16 V) X5 VINL C31 1 nF (63 V) 9 47 µF (16 V) UDA1340 3 24 R23 left output R22 10 kΩ C8 47 µF (16 V) X2 100 Ω R26 100 Ω R27 10 kΩ X3 right output R33 680 kΩ L3MODE L3CLOCK L3DATA 13 28 14 27 25 23 22 VDDO VSSA(DAC) C26 C27 100 nF (63 V) 100 nF (63 V) C7 C10 100 µF (16 V) R25 1Ω 100 µF (16 V) VDDO Fig.8 Application diagram. 19 Vref(D) C23 100 nF (63 V) 15 VSSO 1997 Jul 09 VOUTR VINR 5 C32 1 nF (63 V) C5 VOUTL 47 µF (16 V) R32 1 MΩ C6 C3 47 µF (16 V) 19 26 X4 Vref(A) C4 47 µF (16 V) MGK582 VDDA(DAC) R29 1Ω VDDA Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 1997 Jul 09 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AH 20 o Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1997 Jul 09 21 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Jul 09 22 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio CODEC with DSP features UDA1340 NOTES 1997 Jul 09 23 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA55 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547027/1200/02/pp24 Date of release: 1997 Jul 09 Document order number: 9397 750 02548