TI PADS5546IRGZT

ADS5546
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SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006
14-BIT, 190 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
FEATURES
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Maximum Sample Rate: 190 MSPS
14-Bit Resolution
No Missing Codes
Total Power Dissipation 1.1 W
Internal Sample and Hold
73.2-dBFS SNR at 70-MHz IF
87-dBc SFDR at 70-MHz IF, 0 dB gain
Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options
Programmable Gain up to 6 dB for SNR/SFDR
Trade-Off at High IF
Reduced Power Modes at Lower Sample
Rates
Supports input clock amplitude down to 400
mVPP
Clock Duty Cycle Stabilizer
No External Reference Decoupling Required
Internal and External Reference Support
Programmable Output Clock position to ease
data capture
3.3-V Analog and Digital Supply
48-QFN Package (7 mm × 7 mm)
APPLICATIONS
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Wireless Communications Infrastructure
Software Defined Radio
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Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
Medical Imaging
Radar Systems
DESCRIPTION
ADS5546 is a high performance 14-bit, 190-MSPS
A/D converter. It offers state-of-the art functionality
and performance using advanced techniques to
minimize board space. Using an internal sample and
hold and low jitter clock buffer, the ADC supports
both high SNR and high SFDR at high input
frequencies. It features programmable gain options
that can be used to improve SFDR performance at
lower full-scale analog input ranges.
In a compact 48-pin QFN, the device offers fully
differential LVDS DDR (Double Data Rate) interface
while parallel CMOS outputs can also be selected.
Flexible output clock position programmability is
available to ease capture and trade-off setup for hold
times. At lower sampling rates, the ADC can be
operated at scaled down power with no loss in
performance. ADS5546 includes an internal
reference, while eliminating the traditional reference
pins and associated external decoupling. The device
also supports an external reference mode.
The device is specified over
temperature range (-40°C to 85°C).
the
industrial
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
ADS5546
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SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
CLKP
DRGND
DRVDD
AGND
AVDD
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
CLKOUTP
CLOCKGEN
CLKM
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
Digital
Encoder
and
Serializer
INP
14-Bit
ADC
SHA
INM
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
VCM
Control
Interface
Reference
D12_D13_P
D12_D13_M
OVR
MODE
OE
DFS
RESET
SEN
SDATA
SCLK
IREF
ADS5546
LVDS MODE
B0095-01
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
ADS5546
QFN-48 (2)
(1)
(2)
2
PACKAGE
DESIGNATOR
RGZ
SPECIFIED
TEMPERATURE
RANGE
–40°C to 85°C
PACKAGE
MARKING
AZ5546
ORDERING
NUMBER
TRANSPORT
MEDIA,
QUANTITY
ADS5546IRGZT
Tape and Reel,
250
ADS5546IRGZR
Tape and Reel,
2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 25.41°C/W (0 LFM air flow), θJC
= 16.5°C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in PCB.
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
Supply voltage range, AVDD
–0.3 V to 3.9
V
Supply voltage range, DRVDD
–0.3 V to 3.9
V
Voltage between AGND and DRGND
-0.3 to 0.3
V
Voltage between AVDD to DRVDD
-0.3 to 3.3
V
Voltage applied to VCM pin (in external reference mode)
-0.3 to 1.8
V
–0.3 V to minimum (3.6, AVDD + 0.3 V)
V
Voltage applied to analog input pins, INP and INM
Voltage applied to input clock pins, CLKP and CLKM
TA
Operating free-air temperature range
TJ
Operating junction temperature range
Tstg
Storage temperature range
(1)
-0.3 V to AVDD + 0.3 V
V
–40 to 85
°C
125
°C
–65 to 150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
Analog supply voltage, AVDD
3
3.3
3.6
V
Digital supply voltage, DRVDD
3
3.3
3.6
V
SUPPLIES
ANALOG INPUTS
Differential input voltage range
2
VPP
1.5 ±0.1
Input common-mode voltage
Voltage applied on VCM in external reference mode
1.45
1.5
V
1.55
V
50
190
MSPS
1
60
CLOCK INPUT
Input clock sample rate
DEFAULT SPEED mode
LOW SPEED mode
Input clock amplitude differential (V(CLKP) - V(CLKM))
Sine wave, ac-coupled
1.5
VPP
LVPECL, ac-coupled
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
3.3
V
Input clock duty cycle (See Figure 34)
0.4
35%
50%
65%
DIGITAL OUTPUTS
CL
Maximum external load capacitance from each output pin to DRGND (LVDS and
CMOS modes)
RL
Differential load resistance between the LVDS output pairs (LVDS mode)
Operating free-air temperature
5
Ω
100
–40
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pF
85
°C
3
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SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
RESOLUTION
TYP
MAX
UNIT
14
bits
Differential input voltage range
2
VPP
Differential input capacitance
7
pF
ANALOG INPUT
Analog input bandwidth
–3 dB, source impedance 50 Ω
Analog input common mode current
(per input pin)
500
MHz
310
µA
REFERENCE VOLTAGES
V(REFB)
Internal reference bottom voltage
Internal reference mode
0.5
V
V(REFT)
Internal reference top voltage
Internal reference mode
2.5
V
VCM
Common mode output voltage
Internal reference mode
1.5
V
VCM output current capability
Internal reference mode
±4
mA
DC ACCURACY
No Missing Codes
DNL
Differential non-linearity
INL
Integral non-linearity
Specified
Offset error
0.5
2.5
LSB
–5
±3
5
LSB
5
Offset temperature coefficient
mV
0.002
ppm/°C
±1
Gain error
Gain temperature coefficient
PSRR
–0.9
DC Power supply rejection ratio
%FS
0.01
∆%/°C
0.6
mV/V
POWER SUPPLY
I(AVDD)
I(DRVDD)
ICC
4
Analog supply current
Digital supply current
291
mA
LVDS mode, IO = 3.5 mA,
RL = 100 Ω, CL = 5 pF
51
mA
CMOS mode, FIN = 2.5 MHz,
CL = 5 pF
43
mA
mA
Total supply current
LVDS mode
342
Total power dissipation
LVDS mode
1.13
1.29
W
Standby power
In STANDBY mode with clock
running
100
150
mW
Clock stop power
With input clock stopped
100
150
mW
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ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC CHARACTERISTICS
FIN = 10 MHz
73.8
FIN = 40 MHz
73.6
FIN = 70 MHz
SNR
Signal to noise ratio
73
FIN = 150 MHz
72.2
FIN = 300 MHz
0 dB gain, 2 VPP FS (1)
71
3 dB gain, 1.4 VPP FS
69.8
0 dB gain, 2 VPP FS
69
Inputs tied to common-mode
1.1
FIN = 10 MHz
90
77
FIN = 100 MHz
FIN = 300 MHz
84
0 dB gain, 2 VPP FS
75
3 dB gain, 1.4 VPP FS
78
0 dB gain, 2 VPP FS
72
3 dB gain, 1.4 VPP FS
73.5
FIN = 40 MHz
73.1
FIN = 70 MHz
71
FIN = 100 MHz
Signal to noise and distortion ratio
FIN = 300 MHz
71.8
0 dB gain, 2 VPP FS
Second harmonic
68.5
0 dB gain, 2 VPP FS
67.8
3 dB gain, 1.4 VPP FS
67.5
FIN = 10 MHz
92
FIN = 40 MHz
91
90
89
FIN = 150 MHz
87
FIN = 300 MHz
(1)
77
FIN = 100 MHz
FIN = 225 MHz
dBFS
69
3 dB gain, 1.4 VPP FS
FIN = 70 MHz
HD2
72.8
72.1
FIN = 150 MHz
FIN = 225 MHz
dBc
75
FIN = 10 MHz
SINAD
87
84
FIN = 150 MHz
FIN = 225 MHz
LSB
89
FIN = 70 MHz
Spurious free dynamic range
dBFS
70
3 dB gain, 1.4 VPP FS
FIN = 40 MHz
SFDR
73.5
FIN = 100 MHz
FIN = 225 MHz
RMS output noise
71.5
0 dB gain, 2 VPP FS
76
3 dB gain, 1.4 VPP FS
79
0 dB gain, 2 VPP FS
73
3 dB gain, 1.4 VPP FS
75
dBc
FS = Full scale range
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ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
FIN = 10 MHz
84
84
0 dB gain, 2 VPP FS
75
3 dB gain, 1.4 VPP FS
78
0 dB gain, 2 VPP FS
72
3 dB gain, 1.4 VPP FS
74
FIN = 10 MHz
93
FIN = 40 MHz
92
FIN = 70 MHz
91
FIN = 100 MHz
90
FIN = 150 MHz
89
FIN = 225 MHz
87
FIN = 300 MHz
87
FIN = 10 MHz
85
FIN = 40 MHz
85
FIN = 70 MHz
THD
Total harmonic distortion
IMD
PSRR
6
Effective number of bits
Two-tone intermodulation distortion
75
81
FIN = 150 MHz
80
FIN = 225 MHz
72
FIN = 10 MHz
FIN1 = 50.09 MHz, FIN2 = 46.09 MHz, -7 dBFS
each tone
dBc
dBc
83
FIN = 100 MHz
FIN = 300 MHz
ENOB
87
FIN = 150 MHz
FIN = 300 MHz
Worst harmonic (other than HD2, HD3)
77
FIN = 100 MHz
FIN = 225 MHz
UNIT
89
FIN = 70 MHz
Third harmonic
MAX
90
FIN = 40 MHz
HD3
TYP
dBc
68
11.8
bits
95
dBFS
FIN1 = 135.08 MHz, FIN2 = 130.08 MHz, -7 dBFS
each tone
89
AC power supply rejection ratio
30 MHz, 200 mVPP signal on 3.3-V supply
35
dBc
Voltage overload recovery time
Recovery to 1% (of final value) for 6-dB overload
with sine-wave input at Nyquist frequency
1
Clock
cycles
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DIGITAL CHARACTERISTICS
(1)
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
33
µA
Low-level input current
–33
µA
4
pF
High-level output voltage
3.3
V
Low-level output voltage
0
V
2
pF
1375
mV
1025
mV
350
mV
1200
mV
2
pF
Input capacitance
DIGITAL OUTPUTS – CMOS MODE
Output capacitance
Output capacitance inside the device, from each output to
ground
DIGITAL OUTPUTS – LVDS MODE
High-level output voltage
Low-level output voltage
Output differential voltage, |VOD|
225
VOS Output offset voltage, single-ended
Common-mode voltage of OUTP and OUTM
Output capacitance
Output capacitance inside the device, from either output to
ground
(1)
(2)
All LVDS and CMOS specifications are characterized, but not tested at production.
IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA,
RL = 100 Ω (3), no internal termination, unless otherwise noted.
For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ta
Aperture delay
1.2
ns
tj
Aperture jitter
150
fs rms
Wake-up time
Time to valid data after coming out of
STANDBY mode
100
Time to valid data after stopping and restarting
the input clock
100
µs
Latency
14
clock
cycles
DDR LVDS MODE (4)
Data setup time (5)
Data valid
1.2
1.7
ns
th
Data hold time (5)
Zero-cross of CLKOUTP to data becoming
invalid (6)
0.4
0.9
ns
tPDI
Clock propagation delay
Input clock rising edge zero-cross to output
clock rising edge zero-cross
4
4.7
tsu
(1)
(2)
(3)
(4)
(5)
(6)
(6)
to zero-cross of CLKOUTP
5.4
ns
Timing parameters are specified by design and characterization and not tested in production.
CL is the effective external single-ended load capacitance between each output pin and ground.
IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load.
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margin.
Data valid refers to logic high of +50 mV and logic low of –50 mV.
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
45%
50%
55%
UNIT
LVDS bit clock duty cycle
Duty cycle of differential clock,
(CLKOUTP-CLKOUTM)
80 ≤ Fs ≤ 190 MSPS
tr ,
tf
Data rise time,
Data fall time
Rise time measured from –50 mV to 50 mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 190 MSPS
50
100
200
ps
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from –50 mV to 50 mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 190 MSPS
50
100
200
ps
tOE
Output enable (OE) to valid data
delay
Time to valid data after OE becomes active
1
µs
PARALLEL CMOS MODE
tsu
(5)
(5)
Data valid (7) to 50% of CLKOUT rising edge
2.2
3
ns
50% of CLKOUT rising edge to data becoming
invalid (7)
0.5
0.9
ns
2.4
3.2
th
Data hold time
tPDI
Clock propagation delay
Input clock rising edge zero-cross to 50% of
CLKOUT rising edge
Output clock duty cycle
Duty cycle of output clock (CLKOUT)
80 ≤ Fs ≤ 190 MSPS
tr,
tf
Data rise time,
Data fall time
Rise time measured from 20% to 80% of
DRVDD
Fall time measured from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 190 MSPS
0.8
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from 20% to 80% of
DRVDD
Fall time measured from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 190 MSPS
0.4
tOE
Output enable (OE) to valid data
delay
Time to valid data after OE becomes active
(7)
8
Data setup time
Data valid refers to logic high of 2 V and logic low of 0.8 V
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4
ns
1.5
2
ns
0.8
1.2
ns
50
ns
45%
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N+4
N+3
N+2
N+1
Sample
N
N+17
N+16
N+15
N+14
Input
Signal
ta
Input
Clock
CLKP
CLKM
CLKOUTM
CLKOUTP
tsu
Output Data
DXP, DXM
E
E
O
E – Even Bits D0,D2,D4,D6,D8,D10,D12
O – Odd Bits D1,D3,D5,D7,D9,D11,D13
O
N–14
E
O
N–13
E
E
O
N–12
tPDI
th
14 Clock Cycles
DDR
LVDS
E
O
N–11
E
O
N–10
O
E
O
N
N–1
E
E
O
O
N+2
N+1
tPDI
CLKOUT
tsu
Parallel
CMOS
14 Clock Cycles
Output Data
D0–D13
N–13
N–14
N–12
th
N–11
N–10
N
N–1
N+1
N+2
Figure 1. Latency
Input
Clock
CLKM
CLKP
tPDI
Output
Clock
CLKOUTP
CLKOUTM
tsu
th
tsu
Output
Data Pair
(1)
(2)
Dn
Dn_Dn+1_P,
Dn_Dn+1_M
th
Dn
(1)
Dn+1
(2)
– Bits D0, D2, D4, D6, D8, D10, D12
Dn+1 – Bits D1, D3, D5, D7, D9, D11, D13
T0106-01
Figure 2. LVDS Mode Timing
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CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
th
tsu
Output
Data
Dn
Dn
(1)
(1)
Dn – Bits D0–D13
T0107-01
Figure 3. CMOS Mode Timing
10
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DEVICE PROGRAMMING MODES
ADS5546 offers flexibility with several programmable features that are easily configured.
The device can be configured independently using either a parallel interface control or a serial interface
programming.
In addition, the device supports a third mode, where both the parallel interface and the serial control registers
are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority table
(Table 2). If this additional level of flexibility is not required, the user can select either the serial interface
programming or the parallel interface control.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using the parallel interface, keep RESET tied to high (DRVDD). Pins DFS, MODE, SEN,
SCLK, and SDATA are used to directly control certain modes of the ADC. The device is configured by
connecting the parallel pins to the correct voltage levels (as described in Table 4 to Table 7). There is no need
to apply reset.
In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions are
controlled in this mode—standby, selection between LVDS/CMOS output format, internal/external reference,
two's complement/straight binary output format, and position of the output clock edge.
Table 1 has a description of the modes controlled by the four parallel pins.
Table 1. Parallel Pin Definition
PIN
DFS
MODE
CONTROL MODES
DATA FORMAT and the LVDS/CMOS output interface
Internal or external reference
SEN
CLKOUT edge programmability
SCLK
LOW SPEED mode control for low sampling frequencies (< 50 MSPS)
SDATA
STANDBY mode – Global (ADC, internal references and output buffers are powered down)
USING SERIAL INTERFACE PROGRAMMING ONLY
To program using the serial interface, the internal registers must first be reset to their default values, and the
RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are
used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET
pin, or by a high setting on the <RST> bit (D1 in register 0x6C). The serial interface section describes the
register programming and register reset in more detail.
Since the parallel pins DFS and MODE are not used in this mode, they must be tied to ground.
USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (DFS, MODE) can
also be used to configure the device.
The serial registers must first be reset to their default values, and the RESET pin must be kept low. In this mode
SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.
The registers are reset either by applying a pulse on RESET pin or by a high setting on the <RST> bit (D1 in
register 0x6C). The serial interface section describes the register programming and register reset in more detail.
The parallel interface control pins DFS and MODE are used, and their function is determined by the appropriate
voltage levels as described in Table 6 and Table 7. The voltage levels are derived by using a resistor string as
illustrated in Figure 4. Since some functions are controlled using both the parallel pins and serial registers, the
priority between the two is determined by a priority table (Table 2).
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Table 2. Priority Between Parallel Pins and Serial Registers
PIN
MODE
FUNCTIONS SUPPORTED
PRIORITY
Internal/External reference
When using the serial interface, bit <REF> (register 0x6D, bit D4) controls this mode, ONLY
if the MODE pin is tied low.
DATA FORMAT
When using the serial interface, bit <DF> (register 0x63, bit D3) controls this mode, ONLY if
the DFS pin is tied low.
LVDS/CMOS
When using the serial interface, bit <ODI> (register 0x6C, bits D3-D4) controls LVDS/CMOS
selection independent of the state of DFS pin
DFS
AVDD
(2/3) AVDD
R
(2/3) AVDD
GND
R
AVDD
(1/3) AVDD
(1/3) AVDD
R
To Parallel Pin
Figure 4. Simple Scheme to Configure Parallel Pins
12
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DESCRIPTION OF PARALLEL PINS
Table 3. SCLK Control Pin
SCLK (Pin 29)
0
DRVDD
DESCRIPTION
DEFAULT SPEED - Must be used for sampling frequency > 50 MSPS
LOW SPEED - Must be used for sampling frequency <= 50 MSPS
Table 4. SDATA Control Pin
SDATA (Pin 28)
0
DRVDD
DESCRIPTION
Normal operation (Default)
STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.
Table 5. SEN Control Pin
SEN (Pin 27)
CMOS mode: CLKOUT edge later by (3/12)Ts
(1);
LVDS mode: CLKOUT edge aligned with data transition
(1/3)DRVDD
CMOS mode: CLKOUT edge later by (2/12)Ts
(1);
LVDS mode: CLKOUT edge aligned with data transition
(2/3)DRVDD
CMOS mode: CLKOUT edge later by (1/12)Ts
(1);
LVDS mode: CLKOUT edge earlier by (1/12)Ts
DRVDD
(1)
DESCRIPTION
0
(1)
Default CLKOUT position
Ts = 1/Sampling Frequency
Table 6. DFS Control Pin
DFS (Pin 6)
0
DESCRIPTION
2's complement data and DDR LVDS output (Default)
(1/3)DRVDD
2's complement data and parallel CMOS output
(2/3)DRVDD
Offset binary data and parallel CMOS output
DRVDD
Offset binary data and DDR LVDS output
Table 7. MODE Control Pin
MODE (Pin 23)
DESCRIPTION
0
Internal reference
(1/3)AVDD
External reference
(2/3)AVDD
External reference
AVDD
Internal reference
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET
(of width greater than 10 ns).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in
multiples of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits form the register data.
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REGISTER INITIALIZATION
After power-up, the internal registers must be reset to their default values. This is done in one of two ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as
shown in Figure 5.
OR
2. By applying software reset. Using the serial interface, set the <RST> bit (D1 in register 0x6C) to high. This
initializes the internal registers to their default values and then self-resets the <RST> bit to low. In this case
the RESET pin is kept low.
Register Address
SDATA
A7
A6
A5
A4
A3
A2
Register Data
A1
A0
D7
t(SCLK)
D6
D5
D4
D3
D2
D1
D0
t(DH)
t(DSU)
SCLK
t(SLOADH)
t(SLOADS)
SEN
RESET
T0109-01
Figure 5. Serial Interface Timing Diagram
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
MIN
tSCLK
SCLK period
TYP
50
SCLK duty cycle
MAX
UNIT
ns
50%
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
14
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RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t1
Power-on delay
Delay from power-up of AVDD and DRVDD to RESET pulse active
MIN
t2
Reset pulse width
t3
tPO
TYP
MAX
UNIT
5
ms
Pulse width of active RESET signal
10
ns
Register write delay
Delay from RESET disable to SEN active
25
ns
Power-up time
Delay from power-up of AVDD and DRVDD to output stable
6.5
ms
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
T0108-01
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 6. Reset Timing Diagram
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DESCRIPTION OF SERIAL REGISTERS
Table 8 gives a summary of all the modes that can be programmed through the serial interface.
Table 8. Serial Interface Register Map
REGISTER ADDRESS
A7
A6
A5
A4
A3
A2
REGISTER DATA
A1
A0
D7
D6
D5
D4
D3
D2
D1
DESCRIPTION
D0
<STBY> – Global Power Down
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
NORMAL converter operation (Default after
reset)
0
0
0
0
0
0
STANDBY
1
0
Resets all registers to default values
<RST> – Software Reset
0
1
1
0
1
1
0
0
0
0
0
0
0
0
<DF> – Output Data Format
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
2's complement output format (Default after
reset)
0
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
Straight binary output format
<ODI> – Output Data Interface
0
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
DDR LVDS outputs (D4:D3 defaults to 00
after reset)
0
1
1
0
1
1
0
0
0
0
0
1
1
0
0
0
Parallel CMOS outputs
<REF> –Internal/External reference mode
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
Internal reference (Default after reset)
0
1
1
0
1
1
0
1
0
0
0
1
0
0
0
0
External reference – Force voltage on VCM
pin
0
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
Normal operation (Default after reset)
0
1
1
0
0
1
0
1
0
0
1
0
0
0
0
0
All zeros
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
All ones
0
1
1
0
0
1
0
1
0
1
1
0
0
0
0
0
Toggle pattern Alternate 1s and 0s on each
data output and across the data outputs.
0
1
1
0
0
1
0
1
1
0
0
0
0
0
0
0
Ramp pattern – Output data ramps from
0x0000 to 0x3FFF every clock cycle
0
1
1
0
0
1
0
1
1
0
1
0
0
0
0
0
Custom pattern. Write the custom pattern in
CUSTOM PATTERN registers A and B.
0
1
1
0
0
1
0
1
X
X
X
0
0
0
0
0
NOT USED
<TEST PATTERN> – Output test pattern on data outputs
<CUSTOM PATTERN> – Output custom pattern on data outputs
0
1
1
0
1
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0 CUSTOM PATTERN D7-D0
0
1
1
0
1
0
1
0
0
0
D13
D12
D11
D10
D9
D8 CUSTOM PATTERN D13-D8
<CLK GAIN> – Clock Buffer gain programmability, Gain decreases monotonically from Gain 4 to Gain 0
0
1
1
0
1
0
1
1
0
0
1
1
0
0
1
0
Gain 4
0
1
1
0
1
0
1
1
0
0
1
0
1
0
1
0
Gain 3
0
1
1
0
1
0
1
1
0
0
1
0
0
1
1
0
Gain 2
0
1
1
0
1
0
1
1
0
0
1
0
0
0
0
0
Gain 1 (Default after reset)
0
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
Gain 0 Minimum gain
<POWER SCALING> Power scaling vs sampling frequency. The ADC can be operated at reduced power at lower sampling rates
with no loss in performance.
16
0
1
1
0
1
1
0
1
0
0
1
0
0
0
0
0
Default Fs > 150 MSPS (Default after reset)
0
1
1
0
1
1
0
1
1
0
1
0
0
0
0
0
Power Mode 1 – 105 < Fs ≤ 150 MSPS
0
1
1
0
1
1
0
1
0
1
1
0
0
0
0
0
Power Mode 2 – 50 < Fs ≤ 105 MSPS
0
1
1
0
1
1
0
1
1
1
1
0
0
0
0
0
Power Mode 3 – Fs ≤ 50 MSPS
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Table 8. Serial Interface Register Map (continued)
REGISTER ADDRESS
A7
A6
A5
A4
A3
A2
REGISTER DATA
A1
A0
D7
D6
D5
D4
D3
D2
D1
DESCRIPTION
D0
<GAIN> Gain programming - Channel gain can be programmed from 0 to 6 dB for SFDR/SNR trade-off. For each gain setting, the
input full-scale range has to be proportionally scaled. For 6 dB gain, the full-scale range will be 1 VPP compared to 2 VPP at 0 dB
gain.
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0 dB (Default after reset)
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
0
1
0
2 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
0
1
1
3 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
0
4 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
1
5 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
0
6 dB
<LVDS CURRENT> – LVDS Output data and clock buffers nominal current programmability
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
3.5 mA (Default after reset)
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
2.5 mA
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
4.5 mA
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1.75 mA
<CURRENT DOUBLE> – The output data and clock buffer currents are doubled from the value selected by the <LVDS CURRENT>
register.
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
value specified by <LVDS CURRENT>
(Default after reset)
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
2x data, 2x clock currents
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1x data, 2x clock currents
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2x data, 4x clock currents
<DATA TERM> Internal termination - Option to terminate the LVDS DATA buffers inside the ADC to improve signal integrity. By
default, internal termination is disabled.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
No termination (Default after reset)
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
325 Ω
0
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
200 Ω
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
125 Ω
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
170 Ω
0
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
120 Ω
0
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
100 Ω
0
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
75 Ω
<CLK TERM> Internal termination - Option to terminate the LVDS CLK buffers inside the ADC to improve signal integrity. By
default, internal termination is disabled.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
No termination (Default after reset)
0
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
325 Ω
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
200 Ω
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
125 Ω
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
170 Ω
0
1
1
1
1
1
1
0
0
0
0
1
0
1
0
0
120 Ω
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
100 Ω
0
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
75 Ω
<CLKOUT POSN CMOS> – Output clock rising edge programmability in CMOS mode
(1)
(1)
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
Default position
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
1
CLKOUT rising edge later by (1/12)Ts
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
1
CLKOUT rising edge later by (3/12)Ts
0
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
CLKOUT rising edge later by (2/12)Ts
Ts = 1/Sampling Frequency
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Table 8. Serial Interface Register Map (continued)
REGISTER ADDRESS
A7
A6
A5
A4
A3
A2
REGISTER DATA
A1
A0
D7
D6
D5
D4
D3
D2
D1
DESCRIPTION
D0
<CLKOUT POSN CMOS> – Output clock falling edge programmability in CMOS mode
(2)
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
Default position
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
1
CLKOUT falling edge later by (1/12)Ts
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
1
CLKOUT falling edge later by (3/12)Ts
0
1
1
0
0
0
1
0
0
0
0
1
1
0
0
1
CLKOUT falling edge later by (2/12)Ts
<CLKOUT POSN LVDS> – Output clock rising edge programmability in LVDS mode
(2)
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
Default position
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
1
CLKOUT rising edge earlier by (1/12)Ts
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
1
CLKOUT rising edge aligned with data
transition
0
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
CLKOUT rising edge aligned with data
transition
<CLKOUT POSN LVDS> – Output clock falling edge programmability in LVDS mode
(2)
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
Default position
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
1
CLKOUT falling edge earlier by (1/12)Ts
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
1
CLKOUT falling edge aligned with data
transition
0
1
1
0
0
0
1
0
0
0
0
1
1
0
0
1
CLKOUT falling edge aligned with data
transition
<LOW SPEED> - For low sampling frequency operation
(2)
18
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
DEFAULT SPEED mode - for 50 <Fs ≤ 190
MSPS
0
1
1
0
0
0
1
1
0
0
0
1
0
0
0
0
LOW SPEED mode - for 1 ≤ Fs ≤ 50 MSPS
Ts = 1/Sampling Frequency
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PIN CONFIGURATION (LVDS MODE)
37 D2_D3_M
38 D2_D3_P
39 D4_D5_M
40 D4_D5_P
41 D6_D7_M
42 D6_D7_P
43 D8_D9_M
44 D8_D9_P
45 D10_D11_M
46 D10_D11_P
47 D12_D13_M
48 D12_D13_P
RGZ PACKAGE
(TOP VIEW)
DRGND 1
36 DRGND
DRVDD 2
35 DRVDD
OVR 3
34 D0_D1_P
CLKOUTM 4
33 D0_D1_M
CLKOUTP 5
32 NC
DFS 6
31 NC
OE 7
30 RESET
AVDD 8
29 SCLK
AGND 9
28 SDATA
AVDD 24
MODE 23
AVDD 22
IREF 21
AVDD 20
AGND 19
AVDD 18
25 AGND
AGND 17
AGND 12
INM 16
26 AVDD
INP 15
CLKM 11
AGND 14
27 SEN
VCM 13
CLKP 10
P0023-02
Figure 7. LVDS Mode Pinout
PIN ASSIGNMENTS – LVDS Mode
PIN NAME
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
AVDD
Analog power supply
I
8, 18, 20,
22, 24, 26
6
AGND
Analog ground
I
9, 12, 14,
17, 19, 25
6
CLKP, CLKM
Differential clock input
I
10, 11
2
INP, INM
Differential analog input
I
15, 16
2
VCM
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets
the internal references.
I/O
13
1
IREF
Current-set resistor, 56.2-kΩ resistor to ground.
I
21
1
RESET
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using
the software reset option. See the SERIAL INTERFACE section.
In parallel interface mode, the user has to tie the RESET pin permanently HIGH.
(SDATA and SEN are used as parallel pin controls in this mode)
The pin has an internal 100-kΩ pull-down resistor.
I
30
1
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PIN ASSIGNMENTS – LVDS Mode (continued)
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED mode control pin when RESET is tied high. Tie SCLK
to LOW for Fs > 50 MSPS and SCLK to HIGH for Fs ≤ 50 MSPS. See Table 3.
The pin has an internal 100-kΩ pull-down resistor.
I
29
1
I
28
1
SEN
This pin functions as serial interface enable input when RESET is low. It functions
as CLKOUT edge programmability when RESET is tied high. See Table 5 for
detailed information.
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
I
27
1
OE
Output buffer enable input, active high. The pin has an internal 100-kΩ pull-up
resistor to DRVDD.
I
7
1
DFS
Data Format Select input. This pin sets the DATA FORMAT (Twos complement or
Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed
information.
I
6
1
MODE
Mode select input. This pin selects the Internal or External reference mode. See
Table 7 for detailed information.
I
23
1
CLKOUTP
Differential output clock, true
O
5
1
CLKOUTM
Differential output clock, complement
O
4
1
D0_D1_P
Differential output data D0 and D1 multiplexed, true
O
34
1
D0_D1_M
Differential output data D0 and D1 multiplexed, complement.
O
33
1
D2_D3_P
Differential output data D2 and D3 multiplexed, true
O
38
1
D2_D3_M
Differential output data D2 and D3 multiplexed, complement
O
37
1
D4_D5_P
Differential output data D4 and D5 multiplexed, true
O
40
1
D4_D5_M
Differential output data D4 and D5 multiplexed, complement
O
39
1
D6_D7_P
Differential output data D6 and D7 multiplexed, true
O
42
1
D6_D7_M
Differential output data D6 and D7 multiplexed, complement
O
41
1
D8_D9_P
Differential output data D8 and D9 multiplexed, true
O
44
1
D8_D9_M
Differential output data D8 and D9 multiplexed, complement
O
43
1
D10_D11_P
Differential output data D10 and D11 multiplexed, true
O
46
1
D10_D11_M
Differential output data D10 and D11 multiplexed, complement
O
45
1
D12_D13_P
Differential output data D12 and D13 multiplexed, true
O
48
1
D12_D13_M
Differential output data D12 and D13 multiplexed, complement
O
47
1
OVR
Out-of-range indicator, CMOS level signal
O
3
1
DRVDD
Digital and output buffer supply
I
2, 35
2
DRGND
Digital and output buffer ground
I
1, 36
2
NC
Do not connect
31, 32
2
PIN NAME
SCLK
This pin functions as serial interface data input when RESET is low. It functions
as STANDBY control pin when RESET is tied high.
SDATA
See Table 4 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
20
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PIN CONFIGURATION (CMOS MODE)
37 D2
38 D3
39 D4
40 D5
41 D6
42 D7
43 D8
44 D9
45 D10
46 D11
47 D12
48 D13
RGZ PACKAGE
(TOP VIEW)
DRGND 1
36 DRGND
DRVDD 2
35 DRVDD
OVR 3
34 D1
UNUSED 4
33 D0
CLKOUT 5
32 NC
DFS 6
31 NC
OE 7
30 RESET
AVDD 8
29 SCLK
AGND 9
28 SDATA
AVDD 24
MODE 23
AVDD 22
IREF 21
AVDD 20
AGND 19
AVDD 18
25 AGND
AGND 17
AGND 12
INM 16
26 AVDD
INP 15
CLKM 11
AGND 14
27 SEN
VCM 13
CLKP 10
P0023-03
Figure 8. CMOS Mode Pinout
PIN ASSIGNMENTS – CMOS Mode
PIN NAME
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
AVDD
Analog power supply
I
8, 18, 20,
22, 24, 26
6
AGND
Analog ground
I
9, 12, 14, 17,
19, 25
6
CLKP, CLKM Differential clock input
I
10, 11
2
INP, INM
Differential analog input
I
15, 16
2
VCM
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets
the internal references.
I/O
13
1
IREF
Current-set resistor, 56.2-kΩ resistor to ground.
I
21
1
I
30
1
I
29
1
Serial interface RESET input.
RESET
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using
the software reset option. See the SERIAL INTERFACE section.
In parallel interface mode, the user has to tie RESET pin permanently HIGH.
(SDATA and SEN are used as parallel pin controls in this mode).
The pin has an internal 100-kΩ pull-down resistor.
SCLK
This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED mode control pin when RESET is tied high. Tie SCLK
to LOW for Fs > 50 MSPS and SCLK to HIGH for Fs ≤ 50 MSPS. See Table 3.
The pin has an internal 100-kΩ pull-down resistor.
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PIN ASSIGNMENTS – CMOS Mode (continued)
PIN NAME
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
I
28
1
I
27
1
This pin functions as serial interface data input when RESET is low. It functions as
STANDBY control pin when RESET is tied high.
SDATA
See Table 4 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
SEN
This pin functions as serial interface enable input when RESET is low. It functions
as CLKOUT edge programmability when RESET is tied high. See Table 5 for
detailed information.
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
OE
Output buffer enable input, active high. The pin has an internal 100-kΩ pull-up
resistor to DRVDD.
I
7
1
DFS
Data Format Select input. This pin sets the DATA FORMAT (Twos complement or
Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed
information.
I
6
1
MODE
Mode select input. This pin selects the internal or external reference mode. See
Table 7 for detailed information.
I
23
1
CLKOUT
CMOS output clock
O
5
1
D0
CMOS output data D0
O
33
1
D0
CMOS output data D1
O
34
1
D2
CMOS output data D2
O
37
1
D2
CMOS output data D3
O
38
1
D4
CMOS output data D4
O
39
1
D4
CMOS output data D5
O
40
1
D6
CMOS output data D6
O
41
1
D7
CMOS output data D7
O
42
1
D8
CMOS output data D8
O
43
1
D9
CMOS output data D9
O
44
1
D10
CMOS output data D10
O
45
1
D11
CMOS output data D11
O
46
1
D12
CMOS output data D12
O
47
1
D13
CMOS output data D13
O
48
1
OVR
Out-of-range indicator, CMOS level signal
O
3
1
DRVDD
Digital and output buffer supply
I
2, 35
2
DRGND
Digital and output buffer ground
I
1, 36
2
UNUSED
Unused pin in CMOS mode
4
1
NC
Do not connect
31, 32
2
22
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TYPICAL CHARACTERISTICS
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
FFT for 10 MHz INPUT SIGNAL
FFT for 40 MHz INPUT SIGNAL
0
0
SFDR = 91.4 dBc,
SNR = 74.2 dBFS,
SINAD = 74 dBFS
-40
SFDR = 89.2 dBc,
SNR = 74 dBFS,
SINAD = 73.7 dBFS
-20
Amplitude - dB
Amplitude - dB
-20
-60
-80
-100
-120
-40
-60
-80
-100
-120
-140
-140
0
10
20
30
40
50
60
70
80
0
90
10
20
f - Frequency - MHz
30
60
70
80
90
80
90
Figure 10.
FFT for 70 MHz INPUT SIGNAL
FFT for 100 MHz INPUT SIGNAL
0
0
SFDR = 87.8 dBc,
SNR = 73.7 dBFS,
SINAD = 73.3 dBFS
-40
SFDR = 86.9 dBc,
SNR = 73.2 dBFS,
SINAD = 72.8 dBFS
-20
Amplitude - dB
-20
Amplitude - dB
50
f - Frequency - MHz
Figure 9.
-60
-80
-100
-120
-40
-60
-80
-100
-120
-140
-140
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
f - Frequency - MHz
f - Frequency - MHz
Figure 11.
Figure 12.
FFT for 130 MHz INPUT SIGNAL
FFT for 150 MHz INPUT SIGNAL
0
0
SFDR = 86.5 dBc,
SNR = 72.8 dBFS,
SINAD = 72.3 dBFS
-40
SFDR = 85.2 dBc,
SNR = 72.4 dBFS,
SINAD = 71.9 dBFS
-20
Amplitude - dB
-20
Amplitude - dB
40
-60
-80
-100
-120
-40
-60
-80
-100
-120
-140
-140
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
f - Frequency - MHz
f - Frequency - MHz
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
FFT for 200 MHz INPUT SIGNAL
FFT for 225 MHz INPUT SIGNAL
0
0
SFDR = 77.2 dBc,
SNR = 71.7 dBFS,
SINAD = 69.4 dBFS
-40
SFDR = 74 dBc,
SNR = 71 dBFS,
SINAD = 69.9 dBFS
-20
Amplitude - dB
Amplitude - dB
-20
-60
-80
-100
-40
-60
-80
-100
-120
-120
-140
-140
0
10
20
30
40
50
60
70
80
0
90
10
20
30
Figure 15.
70
80
90
FFT for 375 MHz INPUT SIGNAL
0
0
SFDR = 72.1 dBc,
SNR = 70.1 dBFS,
SINAD = 66.3 dBFS
-40
SFDR = 65.6 dBc,
SNR = 68.7 dBFS,
SINAD = 62.3 dBFS
-20
Amplitude - dB
-20
Amplitude - dB
60
Figure 16.
FFT for 300 MHz INPUT SIGNAL
-60
-80
-100
-40
-60
-80
-100
-120
-120
-140
-140
0
10
20
30
40
50
60
70
80
0
90
10
20
30
40
50
60
70
80
90
f - Frequency - MHz
f - Frequency - MHz
Figure 17.
Figure 18.
FFT for 500 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
0
SFDR = 59 dBc,
SNR = 66 dBFS,
SINAD = 56.3 dBFS
-40
FIN1 = 50.09 MHz, -7 dBFS,
FIN2 = 46.09 MHz, -7 dBFS,
2-Tone IMD, 95 dBFS
-20
Amplitude - dB
-20
Amplitude - dB
50
f - Frequency - MHz
f - Frequency - MHz
-60
-80
-100
-120
-40
-60
-80
-100
-120
-140
-140
0
10
20
30
40
50
60
70
80
90
0
f - Frequency - MHz
10
20
30
40
50
60
f - Frequency - MHz
Figure 19.
24
40
Figure 20.
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80
90
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
SFDR vs INPUT FREQUENCY
94
0
FIN1 = 135.08 MHz, -7 dBFS,
FIN2 = 130.08 MHz, -7 dBFS,
2-Tone IMD, 89 dBFS
90
86
-40
SFDR - dBc
Amplitude - dB
-20
-60
-80
-100
82
78
74
70
66
-120
62
-140
58
0
10
20
30
40
50
60
70
80
0
90
50
100 150 200 250 300 350 400 450 500
fIN - Input Frequency - MHz
f - Frequency - MHz
Figure 21.
Figure 22.
SNR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
75
LVDS Mode
73
72
SNR − dBFS
SNR - dBFS
74
71
70
69
68
67
66
65
0
50
72
71
70
69
68
67
66
65
64
63
62
61
60
59
CMOS Mode
0
100 150 200 250 300 350 400 450 500
50 100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
fIN - Input Frequency - MHz
Figure 23.
Figure 24.
SNR vs GAIN
75
5 dB
0 dB
6 dB
4 dB
3 dB
2 dB
1 dB
Input Adjusted to -1 dBFS
for Each Gain Setting
30
50
70
74
1 dB
73
2 dB
72
3 dB
71
4 dB
70
5 dB
69
6 dB
68
0 dB
10
SNR − dBFS
SFDR − dBc
SFDR vs GAIN
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
67
10
30
90 110 130 150 170 190 210 230
50
70
90 110 130 150 170 190 210 230
fIN − Input Frequency − MHz
fIN − Input Frequency − MHz
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
PERFORMANCE vs AVDD
PERFORMANCE vs DRVDD
73.6
FIN = 70 MHz
DRVDD = 3.3 V
SNR
87
73.3
86
SFDR − dBc
73.4
88
3
3.1
3.2
3.3
3.4
3.5
73.2
87
86
73.1
85
72.4
72.0
3.1
3.2
3.4
3.5
Figure 27.
Figure 28.
PERFORMANCE vs TEMPERATURE
SNR vs SAMPLING FREQUENCY
ACROSS POWER SCALING MODES
90
73
74.5
87
74
86
SNR − dBFS
SFDR
88
SNR − dBFS
75
89
73.5
10
35
Default
71
Power Mode 1
70
Power Mode 3
69
Power Mode 2
73
85
50
72
68
SNR
−15
3.6
74
75.5
fIN = 70 MHz
SFDR − dBc
3.3
DRVDD − Supply Voltage − V
AVDD - Supply Voltage - V
85
−40
72.8
SNR
3.0
3.6
73.6
SFDR
88
73.2
SFDR
85
fIN = 70 MHz
AVDD = 3.3 V
89
73.5
SNR - dBFS
SFDR - dBc
89
74.0
90
SNR − dBFS
90
67
fIN = 70 MHz
66
40
TA − Free-Air Temperature − oC
60
80
100
120
140
160
180
200
Figure 30.
POWER DISSIPATION vs
SAMPLING FREQUENCY
PERFORMANCE vs
INPUT AMPLITUDE
105
LVDS Mode
75.0
95
Default
Power Mode 1
Power Mode 2
74.8
SFDR (dBFS)
85
75
74.5
74.3
SNR
74.0
65
73.8
55
SFDR (dBc)
45
73.5
35
25
−60
Power Mode 3
0
20
40
60
80 100
73.3
fIN = 10 MHz
−50
120 140 160 180 200
73.0
−40
−30
−20
Input Amplitude − dBFS
FS − Sampling Frequency − MSPS
Figure 31.
26
Figure 32.
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−10
0
SNR − dBFS
1.21
1.16
1.11
1.06
1.01
0.96
0.91
0.86
0.81
0.76
0.71
0.66
0.61
Figure 29.
SFDR − dBc, dBFS
PD − Power Dissipation − W
FS − Sampling Frequency − MSPS
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
PERFORMANCE vs CLOCK AMPLITUDE
84
90
75
0.64
0.94
1.24 1.54 1.84 2.14
Clock Amplitude - VPP
74.5
84
74.0
SNR
fIN = 150 MHz
Sine Wave Input Clock
76
86
80
30
70
2.74
2.44
73.5
82
71
73.0
35
40
45
55
60
65
Input Clock Duty Cycle − %
Figure 33.
Figure 34.
OUTPUT NOISE HISTOGRAM WITH
INPUTS SHORTED TO COMMON-MODE
PERFORMANCE IN EXTERNAL REFERENCE MODE
90
35
30
76
75
88
SFDR − dBc
25
20
15
10
SFDR
74
86
SNR
84
73
82
72
80
1.4
8200
8199
8198
8197
8196
8195
8194
71
1.45
1.5
1.55
1.6
Voltage Forced on the CM Pin − V
Output Code
Figure 35.
Figure 36.
COMMON-MODE REJECTION RATIO vs FREQUENCY
-35
-40
CMRR − dBc
8193
8192
0
8191
5
8190
Occurence − %
50
SNR − dBFS
77
SFDR
SNR − dBFS
72
78
SFDR − dBc
73
79
SNR - dBFS
SNR
80
75.0
88
74
82
81
75
74
0.34
75.5
FIN = 10 MHz
SFDR
83
SFDR - dBc
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
-45
-50
-55
-60
-65
-70
0
20
40
60
80
100
f - Frequency of AC Common-Mode Voltage - MHz
Figure 37.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS
data output (unless otherwise noted)
160
66
68
60
70
120
66
72
73
74
140
68
70
100
64
70
66
72
80
73
74
62
fS - Sampling Frequency - MSPS
62
70
72
74
180
73
190
65
64
68
10
50
100
150
200
250
300
350
400
450
500
72
74
fIN - Input Frequency - MHz
56
58
60
62
64
66
68
70
SNR - dBFS
Figure 38. SNR Contour in dBFS
70
80
85
190
55
65
85
85
85
75
80
90
85
60
75
160
50
65
85
55
90
70
60
90
70
75
90
120
85
70
140
90
100
70
80
fS - Sampling Frequency - MSPS
180
65
10
50
100
150
200
65
70
75
90
85
80
250
300
60
350
400
450
500
80
85
90
95
fIN - Input Frequency - MHz
45
50
55
60
65
70
75
SFDR - dBc
Figure 39. SFDR Contour in dBc
28
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APPLICATION INFORMATION
THEORY OF OPERATION
ADS5546 is a low power 14-bit 190 MSPS pipeline ADC in a CMOS process. ADS5546 is based on switched
capacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge of
the external input clock. Once the signal is captured by the input sample and hold, the input sample is
sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction
logic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of 14
clock cycles. The output is available as 14-bit data, in DDR LVDS or CMOS and coded in either straight offset
binary or binary 2’s complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 40. This differential topology results in good ac-performance even for high input frequencies at high
sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V
available on VCM pin 13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically
between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The maximum swing is
determined by the internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).
Sampling
Switch
Lpkg
6 nH
Sampling
Capacitor
R-C-R Filter
INP
Cbond
2 pF
25 W
Resr
200 W
4 pF
Lpkg
6 nH
Cpar2
1 pF
50 W
Ron
15 W
Ron
10 W
Cpar1
0.8 pF
50 W
Ron
15 W
25 W
Csamp
3.2 pF
Csamp
3.2 pF
INM
Cbond
2 pF
Resr
200 W
Sampling
Capacitor
Cpar2
1 pF
Sampling
Switch
Figure 40. Input Stage
The input sampling circuit has a 3-dB bandwidth that extends up to 500 MHz, see Figure 41 (measured from the
input pins to the voltage across the sampling capacitors).
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APPLICATION INFORMATION (continued)
ADC Input Impedance, ZI
2
500
0
450
400
350
-2
Magnitude − W
Magnitude − dB
Transfer Function - ADC Only
-4
-6
-8
-10
-12
-14
-16
0
100 200 300 400 500 600 700 800 900 1000
300
250
200
150
100
50
0
0
100 200 300 400 500 600 700 800 900 1000
f − Frequency − MHz
f − Frequency − MHz
Figure 41. Analog Input Bandwidth (Data From Actual
Silicon)
Figure 42. Impedance Looking Into INP, INM (Data From
Simulation)
Drive Circuit Requirements
A 5-Ω resistor in series with each input pin is recommended to damp out ringing caused by the package
parasitics. It is also necessary to present a low impedance (< 50 Ω) for the common-mode switching currents.
For example, this is achieved by using two resistors from each input terminated to the common-mode voltage
(VCM).
In addition to the above ADC requirements, the drive circuit may have to be designed to provide a low insertion
loss over the desired frequency range and matched impedance to the source. For this, the ADC input
impedance has to be considered, see Figure 42.
Example Drive Circuits
A configuration suitable for low input frequency ranges (< 100 MHz) is shown in Figure 43. Note the 5-Ω series
resistors and the low common-mode impedance (using 25-Ω resistors terminated to VCM). In addition, the circuit
has low insertion loss, and good impedance match at low input frequencies, see Figure 44.
ADS5546
0.1 mF
ADT1-1T
5W
INP
0.1 mF
25 W
25 W
INM
5W
1:1
S11, ZI
VCM
Figure 43. Configuration for Low Input Frequencies
30
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APPLICATION INFORMATION (continued)
S11
0
-10
S11 − dB
-20
-30
-40
S(1, 1)
-50
-60
-70
0
50
100
150
200
250
f − Frequency − MHz
Transfer Function − Source To ADC Output
(Including the Transformer)
Frequency (100 kHz to 500 MHz)
3
Frequency = 100 MHz
S(1, 1) = 0.11/-1.19E2
Impedance = 44.07 - j8.63
Magnitude − dB
1
-1
-3
-5
-7
-9
0
50
100
150
200
250
f − Frequency − MHz
Figure 44. S11, Input Impedance and Transfer Function for the Configuration in Figure 43
For high input frequencies, the previous configuration has been modified to improve the insertion loss and
impedance matching (see Figure 45). The S11 curve shows that the matching is good from 100 MHz to
300 MHz.
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APPLICATION INFORMATION (continued)
ADS5546
TC4-1W
0.1 mF
12 nH
(Note A)
TC4-1W
5W
INP
0.1 mF
50 W
50 W
INM
1:2
12 nH
(Note A)
2:1
5W
S11, ZI
A.
VCM
Includes transformer leakage inductances.
Figure 45. Configuration for Higher Input Frequencies
S11
0
-5
S11 − dB
-10
S(1, 1)
-15
-20
-25
0
100 200 300 400 500 600 700 800 900 1000
f − Frequency − MHz
Transfer Function − Source to ADC Output
(Including the Transformer)
Frequency (100 kHz to 500 MHz)
2
Frequency = 200 MHz
S(1, 1) = 0.09/50.92
Impedance = 55.57 + j8.03
Magnitude − dB
0
-2
-4
-6
-8
-10
0
50
100 150 200 250 300 350 400 450 500
f − Frequency − MHz
Figure 46. S11, Input Impedance and Transfer Function for the Configuration in Figure 45
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APPLICATION INFORMATION (continued)
Using RF Transformer-Based Drive Circuits
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection. Some examples of input configurations using RF
transformers suitable for low and high input frequencies are shown in Figure 45 and Figure 46.
The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on
the secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the
sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two
resistors connected in series, with the center point connected to the 1.5 V common-mode (VCM pin 13). The
value of the termination resistors (connected to common-mode) has to be low (< 100 Ω) to provide a
low-impedance path for the ADC common-mode switching current.
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results
in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps
minimize this mismatch, and good performance is obtained for high frequency input signals. An additional
termination resistor pair (enclosed within the shaded box in Figure 45) may be required between the two
transformers to improve the balance between the P and M sides. The center point of this termination must be
connected to ground. (Note that the drive circuit has to be tuned to account for this additional termination, to get
the desired S11 and impedance match).
Input Common-Mode
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC
sinks a common-mode current in the order of 310 µA (at 190 MSPS). Equation 1 describes the dependency of
the common-mode current and the sampling frequency.
(310 mA) x Fs
190 MSPS
(1)
This equation helps to design the output capability and impedance of the CM driving circuit accordingly.
Reference
ADS5546 has built-in internal references REFP and REFM, requiring no external components. Design schemes
are used to linearize the converter load seen by the references; this and the integration of the requisite
reference capacitors on-chip eliminates the need for external decoupling. The full-scale input range of the
converter can be controlled in the external reference mode as explained below. The internal or external
reference modes can be selected by controlling the MODE pin 23 (see Table 7 for details) or by programming
the serial interface register bit <REF>.
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APPLICATION INFORMATION (continued)
INTREF
Internal
Reference
VCM
INTREF
EXTREF
REFM
REFP
ADS5546
S0165-01
Figure 47. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.
Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog
input pins.
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on
the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input voltage corresponding to full-scale is given by Equation 2.
Full−scale differential input pp + (Voltage forced on VCM) 1.33
(2)
In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is no
change in performance compared to internal reference mode.
Low Sampling Frequency Operation
For best performance at high sampling frequencies, ADS5546 uses a clock generator circuit to derive internal
timing for the ADC. The clock generator operates from 190 MSPS down to 50 MSPS in the DEFAULT SPEED
mode. The ADC enters this mode after applying reset (with serial interface configuration) or by tying SCLK pin to
low (with parallel configuration).
For low sampling frequencies (below 50 MSPS), the ADC must be put in the LOW SPEED mode. This mode
can be entered by:
• setting the register bit <LOW SPEED> through the serial interface, OR
• tying the SCLK pin to high (see Table 3) using the parallel configuration.
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APPLICATION INFORMATION (continued)
Clock Input
ADS5546 clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between configurations. The common-mode voltage of the clock inputs is
set to VCM using internal 5-kΩ resistors as shown in Figure 48. This allows the use of transformer-coupled drive
circuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources (Figure 49 and Figure 50)
VCM
VCM
5 kW
5 kW
CLKP
CLKM
ADS5546
S0166-01
Figure 48. Internal Clock Buffer
For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to
common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with
0.1-µF capacitors, as shown in Figure 49.
0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS
Clock Input
0.1 mF
CLKM
ADS5546
Figure 49. Differential Clock Driving Circuit
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APPLICATION INFORMATION (continued)
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground with
a 0.1-µF capacitor, as shown in Figure 50.
0.1 mF
CMOS Clock Input
CLKP
0.1 mF
CLKM
ADS5546
Figure 50. Single-Ended Clock Driving Circuit
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, the use a clock source with very low jitter is recommended. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input. Figure 34 shows the performance variation of the ADC versus clock duty cycle
Clock Buffer Gain
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is
increased. Therefore, using a large amplitude clock is recommended. In addition, the clock buffer has a
programmable gain option to amplify the input clock. The clock buffer gain can be set by programming the
register bits <CLK GAIN>. The clock buffer gain decreases monotonically from Gain 4 to Gain 0 settings.
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APPLICATION INFORMATION (continued)
Table 9. Clock Buffer Gain Programming
REGISTER ADDRESS
A7
A6
A5
A4
A3
A2
REGISTER DATA
A1
A0
D7
D6
D5
D4
D3
DESCRIPTION
D2
D1
D0
<CLK GAIN> – Clock buffer gain programmability, Gain decreases monotonically from Gain 4 to Gain 0
0
1
1
0
1
0
1
1
0
0
1
1
0
0
1
0
Gain 4
0
1
1
0
1
0
1
1
0
0
1
0
1
0
1
0
Gain 3
0
1
1
0
1
0
1
1
0
0
1
0
0
1
1
0
Gain 2
0
1
1
0
1
0
1
1
0
0
1
0
0
0
0
0
Gain 1 Default gain
0
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
Gain 0 Minimum gain
Programmable Gain
ADS5546 has programmable gain from 0 dB to 6 dB in steps of 1 dB. The corresponding full-scale input range
varies from 2 VPP down to 1 VPP, with 0 dB being the default gain. At high IF, this is especially useful as the
SFDR improvement is significant with marginal degradation in SNR.
The gain can be programmed using the serial interface (bits D3-D0 in register 0x68).
Table 10. Programmable Gain
REGISTER ADDRESS
A7
A6
A5
A4
A3
A2
REGISTER DATA
A1
A0
D7
D6
D5
D4
D3
DESCRIPTION
D2
D1
D0
<GAIN> Gain programming - Channel gain can be programmed from 0 to 6 dB for SFDR/SNR trade-off. For each gain setting, the
input full-scale range has to be proportionally scaled. For 6 dB gain, the full-scale range will be 1 VPP compared to 2 VPP at 0 dB
gain.
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0 dB Default after reset
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
0
1
0
2 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
0
1
1
3 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
0
4 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
1
5 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
0
6 dB
Power Down
ADS5546 has three power-down modes – global STANDBY, output buffer disabled, and input clock stopped.
Global STANDBY
This mode can be initiated by controlling SDATA (pin 28) or by setting the register bit <STBY> through the serial
interface. In this mode, the A/D converter, reference block and the output buffers are powered down and the
total power dissipation reduces to about 100 mW. The output buffers are in high impedance state. The wake-up
time from the global power down to data becoming valid normal mode is maximum 100 µs.
Output Buffer Disable
The output buffers can be disabled using OE pin 7 in both the LVDS and CMOS modes, reducing the total
power by about 100 mW. With the buffers disabled, the outputs are in high impedance state. The wake-up time
from this mode to data becoming valid in normal mode is maximum 1 µs in LVDS mode and 50 ns in CMOS
mode.
Input Clock Stop
The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is
about 100 mW and the wake-up time from this mode to data becoming valid in normal mode is maximum
100 µs.
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Power Scaling Modes
ADS5546 has a power scaling mode in which the device can be operated at reduced power levels at lower
sampling frequencies with no difference in performance. (See Figure 30) (1) There are four power scaling modes
for different sampling clock frequency ranges, using the serial interface register bits <POWER SCALING>. Only
the AVDD power is scaled, leaving the DRVDD power unchanged.
Table 11. Power Scaling vs Sampling Speed
Sampling Frequency
MSPS
(1)
Power Scaling Mode
Analog Power
(Typical)
Analog Power in Default Mode
> 150
Default
960 mW at 190 MSPS
960 mW at 190 MSPS
105 to 150
Power Mode 1
841 mW at 150 MSPS
917 mW at 150 MSPS
50 to 105
Power Mode 2
670 mW at 105 MSPS
830 mW at 105 MSPS
< 50
Power Mode 3
525 mW at 50 MSPS
760 mW at 50 MSPS
The performance in the power scaling modes is from characterization and not tested in production.
REGISTER ADDRESS
A7
A6
A5
A4
A3
A2
REGISTER DATA
A1
A0
D7
D6
D5
D4
D3
D2
D1
DESCRIPTION
D0
<POWER SCALING> Power scaling vs sampling frequency. The ADC can be operated at reduced power at lower sampling rates
with no loss in performance.
0
1
1
0
1
1
0
1
0
0
1
0
0
0
0
0
Default Fs > 150 MSPS Default after
reset
0
1
1
0
1
1
0
1
1
0
1
0
0
0
0
0
Power Mode1 105 < Fs ≤ 150
MSPS
0
1
1
0
1
1
0
1
0
1
1
0
0
0
0
0
Power Mode2 50 < Fs ≤ 105
MSPS
0
1
1
0
1
1
0
1
1
1
1
0
0
0
0
0
Power Mode3 Fs ≤ 50 MSPS
Power Supply Sequence
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated inside the device. Externally, they can be driven from separate supplies or from a single supply.
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Digital Output Information
ADS5546 provides 14-bit data, an output clock synchronized with the data and an out-of-range indicator that
goes high when the output reaches the full-scale limits. In addition, output enable control (OE pin 7) is provided
to power down the output buffers and put the outputs in high-impedance state.
Output Interface
Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be
selected using the DFS (see Table 6) or the serial interface register bit <ODI>.
DDR LVDS Outputs
In this mode, the 14 data bits and the output clock are available as LVDS (Low Voltage Differential Signal)
levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown in
Figure 51. So, there are 7 LVDS output pairs for the 14 data bits and 1 LVDS output pair for the output clock.
Pins
CLKOUTP
Output Clock
CLKOUTM
D0_D1_P
Data Bits D0. D1
D0_D1_M
D2_D3_P
Data Bits D2, D3
D2_D3_M
D4_D5_P
Data Bits D4, D5
D4_D5_M
D6_D7_P
Data Bits D6, D7
D6_D7_M
D8_D9_P
Data Bits D8, D9
D8_D9_M
D10_D11_P
Data Bits D10, D11
D10_D11_M
D12_D13_P
Data Bits D12, D13
D12_D13_M
OVR
Out-of-Range Indicator
ADS5546
S0169-01
Figure 51. DDR LVDS Outputs
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Even data bits D0, D2, D4, D6, D8, D10, and D12 are output at the falling edge of CLKOUTP and the odd data
bits D1, D3, D5, D7, D9, D11, and D13 are output at the rising edge of CLKOUTP. Both the rising and falling
edges of CLKOUTP have to be used to capture all the 14 data bits (see Figure 52).
CLKOUTP
CLKOUTM
D0_D1_P,
D0_D1_M
D0
D1
D0
D1
D2_D3_P,
D2_D3_M
D2
D3
D2
D3
D4_D5_P,
D4_D5_M
D4
D5
D4
D5
D6_D7_P,
D6_D7_M
D6
D7
D6
D7
D8_D9_P,
D8_D9_M
D8
D9
D8
D9
D10_D11_P,
D10_D11_M
D10
D11
D10
D11
D12_D13_P,
D12_D13_M
D12
D13
D12
D13
Sample N
Sample N+1
T0110-01
Figure 52. DDR LVDS Interface
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV
single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to
2.5 mA, 4.5 mA, and 1.75 mA using the serial interface. In addition, there exists a current double mode, where
this current is doubled for the data and output clock buffers.
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Table 12. LVDS Buffer Currents Programming
REGISTER ADDRESS
A7
A6
A5
A4
A3
A2
REGISTER DATA
A1
A0
D7
D6
D5
D4
D3
DESCRIPTION
D2
D1
D0
<LVDS CURRENT> – Output data and clock buffers current programmability
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
3.5 mA Default after reset
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
2.5 mA
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
4.5 mA
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1.75 mA
<CURRENT DOUBLE> – The output data and clock buffer currents are doubled from the value selected by the <LVDS CURRENT>
register.
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Value specified by <LVDS
CURRENT>Default after reset
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
2x data, 2x clock currents
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1x data, 2x clock currents
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2x data, 4x clock currents
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistances available are – 325, 200, and 170 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistances. This results in eight effective terminations from open (no
termination) to 75 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode (see Table 12).
Table 13. Programming Internal Termination for LVDS Data and Clock
REGISTER ADDRESS
A7
A6
A5
A4
A3
A2
REGISTER DATA
A1
A0
D7
D6
D5
D4
D3
DESCRIPTION
D2
D1
D0
<DATA TERM> Internal termination - Option to terminate the LVDS DATA buffers inside the ADC to improve signal integrity. By
default, internal termination is disabled.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
No termination Default after reset
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
325 Ω
0
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
200 Ω
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
125 Ω
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
170 Ω
0
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
120 Ω
0
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
100 Ω
0
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
75 Ω
<CLK TERM> Internal termination – Option to terminate the LVDS CLK buffers inside the ADC to improve signal integrity. By
default, internal termination is disabled.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
No termination Default after reset
0
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
325 Ω
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
200 Ω
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
125 Ω
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
170 Ω
0
1
1
1
1
1
1
0
0
0
0
1
0
1
0
0
120 Ω
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
100 Ω
0
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
75 Ω
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Parallel CMOS
In this mode, the 14 data outputs and the output clock are available as 3.3-V CMOS voltage levels. Each data
bit and the output clock is available on a separate pin in parallel. By default, the data outputs are valid during the
rising edge of the output clock. The output clock is CLKOUT (pin 5).
Output Clock Position Programmability
In both the LVDS and CMOS modes, the output clock can be moved around its default position. This can be
done using SEN pin 27 (as described in Table 5) or using the serial interface register bits <CLKOUT POSN>.
Using this allows to trade-off the setup and hold times leading to reliable data capture. There also exists an
option to align the output clock edge with the data transition.
Note that programming the output clock position also affects the clock propagation delay times.
Table 14. CLKOUT Position Programing
REGISTER ADDRESS
A7
A6
A5
A4
A3
A2
REGISTER DATA
A1
A0
D7
D6
D5
D4
D3
D2
DESCRIPTION
D1
D0
<CLKOUT POSN CMOS> – Output clock rising edge programmability in CMOS mode
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
Default position
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
1
Output clock rising edge later by (1/12)Ts
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
1
Output clock rising edge later by (3/12)Ts
0
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
Output clock rising edge later by (2/12)Ts
<CLKOUT POSN CMOS> – Output clock falling edge programmability in CMOS mode
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
Default position
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
1
Output clock falling edge later by (1/12)Ts
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
1
Output clock falling edge later by (3/12)Ts
0
1
1
0
0
0
1
0
0
0
0
1
1
0
0
1
Output clock falling edge later by (2/12)Ts
<CLKOUT POSN LVDS> – Output clock rising edge programmability in LVDS mode
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
Default position
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
1
Output clock rising edge earlier by (1/12)Ts
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
1
Output clock rising edge aligned with data
transition
0
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
Output clock rising edge aligned with data
transition
<CLKOUT POSN LVDS> – Output clock falling edge programmability in LVDS mode
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
Default position
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
1
Output clock falling edge earlier by (1/12)Ts
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
1
Output clock falling edge aligned with data
transition
0
1
1
0
0
0
1
0
0
0
0
1
1
0
0
1
Output clock falling edge aligned with data
transition
Output Data Format
Two output data formats are supported – 2's complement and offset binary. They can be selected using the DFS
(pin 6) or the serial interface register bit <DFS> . In the event of an input voltage overdrive, the digital outputs go
to the appropriate full scale level. For a positive overdrive, the output code is 0x3FFF in offset binary output
format, and 0x1FFF in 2's complement output format. For a negative input overdrive, the output code is 0x0000
in offset binary output format and 0x2000 in 2's complement output format.
42
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SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006
Output Timing
For the best performance at high sampling frequencies, ADS5546 uses a clock generator circuit to derive
internal timing for ADC. This results in optimal setup and hold times of the output data and 50% output clock
duty cycle for sampling frequencies from 80 MSPS to 190 MSPS. See Table 15 for timing information above 80
MSPS.
Table 15. Timing Characteristics (80 MSPS to 190 MSPS)
Fs, MSPS
tsu DATA SETUP TIME, ns
th DATA HOLD TIME, ns
MIN
TYP
MAX
MIN
190
1.3
1.8
0.5
150
1.6
2.1
0.6
130
2.0
2.5
0.8
80
3.6
4.1
190
2.5
150
2.8
130
80
TYP
(1)
tPDI CLOCK PROPAGATION DELAY, ns
MAX
MIN
TYP
MAX
1
3.9
4.6
5.3
1.1
4.3
5
5.7
1.3
4.5
5.2
5.9
1.6
2.1
4.7
5.7
6.7
3.3
0.8
1.2
1.9
2.7
3.5
3.6
1.2
1.6
1.7
2.5
3.3
3.3
4.1
1.7
2.1
1.1
1.9
2.7
6
7
3.7
4.1
10.8
12
13.2
DDR LVDS
PARALLEL CMOS
(1)
Timing parameters are specified by design and characterization and not tested in production.
Below 80 MSPS, the setup and hold times do not scale with the sampling frequency. The output clock duty cycle
also progressively moves away from 50% as the sampling frequency is reduced from 80 MSPS.
See Table 16 for detailed timings at sampling frequencies below 80 MSPS. Figure 53 shows the clock duty cycle
across sampling frequencies in the DDR LVDS and CMOS modes.
Table 16. Timing Characteristics (1 MSPS to 80 MSPS)
Fs, MSPS
tsu DATA SETUP TIME, ns
MIN
TYP
th DATA HOLD TIME, ns
MAX
MIN
TYP
(1)
tPDI CLOCK PROPAGATION DELAY, ns
MAX
MIN
TYP
MAX
DDR LVDS
1 to 80
3.6
1.6
5.7
6
3.7
12
PARALLEL CMOS
1 to 80
Timing parameters are specified by design and characterization and not tested in production.
Output Clock Duty Cycle − %
(1)
100
90
80
70
60
DDR LVDS
50
40
CMOS
30
20
10
0
0
20
40
60
80
100 120
140 160
180
Sampling Frequency − MHz
Figure 53. Output Clock Duty Cycle (typical) vs Sampling Frequency
The latency of ADS5546 is 14 clock cycles from the sampling instant (input clock rising edge). In the LVDS
mode, the latency remains constant across sampling frequencies. In the CMOS mode, the latency is 14 clock
cycles above 80 MSPS and 13 clock cycles below 80 MSPS.
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ADS5546
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SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low
frequency value.
Aperture Delay
The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling
occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width)
to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential
sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified operation is given. All parametric testing is performed at this
sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the
deviation of any single step from this ideal value, measured in units of LSBs
Integral Nonlinearity (INL)
The INL is the deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit
of that transfer function, measured in units of LSBs.
Gain Error
The gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Offset Error
The offset error is the difference, given in number of LSBs, between the ADC’s actual average idle channel
output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift
The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree
Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter
across the TMIN to TMAX range by the difference TMAX–TMIN.
44
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DEFINITION OF SPECIFICATIONS (continued)
Signal-to-Noise Ratio
SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc
and the first nine harmonics.
P
SNR + 10Log 10 s
PN
(3)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding dc.
Ps
SINAD + 10Log 10
PN ) PD
(4)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Effective Number of Bits (ENOB)
The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization
noise.
ENOB + SINAD * 1.76
6.02
(5)
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD).
P
THD + 10Log 10 s
PN
(6)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic).
SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral
component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the
fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR)
The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is
typically given in units of mV/V.
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ADS5546
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SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006
DEFINITION OF SPECIFICATIONS (continued)
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If ∆VSUP is the change in
the supply voltage and ∆VOUT is the resultant change in the ADC output code (referred to the input), then
DVOUT
PSRR = 20Log 10
(Expressed in dBc)
DVSUP
(7)
Common Mode Rejection Ratio (CMRR)
CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If ∆Vcm is the
change in the input common-mode voltage and ∆VOUT is the resultant change in the ADC output code (referred
to the input), then
DVOUT
CMRR = 20Log10
(Expressed in dBc)
DVCM
(8)
Voltage Overload Recovery
The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A
6-dBFS sine wave at Nyquist frequency is used as the test stimulus.
46
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ADS5546 Revision history
Revision
Date
Description
A
11/05
Added new graphs to the Typical Characteristics.
B
6/06
New Timing Characteristics table.
New text for the Device Mode Configuration
Parallel Pin Control section changed to Parallel Configuration Only section.
Added Serial Interface Configuration Only section.
Added Configuration Using Both the Serial Interface and Parallel Controls
New text for the Serial Interface section
Added Register Reset section
Additions to Table 8, <RST> and <GAIN>
Revised Typical Characteristics graphs.
Added Programmable gain section in the Application Information
C
10/06
Added DEFAULT and LOW SPEED modes to the Clock Input of the Recommended Operating
Conditions
Changed the max Standby power specifications.
Changed the max Clock stop power specifications.
Changed Analog Input information and Figures.
Changed Drive Circuit and Example Drive Circuit information and Figures.
Added Using RF Transformer-Based Drive Circuits information.
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47
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS5546IRGZR
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5546IRGZRG4
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5546IRGZT
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5546IRGZTG4
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
PADS5546IRGZT
PREVIEW
QFN
RGZ
48
TBD
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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