TI ADS62P15IRGCTG4

ADS62P15
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SLAS572 – OCTOBER 2007
Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
Maximum Sample Rate: 125 MSPS
11-Bit Resolution With No Missing Codes
84 dBc SFDR at Fin = 50 MHz
67.1 dBFS SNR at Fin = 50 MHz
92 dB Crosstalk
Parallel CMOS and DDR LVDS Output Options
3.5 dB Coarse Gain and Programmable Fine
Gain up to 6 dB for SNR/SFDR Trade-Off
Digital Processing Block With:
– Offset Correction
– Fine Gain Correction, in Steps of 0.05 dB
– Decimation by 2/4/8
– Built-in and Custom Programmable 24-Tap
Low/High /Band Pass Filters
Supports Sine, LVPECL, LVDS & LVCMOS
Clocks & Amplitude Down to 400 mVPP
Clock Duty Cycle Stabilizer
Internal Reference; Supports External
•
•
Reference also
64-QFN Package (9mm × 9mm)
Pin Compatible 14-bit and 12-bit Family
(ADS62P4X/ADS62P2X)
APPLICATIONS
•
•
•
•
•
•
•
Wireless Communications Infrastructure
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Medical Imaging
Radar Systems
Test and Measurement Instrumentation
Table 1. ADS62PXX Dual Channel Family
125 MSPS
105 MSPS
80 MSPS
65 MSPS
ADS62P4X
(14 bit)
ADS62P45
ADS62P44
ADS62P43
ADS62P42
ADS62P2X
(12 bit)
ADS62P25
ADS62P24
ADS62P23
ADS62P22
(11 bit)
ADS62P15
-
-
-
DESCRIPTION
ADS62P15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high
performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and
low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and
fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.
ADS62P15 includes a digital processing block that consists of several useful and commonly used digital
functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and
in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions
are disabled.
Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P15 includes
internal references while traditional reference pins and associated decoupling capacitors have been eliminated.
Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial
temperature range (–40°C to 85°C).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
ADS62P15
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SLAS572 – OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DRGND
DRVDD
AGND
AVDD
FUNCTIONAL BLOCK DIAGRAM
Digital Processing
Block
Channel A
INA_P
SHA
11-Bit ADC
INA_M
Output
Buffers
Digital
Encoder
11 Bit
CLKP
CLKM
11 Bit
Output
Clock
Buffer
CLOCKGEN
11 Bit
INB_P
SHA
11-Bit ADC
INB_M
Channel A
11 Bit
Digital
Encoder
Output
Buffers
Channel B
Digital Processing
Block
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
CLKOUT
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
Channel B
2
CMOS INTERFACE
CTRL1
CTRL2
CTRL3
Reference
RESET
SCLK
SEN
SDATA
VCM
Control
Interface
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CLIPPER
From ADC
11bits
output
11bits
11bits
11bits
11 bits
To LVDS or CMOS
output buffers
0
OFFSET
ESTIMATION
BLOCK
24TAP FILTER
- LOW PASS
- HIGH PASS
- BAND PASS
GAIN
CORRECTION
(0.05dB steps)
FINE GAIN
(0 to 6 dB, 0.5 dB
steps)
DISABLE
OFFSET
CORRECTION
DECIMATION
BY2/4/8
FILTER
SELECTION
11bits
BYPASS
FILTER
BYPASS
DECIMATION
FREEZE
OFFSET
CORRECTION
DIGITAL
PROCESSING BLOCK
Figure 1. Digital Processing Block Diagram
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
LEAD/BALL
FINISH
PACKAGE
MARKING
ADS62P15
QFN-64
RGC
–40°C to 85°C
Cu NiPdAu
AZ62P15
(1)
(2)
ORDERING (2)
NUMBER
TRANSPORT
MEDIA,
QUANTITY
ADS62P15RGCT
250 Tape/Reel
ADS62P15RGCR
2000 Tape/Reel
For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM airflow), θJC
= 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in. x 3 in. PCB.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
–0.3 V to 3.9
V
–0.3 V to 3.9
V
Voltage between AGND and DRGND
–0.3 to 0.3
V
Voltage between AVDD to DRVDD
–0.3 to 3.3
V
-0.3 to 2
V
–0.3V to minimum
( 3.6, AVDD + 0.3 V )
V
Supply voltage range, AVDD, DRVDD
VSS
Voltage applied to external pin, CM (in external reference mode)
Voltage applied to analog input pins, INA_P, INA_M, INB_P, INB_M
Voltage applied to clock input pins, CLKP, CLKM
TA
Operating free-air temperature range
TJ
Operating junction temperature range
Tstg
Storage temperature range
(1)
–0.3 V to AVDD + 0.3 V
V
–40 to 85
°C
125
°C
–65 to 150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
3
3.3
3.6
CMOS interface
1.65
1.8 to 3.3
3.6
LVDS interface
3.0
3.3
3.6
UNIT
SUPPLIES
Analog supply voltage, AVDD
VSS
Digital supply voltage, DRVDD
V
V
ANALOG INPUTS
Differential input voltage range
2
VPP
Input common-mode voltage
1.5 ± 0.1
V
Voltage applied on CM in external reference mode
1.5 ±0.05
V
CLOCK INPUT
Fs
Input clock sample rate
1
Sine wave, ac-coupled
Input clock amplitude differential
(VCLKP–VCLKM)
0.4
125
LVPECL, ac-coupled
1.6
LVDS, ac-coupled
0.7
LVCMOS, single-ended, ac-coupled
Input clock duty cycle
VPP
3.3
35%
MSPS
3
50%
V
65%
DIGITAL OUTPUTS
Output buffer drive strength (1)
CLOAD
Maximum external load
capacitance from each output pin
to DRGND
For CLOAD ≤ 5 pF and DRVDD ≥ 2.2 V
Default
strength
For CLOAD ≥ 5 pF and DRVDD ≥ 2.2 V
Maximum
strength
For DRVDD < 2.2 V
Maximum
strength
CMOS interface
Differential load resistance between the LVDS output pairs (LVDS mode)
TA
Operating free-air temperature
4
5
LVDS interface, with 100 Ω internal termination
RLOAD
(1)
5
LVDS interface, without internal termination
pF
10
Ω
100
–40
85
°C
See the Output buffer strength programmability in application section
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ELECTRICAL CHARACTERISTICS
Typical values at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
3.3V, DRVDD = 1.8V to 3.3V, sampling frequency = 125 MSPS, 50% clock duty cycle, –1dBFS differential analog input,
internal reference mode, applies to CMOS and LVDS interfaces (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
MAX
11
UNIT
bits
ANALOG INPUTS
Differential input voltage range
2
VPP
MΩ
Differential input resistance (at dc)
See Figure 31
>1
Differential input capacitance
See Figure 32
7
pF
Analog input bandwidth
450
MHz
Analog input common mode current (per input pin)
125
µA
VCM common mode voltage output
1.5
VCM output current capability
V
4
mA
POWER SUPPLY
Analog supply current (AVDD)
ISS
216
Output buffer supply current (DRVDD)
CMOS interface
DRVDD=1.8V, 2.5 MHz input signal
no load capacitance (1)
mA
17
Total power – CMOS interface
0.74
Total power – CMOS interface
DRVDD=3.3V, 50MHz input signal
10pF load capacitance
Total power – LVDS interface
DRVDD = 3.3V
W
1.225
W
0.94
Global power down
30
W
60
mW
DC ACCURACY
No missing codes
Specifie
d
DNL
Differential Non-Linearity
-0.8
±0.4
0.8
LSB
INL
Integral Non-Linearity
-3.5
±1
3.5
LSB
EO
Offset Error
-10
±3
10
mV
Offset error temperature coefficient
0.05
mV/°C
There are two sources of gain error – internal reference inaccuracy and channel gain error
EGREF
Gain error due to internal reference inaccuracy
alone
-1
EGCHAN
Gain error of channel alone (2)
-1
Channel gain error temperature coefficient
(1)
(2)
±0.25
1
±0.3
1
0.005
%FS
%FS
Δ%/°C
In CMOS mode, the DRVDD current scales with the sampling frequency and the load capacitance on output pins (see Figure 28).
This is specified by design and characterization; it is not tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
3.3V, DRVDD = 1.8V to 3.3V, sampling frequency = 125 MSPS, 50% clock duty cycle, –1dBFS differential analog input,
internal reference mode, applies to CMOS and LVDS interfaces (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
Fin= 10 MHz
65.5
Fin = 70 MHz
Signal to noise ratio
Fin= 170 MHz
Fin = 230 MHz
66.8
3.5 dB gain
66.4
0 dB gain
66.6
3.5 dB gain
66.2
Fin = 230 MHz
ENOB
Effective number of bits
66.9
66.5
3.5 dB gain
66.2
0 dB gain
66.3
3.5 dB gain
Fin = 50 MHz
Fin = 230 MHz
75
85
82
3.5 dB gain
84
0 dB gain
78
3.5 dB gain
80
72
Fin = 70 MHz
Fin= 170 MHz
Fin = 230 MHz
83
79
3.5 dB gain
81
0 dB gain
75
3.5 dB gain
77
75
Fin = 70 MHz
Fin= 170 MHz
Fin = 230 MHz
93
85
3.5 dB gain
87
0 dB gain
82
3.5 dB gain
84
75
Fin = 70 MHz
Fin= 170 MHz
Fin = 230 MHz
6
dBc
89
Fin = 50 MHz
Third harmonic distortion
93
0 dB gain
Fin= 10 MHz
HD3
dBc
95
Fin = 50 MHz
Second harmonic distortion
77
0 dB gain
Fin= 10 MHz
HD2
dBc
87
Fin = 50 MHz
Total harmonic distortion
LSB
79
0 dB gain
Fin= 10 MHz
THD
10.8
89
Fin = 70 MHz
Fin= 170 MHz
dBFS
65.9
10.5
Fin = 50 MHz
Spurious free dynamic range
66.9
0 dB gain
Fin= 10 MHz
SFDR
dBFS
67.1
65
Fin = 70 MHz
Fin= 170 MHz
67.1
0 dB gain
Fin = 50 MHz
Signal to noise and distortion ratio
UNIT
67.1
Fin= 10 MHz
SINAD
MAX
67.2
Fin = 50 MHz
SNR
TYP
79
85
0 dB gain
82
3.5 dB gain
84
0 dB gain
78
3.5 dB gain
80
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dBc
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
3.3V, DRVDD = 1.8V to 3.3V, sampling frequency = 125 MSPS, 50% clock duty cycle, –1dBFS differential analog input,
internal reference mode, applies to CMOS and LVDS interfaces (unless otherwise noted).
PARAMETER
Worst
Spur
IMD
PSRR
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Fin= 10 MHz
94
Fin = 50 MHz
92
Fin = 70 MHz
94
Fin= 170 MHz
90
Fin = 230 MHz
88
2-Tone intermodulation distortion
F1 = 185 MHz, F2 = 190 MHz
each tone at –7 dBFS
88
dBFS
Recovery to within 1% (of final
value) for 6-dB overload with sine
wave input
1
Input overload recovery
clock
cycles
Cross-talk
Cross-talk signal frequency upto
100 MHz
95
dB
AC Power supply rejection ratio
For 100 mV pp signal on AVDD
supply, frequency upto 10 MHz
45
dBc
Other than second, third harmonics
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DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD=3.3V, DRVDD=1.8V to 3.3V, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
33
µA
Low-level input current
–33
µA
4
Pf
High-level output voltage
DRVDD
V
Low-level output voltage
0
V
2
pF
High-level output voltage
1375
mV
Low-level output voltage
1025
mV
Input capacitance
DIGITAL OUTPUTS – CMOS MODE, DRVDD = 1.8 to 3.3V
Output capacitance (internal to device)
DIGITAL OUTPUTS – LVDS MODE (1)
(2)
, DRVDD = 3.3V
|VOD|
Output differential voltage
VOS
Output offset voltage
Common-mode voltage of OUTP and OUTM
Output Capacitance
Output capacitance inside the device, from
either output to ground
(1)
(2)
8
250
350
500
mV
1200
mV
2
pF
LVDS buffer current setting, IO = 3.5 mA.
External differential load resistance between the LVDS output pairs, RLOAD = 100 Ω.
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TIMING REQUIREMENTS – LVDS AND CMOS MODES (1)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD
= 3.3V, DRVDD = 1.8V to 3.3V, sampling frequency = 125MSPS, sine wave input clock, 3VPP clock amplitude, CLOAD = 5pF
(2)
, Io = 3.5mA, RLOAD = 100Ω (3), no internal termination, unless otherwise noted.
PARAMETER
TEST CONDITIONS
ta
Aperture delay
tj
Aperture jitter
MIN
TYP MAX
0.8
1.8
2.8
130
from global power down
Wake-up time
to valid output data
Latency
from channel standby
from output buffer disable
UNIT
ns
fs rms
15
50
µs
100
200
ns
CMOS
100
200
ns
LVDS
200
500
ns
default, after reset
14
clock
cycles
in low latency mode
10
clock
cycles
with decimation filter enabled
15
clock
cycles
0.6
1.5
ns
ns
DDR LVDS MODE (4) DRVDD = 3.3V
Data setup time (5)
tsu
(5)
Data valid
(6)
to zero-crossing of CLKOUTP
(6)
th
Data hold time
Zero-crossing of CLKOUTP to data becoming invalid
1.0
2.3
tPDI
Clock propagation
delay
Input clock rising edge cross-over to output clock rising edge cross-over
20 MSPS ≤ Sampling frequency ≤ 125 MSPS
3.5
5.5
7.5
LVDS bit clock duty
cycle
Duty cycle of differential clock, (CLKOUTP-CLKOUTM)
10 MSPS ≤ Sampling frequency ≤ 125 MSPS
46%
49%
52%
tRISE
Data rise time
Rise time measured from –100 mV to +100 mV
1 MSPS ≤ Sampling frequency ≤ 125 MSPS
70
110
170
ps
tFALL
Data fall time
Fall time measured from +100mV to –100 mV
1 MSPS ≤ Sampling frequency ≤ 125 MSPS
70
110
170
ps
tCLKRISE Output clock rise time
Rise time measured from –100mV to +100mV
1 MSPS ≤ Sampling frequency ≤ 125 MSPS
70
110
170
ps
tCLKFALL Output clock fall time
Fall time measured from +100mV to –100mV
1 MSPS ≤ Sampling frequency ≤ 125 MSPS
70
110
170
ps
Data valid (7) to 50% of CLKOUT rising edge
2.0
3.5
ns
50% of CLKOUT rising edge to data becoming invalid (7)
2.0
3.5
ns
5.8
7.3
8.8
45%
53%
60%
ns
PARALLEL CMOS MODE DRVDD = 2.5V to 3.3V
Data setup time (5)
tsu
(5)
th
Data hold time
tPDI
Clock propagation
delay
50% of input clock rising edge to 50% of CLKOUT rising edge
20 MSPS ≤ Sampling frequency ≤ 125 MSPS
Output clock duty cycle
Duty cycle of output clock, CLKOUT
10 MSPS ≤ Sampling frequency ≤ 125 MSPS
tRISE
Data rise time
Rise time measured from 20% to 80% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 125 MSPS
0.7
1.5
2.5
ns
tFALL
Data fall time
Fall time measured from 80% to 20% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 125 MSPS
0.7
1.5
2.5
ns
tCLKRISE Output clock rise time
Rise time measured from 20% to 80% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 125 MSPS
0.7
1.5
2.5
ns
tCLKFALL Output clock fall time
Fall time measured from 80% to 20% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 125 MSPS
0.7
1.5
2.5
ns
(1)
(2)
(3)
(4)
(5)
(6)
(7)
ns
Timing parameters are ensured by design and characterization and not tested in production.
CLOAD is the effective external single-ended load capacitance between each output pin and ground
IO refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
Data valid refers to LOGIC HIGH of +100.0 mV and LOGIC LOW of –100.0mV.
Data valid refers to LOGIC HIGH of 2V (1.7V) and LOGIC LOW of 0.8V (0.7V) for DRVDD = 3.3V (2.5V)
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Table 2. Timing Characteristics at Lower Sampling Frequencies
tsu DATA SETUP TIME, ns
Sampling Frequency, MSPS
MIN
TYP
th DATA HOLD TIME, ns
MAX
MIN
TYP
MAX
CMOS INTERFACE, DRVDD = 2.5 TO 3.3V
105
2.8
4.3
2.7
4.2
80
4.3
5.8
4.2
5.7
65
5.7
7.2
5.6
7.1
40
10.5
12
10.3
11.8
20
23
24.5
23
24.5
105
1
2.3
80
2.4
3.8
65
3.8
5.2
1.0
2.3
40
8.5
10
20
21
22.5
DDR LVDS INTERFACE, DRVDD = 3.3V
N+4
N+3
N+2
N+1
Sample
N
N+16
N+15
N+14
Input
Signal
ta
CLKP
Input
Clock
CLKM
CLKOUTM
CLKOUTP
tsu
14 Clock Cycles
DDR
LVDS
Output Data
DXP, DXM
E
E – Even Bits D0,D2,D4,D6,D8,D10
O – Odd Bits D1,D3,D5,D7,D9
O
E
N–14
O
E
N–13
E
O
N–12
O
(1)
E
N–11
tPDI
th
O
E
N–10
E
O
E
O
N
N–1
E
O
N+1
E
O
O
N+2
tPDI
CLKOUT
tsu
Parallel
CMOS
14 Clock Cycles
Output Data
D0–D10
N–14
N–13
N–12
(1)
N–11
th
N–10
N–1
N
N+1
N+2
T0105-05
(1)
Latency is 10 clock cycles in low-latency mode
Figure 2. Latency Diagram
10
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CLKM
Input
Clock
clock
CLKP
t PDI
CLKOUTM
Output
Clock
clock
CLKOUTP
t su
su
Output
Output
Data
data Pair
pair
Dn_Dn+1_P,
Dn_Dn+1_M
t hh
t su
su
Dn *
t hh
Dn +1*
*Dn - Bits D0, D2, D4, D6, D8, D10
*Dn+1 - Bits D1, D3, D5, D7, D9
Figure 3. LVDS Mode Timing
CLKM
Input
Clock
clock
CLKP
t PDI
PDI
Output
Clock
clock
CLKOUT
t su
su
Output
Data
data
Dn
t hh
Dn *
*Dn - Bits D0 to D10
Figure 4. CMOS Mode Timing
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DEVICE CONFIGURATION
ADS62P15 can be configured independently using either parallel interface control or serial interface
programming.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using the parallel interface, keep RESET tied to high (AVDD). Pins SEN, SCLK, CTRL1,
CTRL2 and CTRL3 can be used to directly control certain modes of the ADC. After power-up, the device will
automatically get configured as per the parallel pin voltage settings (Table 4 to Table 6).
In this mode, SEN and SCLK function as parallel analog control pins, which can be configured using a simple
resistor divider (Figure 5). Table 3 has a brief description of the modes controlled by the parallel pins.
Table 3. Parallel Pin Definition
PIN
SCLK
SEN
CTRL1
CTRL2
CTRL3
TYPE OF PIN
CONTROLS MODES
Analog control pins
(controlled by analog
voltage levels, see )
Coarse Gain and Internal/External reference
Digital control pins
(controlled by digital
logic levels)
LVDS/CMOS interface and Output Data Format
Together control various power down modes and MUX mode.
USING SERIAL INTERFACE PROGRAMMING ONLY
To program the device using the serial interface, keep RESET low. Pins SEN, SDATA, and SCLK function as
serial interface digital pins and are used to access the internal registers of ADC. The registers must first be reset
to their default values either by applying a pulse on RESET pin or by setting bit <RST> = 1. After reset, the
RESET pin must be kept low.
The serial interface section describes the register programming and register reset in more detail. Since the
parallel pins (CTRL1, CTRL2, CTRL3) are not used in this mode, they must be tied to ground.
USING BOTH SERIAL INTERFACE and PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To allow this, keep RESET low.
The parallel interface control pins CTRL1 to CTRL3 are available. After power-up, the device will automatically
get configured as per the voltage settings on these pins (Table 6).
SEN, SDATA, and SCLK function as serial interface digital pins and are used to access the internal registers of
ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by
setting bit <RST> = 1. After reset, the RESET pin must be kept low. The serial interface section describes the
register programming and register reset in more detail.
Since the power down modes can be controlled using both the parallel pins and serial registers, the priority
between the two is determined by <OVRD> bit. When <OVRD> bit = 0, pins CTRL1 to CTRL3 control the power
down modes. With <OVRD> = 1, register bits <POWER DOWN> control these modes, over-riding the pin
settings.
12
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DETAILS OF PARALLEL CONFIGURATION ONLY
The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is
shown in Figure 5.
Table 4. SCLK (Analog Control Pin)
SCLK
DESCRIPTION
0
0dB gain and Internal reference
(3/8)AVDD
0dB gain and External reference
(5/8)2AVDD
3.5dB Coarse gain and External reference
AVDD
3.5dB Coarse gain and Internal reference
Table 5. SEN (Analog Control Pin)
SEN
DESCRIPTION
0
2s complement format and DDR LVDS output
(3/8)AVDD
Straight binary and DDR LVDS output
(5/8)AVDD
Straight binary and parallel CMOS output
AVDD
2s complement format and parallel CMOS output
Table 6. CTRL1, CTRL2 and CTRL3 (Digital Control Pins)
CTRL1
CTRL2
CTRL3
LOW
LOW
LOW
Normal operation
DESCRIPTION
LOW
LOW
HIGH
Channel A output buffer disabled
LOW
HIGH
LOW
Channel B output buffer disabled
LOW
HIGH
HIGH
Channel A and B output buffer disabled
HIGH
LOW
LOW
Channel A and B powered down
HIGH
LOW
HIGH
Channel A standby
HIGH
HIGH
LOW
Channel B standby
HIGH
HIGH
HIGH
MUX mode of operation (only with CMOS interface Channel A and B data is multiplexed and
output on DB10 to DB0 pins. See Multiplexed output mode for detailed description.
AVDD
(5 /8 )AVDD
3R
( 5 /8 ) AVDD
AVDD
GND
2R
( 3 /8 )AVDD
( 3 /8 )AVDD
3R
To parallel pin
GND
Figure 5. Simple Scheme to Configure Parallel Pins
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SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be
loaded in multiple of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits the register data. The interface can work with
SCLK frequency from 20 MHz down to low speeds (few Hertz), and also with a non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to their default values. This can be done in one of two
ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as
shown in Figure 6.
OR
2. By applying software reset. Using the serial interface, set the <RST> bit to high. This initializes internal
registers to their default values and then self-resets the <RST> bit to low. In this case the RESET pin is kept
low.
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V,
DRVDD = 1.8V to 3.3V, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNIT
20
MHz
fSCLK
SCLK frequency
tSLOADS
SEN to SCLK setup time
> DC
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDS
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
REGISTER DATA
REGISTER ADDRESS
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
tSCLK
D5
D4
tDSU
D3
D2
D1
D0
tDH
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 6. Serial Interface Timing
14
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RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, unless otherwise
noted.
PARAMETER
CONDITIONS
t1
Power-on delay
Delay from power-up of AVDD and DRVDD to RESET pulse
active
t2
Reset pulse width
t3
tPO
MIN
TYP
MAX
UNIT
5
ms
Pulse width of active RESET signal
10
ns
Register write delay
Delay from RESET disable to SEN active
25
Power-up time
Delay from power-up of AVDD and DRVDD to output stable
ns
7
ms
NOTE: : A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 7. Reset Timing Diagram
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SERIAL REGISTER MAP
Table 7. Summary of Functions Supported by Serial Interface
REGISTER
ADDRESS
REGISTER FUNCTIONS
A7–A0 IN
HEX
D7
D6
D5
D4
D3
D2
D1
D0
00
0
0
0
0
0
0
<RST>
Software Reset
0
0
0
0
0
0
0
<CLKOUT
STRENGTH>
10
<DATAOUT
STRENGTH>
0
0
12
0
0
13
0
0
0
<OFFSET FREEZE>
0
14
<OVRD>
Over-ride
bit
0
<OUTPUT
INTERFACE>
LVDS or CMOS
interface
<COARSE GAIN>
3.5 dB gain
<REF>
Internal/External
reference
<POWER DOWN MODES>
and
MUX mode
16
0
0
0
<DATA FORMAT>
2s complement or straight
binary
Bit/Byte wise
(LVDS only)
<TEST PATTERNS>
17
0
0
0
0
19
0
0
1A
<LOW
LATENCY>
1B
<OFFSET
EN>
Other
correction
enable
0
<FILTER COEFF
SELECT>
In-built or custom
coefficients
<DECIMATION Enable>
Enable decimation
<ODD TAP
Enable>
1D
0
0
0
0
0
<LVDS TERMINATION>
Internal termination programmability
0
0
0
<FINE GAIN>
0 to 6 dB gain in 0.5 dB steps
<CUSTOM LOW> Lower 5bits
0
0
0
<CUSTOM HIGH> Upper 6 bits
<OFFSET TC>
Offset correction time constant
1E to 2F
(1)
<LVDS CURRENT>
LVDS buffer current
programmability
<CURRENT DOUBLE>
LVDS buffer current double
11
18
16
(1)
<GAIN CORRECTION>
0 to 0.5 dB, steps of 0.05 dB
<DECIMATION RATE>
Decimate by 2, 4, 8
0
<DECIMATION FILTER
FREQ BANDS>
<FILTER COEFFICIENTS> 12 coefficients, each 12 bit signed
Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
Table 1.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
00
0
0
0
0
0
0
<RST>
Software Reset
0
D1
1
<RST>
Software reset applied – resets all internal registers and self-clears to 0.
Table 2.
A7–A0
(hex)
10
D7–D6
01
00
11
10
D7
D6
<CLKOUT STRENGTH>
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
D2
D1
D0
<CLKOUT STRENGTH> Output clock buffer drive strength control
WEAKER than default drive
DEFAULT drive strength
STRONGER than default drive strength (recommended for load capacitances > 5 pF)
MAXIMUM drive strength (recommended for load capacitances > 5 pF)
Table 3.
A7–A0
(hex)
D7
D6
11
0
0
D5
D4
<CURRENT DOUBLE>
LVDS buffer current double
D3
LVDS CURRENT> LVDS
buffer current
programmability
D1–D0
01
00
11
10
<DATAOUT STRENGTH> Output data buffer drive strength control
WEAKER than default drive
DEFAULT drive strength
STRONGER than default drive strength (recommended for load capacitances > 5 pF)
MAXIMUM drive strength (recommended for load capacitances > 5 pF)
D3–D2
00
01
10
11
<LVDS CURRENT> LVDS Current programmability
3.5 mA
2.5 mA
4.5 mA
1.75 mA
D5–D4
00
01
10
11
CURRENT DOUBLE> LVDS Current double control
default current, set by <LVDS CURR>
LVDS clock buffer current is doubled, 2x <LVDS CURR>
LVDS data and clock buffers current are doubled, 2x <LVDS CURR>
unused
DATAOUT STRENGTH>
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Table 4.
A7–A0
(hex)
D7
D6
12
0
0
D5
D4
D3
D2
D1
D0
<LVDS TERMINATION> Internal termination programmability
D5–D3
000
001
010
011
100
101
110
111
<LVDS DATA TERM> Internal termination control for data outputs
No internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
D2–D0
000
001
010
011
100
101
110
111
<LVDS CLK TERM> Internal termination control for clock output
No internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
Table 5.
D4
0
1
18
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
13
0
0
0
<OFFSET FREEZE>
0
0
0
0
<OFFSET FREEZE> Offset correction becomes inactive and the last estimated offset value is used to cancel the offset
Offset correction active
Offset correction inactive
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Table 6.
A7–A0
(hex)
D7
14
<OVRD>
Over-ride bit
D6
D5
D4
D3
0
<OUTPUT
INTERFACE>
LVDS or CMOS
interface
<COARSE GAIN>
3.5 dB gain
<REF>
Internal / External
reference
D2
D1
D0
<POWER DOWN
MODES>
D2-D0
000
001
010
011
100
101
110
111
<POWER DOWN MODES>
Normal operation
Channel A output buffer disabled
Channel B output buffer disabled
Channel A and B output buffers disabled
Global power down
Channel A standby
Channel B standby
Multiplexed mode, MUX– (only with CMOS interface)
Channel A and B data is multiplexed and output on DA10 to DA0 pins.
D3
0
1
<REF> Reference mode
Internal reference enabled
External reference enabled
D4
0
1
<COARSE GAIN> Coarse gain control
0 dB coarse gain
3.5 dB coarse gain
D5
0
1
<OUTPUT INTERFACE> Output interface selection
Parallel CMOS data outputs
DDR LVDS data outputs
D7
<OVRD> Over-ride bit – the LVDS/CMOS selection, power down and MUX modes can also be controlled using parallel pins.
By setting <OVRD> = 1, register bits LVDS <CMOS> and <POWER DOWN MODES> will over-ride the settings of the parallel
pins.
Disable over-ride
Enable over-ride
0
1
Table 7.
A7–A0
(hex)
D7
D6
D5
D4
D3
16
0
0
0
DATA FORMAT>
2s complement or straight binary
Bit / Byte wise (LVDS only)
D2
D1
D0
<TEST PATTERNS>
D2–D0
000
001
010
011
100
101
110
111
<TEST PATTERNS> Test Patterns to verify capture
Normal ADC operation
Outputs all zeros
Outputs all ones
Outputs toggle pattern
Outputs digital ramp
Outputs custom pattern
Unused
Unused
D3
0
1
Bit-wise/Byte-wise selection (DDR LVDS mode ONLY)
Bit wise – Odd bits (D1, D3, D5, D7, D9) on CLKOUT rising edge and Even bits (D0, D2, D4, D6, D8, D10) on CLKOUT
falling edge
Byte wise – Lower 7 bits (D0-D6) at CLKOUT rising edge and Upper 4 bits (D7-D10) at CLKOUT falling edge
D4
0
1
<DATA FORMAT> Data format selection
2s complement
Straight binary
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Table 8.
A7–A0
(hex)
D7
D6
D5
D4
17
0
0
0
0
D2–D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Others
D3
D2
D1
D0
<FINE GAIN> 0 to 6 dB gain in 0.5 dB steps
<FINE GAIN> Gain programmability in 0.5 dB steps
0 dB gain, default after reset
0.5 dB gain
1.0 dB gain
1.5 dB gain
2.0 dB gain
2.5 dB gain
3.0 dB gain
3.5 dB gain
4.0 dB gain
4.5 dB gain
5.0 dB gain
5.5 dB gain
6.0 dB gain
Unused
Table 9.
A7–A0
(hex)
D7
D6
0
0
18
19
D5
D4
D3
<CUSTOM LOW> Lower 5bits
D1
D0
0
0
0
<CUSTOM HIGH> Upper 6 bits
D7-D4
<CUSTOM LOW>
5 lower bits of custom pattern available at the output instead of ADC data.
D5-D0
<CUSTOM HIGH>
6 upper bits of custom pattern available at the output instead of ADC data.
20
D2
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Table 10.
A7–A0
(hex)
D7
1A
<LOW LATENCY>
D6
D5
D4
D3
<OFFSET TC>
Offset correction time constant
D2
D1
D0
<GAIN CORRECTION>
0 to 0.5 dB, steps of 0.05 dB
D2–D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
<GAIN CORRECTION> Enables fine gain correction in steps of 0.05 dB (same correction applies to both channels)
0 dB gain, default after reset
+0.5 dB gain
+0.10 dB gain
+0.15 dB gain
+0.20 dB gain
+0.25 dB gain
+0.30 dB gain
+0.35 dB gain
+0.40 dB gain
+0.45 dB gain
+0.5 dB gain
D6-D4
000
001
010
011
100
101
110
111
<OFFSET TC> Time constant of offset correction in number of clock cycles (seconds, for sampling frequency =
125MSPS)
227 (1.1 s)
226 (0.55 s)
225 (0.27 s)
224 (0.13 s)
228 (2.15 s)
229 (4.3 s)
227 (1.1 s)
227 (1.1 s)
D7
0
1
<LOW LATENCY>
Default latency, 13 clock cycles
Low latency enabled, 9 clock cycles – Digital Processing Block is bypassed.
Table 11.
A7–A0
(hex)
D7
1B
<OFFSET Enable>
Offset correction
enable
D6
D5
D4
D3
0
<FILTER COEFF
SELECT>
In-built or custom
coefficients
<DECIMATION
Enable>
Enable decimation
<ODD TAP
Enable>
D2-D0
000
001
011
100
<DECIMATION RATE> Decimation filters
Decimate by 2 (pre-defined or user coefficients can be used)
Decimate by 4 (pre-defined or user coefficients can be used)
No decimation (Pre-defined coefficients are disabled, only custom coefficients are available)
Decimate by 8 (Only custom coefficients are available)
D3
0
1
<ODD TAP ENABLE>
Even taps enabled (24 coefficients)
0 Odd taps enabled (23 coefficients)
D4
0
1
<DECIMATION ENABLE>
Decimation disabled
0 Decimation enabled
D5
0
1
<FILTER COEFF SELECT>
Pre-defined coefficients are loaded in the filter
User-defined coefficients are loaded in the filter (coefficients have to be loaded in registers – to - )
D7
0
1
<OFFSET Enable>
Offset correction disabled
Offset correction enabled
D2
D1
<DECIMATION RATE>
Decimate by 2,4,8
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Table 12.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
1D
0
0
0
0
0
0
D1-D0
00
01
10, 11
<DECIMATION FILTER FREQ BAND> Decimation filters
With decimate by 2, <DECIMATION RATE> = 000:
Low pass filter (–6 dB frequency at Fs/4)
High pass filter (–6 dB frequency at Fs/4)
Unused
00
01
10
11
With decimate by 4, <DECIMATION RATE> = 001:
Low pass filter (-3 dB frequency at Fs/8)
Band pass filter (center frequency at 3Fs/16)
Band pass filter (center frequency at 5Fs/16)
High pass filter (-3 dB frequency at 3Fs/8)
22
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D0
<DECIMATION FILTER FREQ BANDS>
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NC
DRGND
DRVDD
CLKOUT
NC
DA10
DA9
DA8
DA7
DA6
DA5
63
62 61
60
59
58
57
56
55
54
53
52 51
50
DRGND
NC
64
1
NC
DRVDD
DB0
DRGND
PIN DESCRIPTION (CMOS INTERFACE)
49
48
DRVDD
DB1
2
47
DA4
DB2
3
46
DA3
DB3
4
45
DA2
DB4
5
44
DA1
DB5
6
43
DA0
DB6
7
42
NC
DB7
8
41
NC
DB8
9
40
NC
DB9
10
39
DRGND
DB10
11
38
DRVDD
RESET
12
37
CTRL3
SCLK
13
36
CTRL2
SDATA
14
35
CTRL1
SEN
15
34
AVDD
AVDD
28 29
30
31
33
32
AGND
27
AGND
26
INM_A
AGND
25
INP_A
INM_B
24
AGND
INP_B
23
AGND
AGND
22
CLKM
21
CLKP
20
AGND
19
VCM
18
AGND
16
17
AGND
AVDD
PAD (Connected to DRGND )
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Pin Assignments (CMOS INTERFACE)
PIN NAME
DESCRIPTION
AVDD
Analog power supply
AGND
Analog ground
CLKP, CLKM
INP_A, INM_A
PIN NUMBER
NUMBER OF
PINS
16, 33, 34
3
17, 18, 21, 22, 24,
27, 28, 31, 32
9
Differential input clock
25, 26
2
Differential input signal – channel A
29, 30
2
INP_B, INM_B
Differential input signal – channel B
19, 20
2
VCM
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets
the ADC internal references.
23
1
RESET
Serial interface RESET input.
In serial interface mode, the user must initialize internal registers through
hardware RESET by applying a high-going pulse on this pin or by using
software reset (refer to Serial Interface section).
In parallel interface mode, the user has to tie RESET pin permanently high.
(SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin
has an internal 100 kΩ pull-down resistor.
12
1
SCLK
This pin functions as serial interface clock input when RESET is low.
It functions as analog control pin when RESET is tied high & controls coarse
gain and internal/external reference selection. See Table 4 for details.
The pin has an internal pull-down resistor to ground.
13
1
SDATA
This pin functions as serial interface data input when RESET is low. The pin has
an internal pull-down resistor to ground.
14
1
SEN
This pin functions as serial interface enable input when RESET is low.
It functions as analog control pin when RESET is tied high & controls the output
interface (LVDS/CMOS) and data format selection. See Table 5 for details.
The pin has an internal pull-up resistor to AVDD.
15
1
CTRL1
These are digital logic input pins. Together they control various power down and
multiplexed mode. see Table 6 for details
35
1
36
1
37
1
CTRL2
CTRL3
DA10 to DA0
Channel A 11-bit data outputs, CMOS
43, 44, 45, 46, 47,
50, 51, 52, 53, 54,
55
11
DB10 to DB0
Channel B 11-bit data outputs, CMOS
2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 63
11
CLKOUT
CMOS Output clock
57
1
DRVDD
Digital supply
1, 38, 48, 58
4
DRGND
Digital ground
39, 49, 59, 64
4
PAD
Digital ground. Solder the pad to the digital ground on the board using multiple
vias for good electrical and thermal performance.
–
–
NC
Do not connect
40, 41, 42, 56, 60,
61, 62
7
24
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DB2M
2
DB2P
3
DB4M
NC
DRGND
DRVDD
CLKOUTP
CLKOUTM
DA10P
DA10M
DA8P
DA8M
DA6P
DA6M
63
62 61
60
59
58
57
56
55
54
53
52 51
50
DRGND
NC
64
1
DB0M
DRVDD
DB0P
DRGND
PIN DESCRIPTION (LVDS INTERFACE)
49
48
DRVDD
47
DA4P
46
DA4M
4
45
DA2P
DB4P
5
44
DA2M
DB6M
6
43
DA0P
DB6P
7
42
DA0M
DB8M
8
41
NC
DB8P
9
40
NC
DB10M
10
39
DRGND
DB10P
11
38
DRVDD
RESET
12
37
CTRL3
SCLK
13
36
CTRL2
SDATA
14
35
CTRL1
SEN
15
34
AVDD
AVDD
AGND
27
28 29
30
31
33
32
AGND
AGND
26
AGND
INM_B
25
INM_A
INP_B
24
INP_A
AGND
23
AGND
22
AGND
21
CLKM
20
CLKP
19
AGND
18
VCM
16
17
AGND
AVDD
PAD (Connected to DRGND )
Pin Assignments (LVDS INTERFACE)
PIN NAME
DESCRIPTION
PIN
NUMBER
NUMBER OF
PINS
AVDD
Analog power supply
16, 37, 38
3
AGND
Analog ground
17, 18, 21,
22, 24, 27,
28, 31,32
9
CLKP, CLKM
Differential input clock
25, 26
2
INP_A, INM_A
Differential input signal – Channel A
29, 30
2
INP_B, INM_B
Differential input signal – Channel B
19, 20
2
VCM
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets the
ADC internal references.
23
1
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Pin Assignments (LVDS INTERFACE) (continued)
PIN NAME
DESCRIPTION
PIN
NUMBER
NUMBER OF
PINS
RESET
Serial interface RESET input.
In serial interface mode, the user must initialize internal registers through hardware
RESET by applying a high-going pulse on this pin or by using software reset (refer to
Serial Interface section).
In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK,
SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal
100 kΩ pull-down resistor.
12
1
SCLK
This pin functions as serial interface clock input when RESET is low.
It functions as analog control pin when RESET is tied high & controls coarse gain and
internal/external reference selection. See Table 4 for details.
The pin has an internal pull-down resistor to ground.
13
1
SDATA
This pin functions as serial interface data input when RESET is low. The pin has an
internal pull-down resistor to ground.
14
1
SEN
This pin functions as serial interface enable input when RESET is low.
It functions as analog control pin when RESET is tied high & controls the output
interface (LVDS/CMOS) and data format selection. See Table 5 for details.
The pin has an internal pull-up resistor to AVDD.
15
1
CTRL1
These are digital logic input pins. Together they control various power down and
multiplexed mode. See Table 6 for details.
35
1
36
1
CTRL2
CTRL3
37
1
40, 41, 60,
61
4
Channel A Differential output data 0 and D0 multiplexed, true
43
1
Channel A Differential output data 0 and D0 multiplexed, complement
42
1
DA2P
Channel A Differential output data D1 and D2 multiplexed, true
45
1
DA2M
Channel A Differential output data D1 and D2 multiplexed, complement
44
1
DA4P
Channel A Differential output data D3 and D4 multiplexed, true
47
1
DA4M
Channel A Differential output data D3 and D4 multiplexed, complement
46
1
DA6P
Channel A Differential output data D5 and D6 multiplexed, true
51
1
DA6M
Channel A Differential output data D5 and D6 multiplexed, complement
50
1
DA8P
Channel A Differential output data D7 and D8 multiplexed, true
53
1
DA8M
Channel A Differential output data D7 and D8 multiplexed, complement
52
1
DA10P
Channel A Differential output data D9 and D10 multiplexed, true
55
1
DA10M
Channel A Differential output data D9 and D10 multiplexed, complement
54
1
CLKOUTP
Differential output clock, true
57
1
CLKOUTM
Differential output clock, complement
56
1
DB0P
Channel B Differential output data 0 and D0 multiplexed, true
63
1
DB0M
Channel B Differential output data 0 and D0 multiplexed, complement
62
1
DB2P
Channel B Differential output data D1 and D2 multiplexed, true
3
1
DB2M
Channel B Differential output data D1 and D2 multiplexed, complement
2
1
DB4P
Channel B Differential output data D3 and D4 multiplexed, true
5
1
DB4M
Channel B Differential output data D3 and D4 multiplexed, complement
4
1
DB6P
Channel B Differential output data D5 and D6 multiplexed, true
7
1
DB6M
Channel B Differential output data D5 and D6 multiplexed, complement
6
1
DB8P
Channel B Differential output data D7 and D8 multiplexed, true
9
1
DB8M
Channel B Differential output data D7 and D8 multiplexed, complement
8
1
DB10P
Channel B Differential output data D9 and D10 multiplexed, true
11
1
DB10M
Channel B Differential output data D9 and D10 multiplexed, complement
10
1
DRVDD
Digital supply
1, 38, 48,
58
4
NC
Do not connect
DA0P
DA0M
26
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Pin Assignments (LVDS INTERFACE) (continued)
PIN NAME
DESCRIPTION
DRGND
Digital ground
PAD
Digital ground. Solder the pad to the digital ground on the board using multiple vias for
good electrical and thermal performance.
PIN
NUMBER
NUMBER OF
PINS
39, 49, 59,
64
4
–
–
TYPICAL CHARACTERISTICS
All plots are at 25°C, AVDD = 3.3V, DRVDD = 3.3V, sampling frequency = 125 MSPS, sine wave clock, 50% clock duty cycle,
–1dBFS differential analog input, internal reference mode, 0 dB gain, applies to CMOS and LVDS interfaces (unless
otherwise noted).
SPECTRUM FOR 20MHZ INPUT SIGNAL
SPECTRUM FOR 70MHZ INPUT SIGNAL
0
0
SFDR = 88.8 dBc
SINAD = 67 dBFS
SNR = 67.1 dBFS
THD = 88 dBc
−40
−60
−80
−40
−60
−80
−100
−100
−120
−120
−140
−140
0
10
20
30
40
50
60
f − Frequency − MHz
0
10
20
30
40
50
60
f − Frequency − MHz
G001
G002
Figure 8.
Figure 9.
SPECTRUM FOR 190MHZ INPUT SIGNAL
SPECTRUM FOR 2-TONE INPUT SIGNAL
(INTERMODULATION DISTORTION)
0
0
SFDR = 79.1 dBc
SINAD = 66.4 dBFS
SNR = 66.7 dBFS
THD = 77.5 dBc
−20
−40
fIN1 = 190.1 MHz, –7 dBFS
fIN2 = 185.3 MHz, –7 dBFS
2-Tone IMD = –88.8 dBFS
SFDR = –96 dBFS
−20
Amplitude − dB
Amplitude − dB
SFDR = 86.7 dBc
SINAD = 67 dBFS
SNR = 67 dBFS
THD = 85.1 dBc
−20
Amplitude − dB
Amplitude − dB
−20
−60
−80
−40
−60
−80
−100
−100
−120
−120
−140
−140
0
10
20
30
40
f − Frequency − MHz
50
60
0
G003
Figure 10.
10
20
30
40
50
f − Frequency − MHz
60
G004
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = 3.3V, DRVDD = 3.3V, sampling frequency = 125 MSPS, sine wave clock, 50% clock duty cycle,
–1dBFS differential analog input, internal reference mode, 0 dB gain, applies to CMOS and LVDS interfaces (unless
otherwise noted).
SFDR vs INPUT FREQUENCY (CMOS INTERFACE)
SNR vs INPUT FREQUENCY (CMOS INTERFACE)
94
70
92
88
SNR − dBFS
SFDR − dBc
69
Gain = 3.5 dB
90
86
84
82
68
Gain = 0 dB
67
Gain = 3.5 dB
66
80
Gain = 0 dB
65
78
76
64
0
25
50
75
100
125
150
175
200
fIN − Input Frequency − MHz
0
25
50
75
100
125
150
175
200
fIN − Input Frequency − MHz
G005
Figure 12.
G006
Figure 13.
SFDR vs INPUT FREQUENCY (LVDS INTERFACE)
SNR vs INPUT FREQUENCY (LVDS INTERFACE)
95
70
93
69
Gain = 3.5 dB
89
SNR − dBFS
SFDR − dBc
91
87
85
83
68
Gain = 0 dB
67
81
Gain = 3.5 dB
Gain = 0 dB
79
66
77
75
65
0
25
50
75
100
125
150
175
200
fIN − Input Frequency − MHz
0
25
50
75
100
G007
Figure 14.
SFDR vs INPUT FREQUENCY ACROSS GAINS
175
200
G008
SINAD vs INPUT FREQUENCY ACROSS GAINS
72
Input adjusted to get −1dBFS input
Input adjusted to get −1dBFS input
70
2 dB
3 dB
0 dB
5 dB
4 dB
SINAD − dBFS
95
SFDR − dBc
150
Figure 15.
100
90
85
80
6 dB
1 dB
0 dB
1 dB
68
2 dB
66
64
3 dB
5 dB
4 dB
62
75
6 dB
60
0
25
50
75
100
125
150
fIN − Input Frequency − MHz
175
200
0
25
G009
Figure 16.
28
125
fIN − Input Frequency − MHz
50
75
100
125
150
fIN − Input Frequency − MHz
175
200
G010
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = 3.3V, DRVDD = 3.3V, sampling frequency = 125 MSPS, sine wave clock, 50% clock duty cycle,
–1dBFS differential analog input, internal reference mode, 0 dB gain, applies to CMOS and LVDS interfaces (unless
otherwise noted).
PERFORMANCE vs AVDD SUPPLY
PERFORMANCE vs DRVDD SUPPLY
88
88
69.0
87
87
68.5
SFDR
69.0
fIN = 70.1 MHz
AVDD = 3.31 V
68.5
85
67.5
SNR
84
3.1
3.2
3.3
3.4
AVDD − Supply Voltage − V
67.5
SNR
84
67.0
83
66.5
82
1.8
66.0
3.6
3.5
85
2.0
2.2
2.4
PERFORMANCE vs TEMPERATURE
87
68.5
85
67.5
SNR
84
67.0
83
SFDR − dBc
68.0
66.5
80
T − Temperature − °C
90
SFDR
80
50
75
SNR
40
65
20
60
10
55
50
−50
−40
0
G014
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
fIN = 20.1 MHz
72
SFDR
71
fIN = 20.1 MHz
90
70
88
70
86
69
68
SNR
82
67
80
66
1.5
Input Clock Amplitude − VPP
2.0
65
2.5
SFDR − dBc
71
SNR − dBFS
SFDR − dBc
−10
92
73
1.0
−20
Figure 21.
PERFORMANCE vs INPUT CLOCK AMPLITUDE
0.5
−30
Input Amplitude − dBFS
G013
94
78
0.0
70
30
Figure 20.
84
85
60
0
−60
66.0
60
95
fIN = 20.1 MHz
70
SNR − dBFS
SFDR − dBc
86
90
G012
80
SFDR
92
66.0
3.6
100
90
40
3.4
PERFORMANCE vs INPUT AMPLITUDE
fIN = 70.1 MHz
20
3.2
100
69.0
0
3.0
Figure 19.
88
−20
2.8
DRVDD − Supply Voltage − V
G011
Figure 18.
82
−40
2.6
SNR − dBFS
82
3.0
66.5
fIN = 70.1 MHz
DRVDD = 3.31 V
68.0
88
69
SFDR
86
68
SNR
84
67
82
66
80
SNR − dBFS
83
67.0
86
SNR − dBFS
68.0
SFDR − dBc
86
SNR − dBFS
SFDR − dBc
SFDR
65
35
40
G015
Figure 22.
45
50
55
60
65
Input Clock Duty Cycle − %
G016
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = 3.3V, DRVDD = 3.3V, sampling frequency = 125 MSPS, sine wave clock, 50% clock duty cycle,
–1dBFS differential analog input, internal reference mode, 0 dB gain, applies to CMOS and LVDS interfaces (unless
otherwise noted).
OUTPUT NOISE HISTOGRAM (INPUTS TIED TO
COMMON-MODE)
PERFORMANCE IN EXTERNAL REFERENCE MODE
70
93
75
fIN = 20.1 MHz
External Reference Mode
60
73
40
30
SFDR
89
SNR − dBFS
SFDR − dBc
Occurence − %
91
50
71
87
69
20
SNR
85
67
10
0
83
1.30
1018 1019 1020 1021 1022 1023 1024 1025
Output Code
1.40
1.45
1.50
1.55
1.60
1.65
65
1.70
VVCM − VCM Voltage − V
G017
G018
Figure 25.
COMMON-MODE REJECTION RATIO vs FREQUENCY
POWER DISSIPATION vs SAMPLING FREQUENCY (DDR
LVDS AND CMOS)
0
1.0
−10
0.9
PD − Power Dissipation − W
Figure 24.
−20
−30
CMRR − dBc
1.35
−40
−50
−60
−70
−80
fIN = 2.5 MHz
CL = 5 pF
0.8
LVDS
0.7
0.6
0.5
CMOS
0.4
0.3
0.2
0.1
−90
0.0
−100
0
25
50
75
100
125
150
175
0
200
f − Frequency − MHz
25
50
75
100
fS − Sampling Frequency − MSPS
G019
Figure 26.
125
G020
Figure 27.
DRVDD CURRENT vs SAMPLING FREQUENCY ACROSS
LOAD CAPACITANCE (CMOS)
70
3.3 V, No Load
DRVDD Current − mA
60
1.8 V, 5 pF
50
1.8 V, 10 pF
3.3 V, 5 pF
40
3.3 V, 10 pF
30
20
10
1.8 V, No Load
0
0
25
50
75
100
fS − Sampling Frequency − MSPS
125
G021
Figure 28.
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APPLICATION INFORMATION
THEORY OF OPERATION
ADS62P15 is a low power 11-bit dual channel pipeline ADC family fabricated in a CMOS process using switched
capacitor techniques.
The conversion process is initiated by a rising edge of the external input clock. Once the signal is captured by
the input sample and hold, the input sample is sequentially converted by a series of small resolution stages, with
the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the
pipeline resulting in a data latency of 14 clock cycles. The output is available as 11-bit data, in DDR LVDS or
CMOS and coded in either straight offset binary or binary 2s complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture.
This differential topology results in very good AC performance even for high input frequencies at high sampling
rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5V, available on
VCM pin 13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM
+ 0.5V and VCM – 0.5V, resulting in a 2VPP differential input swing. The maximum swing is determined by the
internal reference voltages REFP (2.5V nominal) and REFM (0.5V, nominal).
Sampling
switch
Lpkg~ 2 nH
Sampling
capacitor
RCR Filter
INP
25 E
Cbond
~ 1 pF
Cpar2
1 pF
50 E
Resr
100 E
3.2 pF
INM
Resr
100 E
Ron
10 E
Csamp
4.0 pF
Ron
15 E
25 E
Cbond
~ 1 pF
Csamp
4.0 pF
Cpar1
0.8 pF
50 E
Lpkg~ 2 nH
Ron
15 E
Sampling
capacitor
Cpar2
1 pF
Sampling
switch
Figure 29. Analog Input Equivalent Circuit
The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins
to the sampled voltage).
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1
0
Magnitude − dB
−1
−2
−3
−4
−5
−6
−7
0
100
200
300
400
500
fI − Input Frequency − MHz
600
G022
Figure 30. ADC Analog Bandwidth
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection. A <5 Ω resistor in series with each input pin is recommended
to damp out ringing caused by the package parasitics.
It is also necessary to present low impedance (50 Ω) for the common mode switching currents. This can be
achieved by using two resistors from each input terminated to the common mode voltage (VCM).
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. While doing this, the ADC input impedance must be considered.
Figure 31 and Figure 32 show the impedance (Zin = Rin || Cin) looking into the ADC input pins.
R − Resistance − kΩ
100
10
1
0.1
0.01
0
100
200
300
400
f − Frequency − MHz
500
600
G023
Figure 31. ADC Analog Input Resistance (Rin) Across Frequency
32
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9
C − Capacitance − pF
8
7
6
5
4
3
2
1
0
0
100
200
300
400
500
f − Frequency − MHz
600
G024
Figure 32. ADC Analog Input Capacitance (Cin) Across Frequency
Using RF-Transformer Based Drive Circuits
Figure 33 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that
can be used for low input frequencies (about 100 MHz). The single-ended signal is fed to the primary winding of
the RF transformer. The transformer is terminated on the secondary side. Putting the termination on the
secondary side helps to shield the kickbacks caused by the sampling circuit from the RF transformer’s leakage
inductances. The termination is accomplished by two resistors connected in series, with the center point
connected to the 1.5 V common mode (VCM pin). The value of the termination resistors (connected to common
mode) has to be low ( <100 Ω) to provide a low-impedance path for the ADC common-mode switching currents.
0.1 mF
INP
0.1mF
25E
25E
INM
1:1
VCM
Figure 33. Drive Circuit at Low Input Frequencies
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results
in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps
minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 34 shows an
example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the
shaded box) may be required between the two transformers to improve the balance between the P and M sides.
The center point of this termination must be connected to ground.
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0.1 mF
INP
50 E
0.1 mF
50E
50E
50 E
INM
1 :1
1:1
VCM
Figure 34. Drive Circuit at High Input Frequencies
Using Differential Amplifier Drive Circuits
Figure 35 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to
differential output that can be interface to the ADC analog input pins. In addition to the single-ended to differential
conversion, the amplifier also provides gain (10 dB). RFIL helps to isolate the amplifier outputs from the switching
input of the ADC. Together with CFIL it also forms a low-pass filter that band-limits the noise (and signal) at the
ADC input. As the amplifier output is ac-coupled, the common-mode voltage of the ADC input pins is set using
two 200 W resistors connected to VCM.
The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC
input pins can be biased to 1.5 V. In this case, use +4 V and –1 V supplies for the THS4509 so that its output
common-mode voltage (1.5 V) is at mid-supply.
RF
+VS
500 W
0.1 mF
0.1 mF 10 mF
RFIL
0.1 mF
5W
INP
RG
RS
CFIL
0.1 mF
RT
CFIL
200 W
200 W
5W
INM
RG
RS || RT
RFIL
500 W
0.1 mF
-VS
0.1 mF
VCM
0.1 mF
0.1 mF 10 mF
RF
Figure 35. Drive Circuit Using the THS4509
Input Common-Mode
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1µF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC
sinks a common-mode current in the order of 165 µA (at 125 MSPS). Equation 1 describes the dependency of
the common-mode current and the sampling frequency.
34
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165 mA Fs
125 MSPS
(1)
This equation helps to design the output capability and impedance of the CM driving circuit accordingly.
REFERENCE
ADS62P15 has built-in internal references REFP and REFM, requiring no external components. Design schemes
are used to linearize the converter load seen by the references; this and the on-chip integration of the requisite
reference capacitors eliminates the need for external decoupling. The full-scale input range of the converter can
be controlled in the external reference mode as explained below. The internal or external reference modes can
be selected by programming the serial interface register bit (REF).
INTREF
INTERNAL
REFERENCE
VCM
1 kW
4 kW
INTREF
EXTREF
REFM
REFP
Figure 36. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.
Common-mode voltage (1.5V nominal) is output on VCM pin, which can be used to externally bias the analog
input pins.
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the
VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input voltage corresponding to full-scale is given in Equation 2.
Full-scale differential input pp = (Voltage forced on VCM) × 1.33
In this mode, the 1.5V common-mode voltage to bias the input pins has to be generated externally.
COARSE GAIN AND PROGRAMMABLE FINE GAIN
ADS62P15 includes gain settings that can be used to get improved SFDR performance (over 0dB gain mode).
For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 8.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The
fine gain is programmable in 0.5 dB steps from 0 to 6 dB; however the SFDR improvement is achieved at the
expense of SNR. So, the programmable fine gain makes it possible to trade-off between SFDR and SNR. The
coarse gain makes it possible to get best SFDR but without losing SNR significantly.
The gains can be programmed using the serial interface (bits COARSE GAIN and FINE GAIN). Note that the
default gain after reset is 0dB.
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Table 8. Full-Scale Range Across Gains
GAIN, dB
TYPE
0
Default after reset
FULL-SCALE, VPP
2V
3.5
Coarse (fixed)
1.34
0.5
1.89
1.0
1.78
1.5
1.68
2.0
1.59
2.5
1.50
3.0
Fine (programmable)
3.5
1.42
1.34
4.0
1.26
4.5
1.19
5.0
1.12
5.5
1.06
6.0
1.00
CLOCK INPUT
The clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with little or
no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using
internal 5 kΩ resistors as shown in Figure 37. This allows using transformer-coupled drive circuits for sine wave
clock or ac-coupling for LVPECL, LVDS clock sources (Figure 39 and Figure 40).
Clock buffer
Lpkg
~2 nH
10 W
CLKP
Cbond
~ 1 pF
Ceq
Ceq
5 kW
Resr
~100 W
VCM
6 pF
5 kW
Lpkg
~2 nH
10 W
CLKM
Cbond
~ 1 pF
Resr
~100 W
Ceq ~ 1 to 3 pF, equivalent input capacitance of clock buffer
Figure 37. Internal Clock Buffer
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100k
Impedance − Ω
10k
1k
100
10
5
25
45
65
85
105
fS − Sampling Frequency − MSPS
125
G028
Figure 38. Clock Input Impedance
0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS Clock Input
CLKM
0.1 mF
Figure 39. Differential Clock Driving Circuit
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground with a
0.1-µF capacitor, as shown in Figure 40.
0.1 mF
CLKP
CMOS Clock Input
CLKM
0.1 mF
Figure 40. Single-Ended Clock Driving Circuit
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input.
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POWER DOWN
ADS62P15 has three power down modes – power down global, individual channel standby and individual
channel output buffer disable. These can be set using either the serial register bits or using the control pins
CTRL1 to CTRL3.
Table 9. Power Down Modes
CONFIGURE USING
POWER DOWN MODES
SERIAL INTERFACE
<POWER DOWN MODES>
PARALLEL CONTROL PINS
CTRL1
CTRL2
WAKE-UP
TIME
CTRL3
Normal operation
000
low
low
low
—
Channel A output buffer disabled
001
low
low
high
Fast (100 ns)
Channel B output buffer disabled
010
low
high
low
Fast (100 ns)
Channel A and B output buffer disabled
011
low
high
high
Fast (100 ns)
Channel A and B powered down
100
high
low
low
Slow (15 µS)
Channel A standby
101
high
low
high
Fast (100 ns)
Channel B standby
110
high
high
low
Fast (100 ns)
Multiplexed (MUX) mode – Output data of
channel A and B is multiplexed and available
on DA13 to DA0 pins.
111
high
high
high
—
Power Down Global
In this mode, the entire chip including both the A/D converters, internal reference and the output buffers are
powered down resulting in reduced total power dissipation of about 50 mW. The output buffers are in high
impedance state. The wake-up time from the global power down to data becoming valid in normal mode is
typically 15 µs.
Channel Standby (Individual or Both Channels)
This mode allows the individual ADCs to be powered down. The internal references are active & this results in
fast wake-up time, about 100 ns. The total power dissipation in standby is about 482 mW.
Output Buffer Disable (Individual or Both Channels)
Each channel’s output buffer can be disabled and put in high impedance state -- wakeup time from this mode is
fast, about 100 ns.
Input Clock Stop
In addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1
MSPS. The power dissipation is about 140 mW.
POWER SUPPLY SEQUENCE
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated in the device. Externally, they can be driven from separate supplies or derived from a single supply.
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DIGITAL OUTPUT INFORMATION
ADS62P15 provides 11 bit data per channel and a common output clock synchronized with the data. The output
interface can be either parallel CMOS or DDR LVDS voltage levels and can be selected using serial register bit
<OUTPUT INTERFACE> or parallel pin SEN.
Parallel CMOS Interface
In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V
(typical). Each data bit is output on separate pin as CMOS voltage level, every clock cycle (see Figure 41).
For DRVDD > 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving
chip. The rising edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed.
It is recommended to minimize the load capacitance seen by data and clock output pins by using short traces to
the receiver. Also, match the output data and clock traces to minimize the skew between them.
For DRVDD < 2.2 V, it is recommended to use external clock (for example, input clock delayed to get desired
setup/hold times).
CMOS
Output Buffers
DA0
DA1
DA2
11 Bit Channel A
Data
DA3
DA9
DA10
CLKOUT
DB0
DB1
DB2
11 Bit Channel B
Data
DB3
DB9
DB10
Figure 41. CMOS Output Interface
Output Buffer Strength Programmability
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of
sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made
stronger. To minimize this, ADS62P15 CMOS output buffers are designed with controlled drive strength to get
best SNR. The default drive strength also ensures wide data stable window for load capacitances up to 5 pF and
DRVDD supply voltage >2.2 V.
To ensure wide data stable window for load capacitance > 5 pF, there exists option to increase the output data
and clock drive strengths using the serial interface ( DATAOUT STRENGTH and CLKOUT STRENGTH). Note
that for DRVDD supply voltage <2.2 V, it is recommended to use maximum drive strength (for any value of load
capacitance).
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CMOS Mode Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital current due to CMOS output switching = CL × DRVDD × (N × FAVG),
where CL = load capacitance, N × FAVG = average number of output bits switching.
Figure 28 shows the current with various load capacitances across sampling frequencies at 2 MHz analog input
frequency.
DDR LVDS Interface
The LVDS interface works only with 3.3V DRVDD supply. In this mode, the 11 data bits of each channel and a
common output clock are available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits
are multiplexed and output on each LVDS differential pair every clock cycle (DDR – Double Data Rate,
Figure 43).
LVDS Buffers
11 Bit Channel A
Data
Pins
DA0P
DA0M
Data bits D0, D1
DA2P
DA2M
Data bits D2, D3
DA10P
DA10M
Data bits D9, D10
CLKOUTP
CLKOUTM
11 Bit Channel B
Data
Output Clock
DB0P
DB0M
Data bits D0, D1
DB2P
DB2M
Data bits D2, D3
DB10P
DB10M
Data bits D9, D10
Figure 42. DDR LVDS Outputs
Odd data bits D1, D3, D5, D7, D9 are output at the rising edge of CLKOUTP and even data bits D0, D2, D4, D6,
D8, D10 are output at the falling edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be
used to capture all the data bits.
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CLKOUTM
CLKOUTP
DA0 (DB0)
0
D0
0
D0
DA2 (DB2)
D1
D2
D1
D2
DA4 (DB4)
D3
D4
D3
D4
DA6 (DB6)
D5
D6
D5
D6
DA8 (DB8)
D7
D8
D7
D8
DA10 (DB10)
D9
D10
D9
D10
Sample N
Sample N + 1
Figure 43. DDR LVDS Interface
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV
single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to
2.5 mA, 4.5 mA, and 1.75 mA (LVDS CURRENT). In addition, there exists a current double mode, where this
current is doubled for the data and output clock buffers (register bits CURRENT DOUBLE).
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistances available are –300 Ω, 185 Ω, and 150 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistances. This results in eight effective terminations from open (no
termination) to 60Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100 Ω internal and 100 Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode. Figure 44 and Figure 45 compare the LVDS eye diagrams without and with 100 Ω internal termination.
With internal termination, the eye looks clean even with 10 pF load capacitance (from each output pin to ground).
The terminations can be programmed using register bits (LVDS TERMINATION).
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Figure 44. LVDS Eye Diagram – No Internal Termination, External Termination = 100 Ω
Figure 45. LVDS Eye Diagram – With 100Ω Internal Termination, External termination = 100 Ω and LVDS
current double mode enabled
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Output Data Format
Two output data formats are supported – 2s complement and straight binary. They can be selected using the
serial interface register bit <DATA FORMAT> or controlling the SEN pin in parallel configuration mode.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive
overdrive, the output code is 0x7FF in offset binary output format, and 0x3FF in 2s complement output format.
For a negative input overdrive, the output code is 0x000 in offset binary output format and 0x400 in 2s
complement output format.
Multiplexed Output mode
This mode is available only with CMOS interface. In this mode, the digital outputs of both the channels are
multiplexed and output on a single bus (DB0-DB10 pins), as per the timing diagram shown in Figure 46. The
channel A output pins (DA0-DA10) are tri-stated. Since the output data rate on the DB bus is effectively doubled,
this mode is recommended only for low sampling frequencies (<65 MSPS).
This mode can be enabled using register bits <POWER DOWN MODES> or using the parallel pins CTRL1 -3 ().
CLKOUT
DB0
DA0
DB0
DA0
DB0
DB1
DA1
DB1
DA1
DB1
DB2
DA2
DB2
DA2
DB2
DB10
DA10
DB10
DA10
DB10
Sample N
Sample N + 1
Figure 46. Multiplexed mode – Output Timing
Low Latency Mode
The default latency of ADS62P15 is 14 clock cycles. For applications, which cannot tolerate large latency,
ADS62P15 includes a special mode with 10 clock cycles latency. In the low latency condition, the Digital
Processing block is bypassed and its features (offset correction, fine gain, decimation filters) are not available.
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DETAILS OF DIGITAL PROCESSING BLOCK
CLIPPER
From ADC
11bits
output
11bits
11bits
11 bits
11bits
To LVDS or CMOS
output buffers
FINE GAIN
(0 to 6 dB, 0.5 dB
steps)
0
OFFSET
ESTIMATION
BLOCK
24TAP FILTER
- LOW PASS
- HIGH PASS
- BAND PASS
GAIN
CORRECTION
(0.05dB steps)
DISABLE
OFFSET
CORRECTION
DECIMATION
BY2/4/8
FILTER
SELECTION
11bits
BYPASS
FILTER
BYPASS
DECIMATION
FREEZE
OFFSET
CORRECTION
DIGITAL
PROCESSING BLOCK
Figure 47. Digital Processing Block Diagram
Offset Correction
ADS62P15 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10mV. The
correction can be enabled using the serial register bit (OFFSET LOOP EN). Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using register bits
(OFFSET LOOP TC) as described in Table 10.
Table 10. Time Constant of Offset Correction Algorithm
(1)
44
<OFFSET LOOP TC>
D6-D5-D4
Time constant (TCCLK),
number of clock cycles
Time constant, sec
(=TCCLK × 1/Fs) (1)
000
227
1.1
001
226
0.55
010
225
0.27
011
224
0.13
100
228
2.15
101
29
2
4.3
110
227
1.1
111
227
1.1
Sampling frequency, Fs = 125 MSPS
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It is also possible to freeze the offset correction using the serial interface (<OFFSET LOOP FREEZE>). Once
frozen, the offset estimation becomes inactive and the last estimated value is used for correction every clock
cycle. Note that the offset correction is disabled by default after reset.
Figure 48 shows the time response of the offset correction algorithm, after it is enabled.
1032
1030
Code − LSB
1028
Device With
Offset Cancelled
1026
1024
1022
Offset Loop
Enabled Here
1020
Device With
Initial Offset
1018
1016
0
2
4
6
8
10
12
t − Time − s
14
G029
Figure 48. Time Response of Offset Correction
Gain Correction
ADS62P15 has ability to make fine corrections to the ADC channel gain. The corrections can be done in steps of
0.05 dB, up to a maximum of 0.5 dB, using the register bits (GAIN CORRECTION). Only positive corrections are
supported and the same correction applies to both the channels.
Table 11. Gain Correction Values
<GAIN CORRECTION>
D3-D2-D1-D0
Amount of correction,
dB
0000
0
0001
+0.05
0010
+0.1
0011
+0.15
0100
+0.20
0101
+0.25
0110
+0.30
0111
+0.35
1000
+0.40
1001
+0.45
1010
+0.5
Other combinations
Unused
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Decimation Filters
ADS62P15 includes option to decimate the ADC output data with in-built low pass, high pass or band pass filters.
The decimation rate and type of filter can be selected using register bits (DECIMATION RATE) and
(DECIMATION FILTER TYPE). Decimation rates of 2, 4 or 8 are available and either low pass, high pass or
band pass filters can be selected (see Table 12). By default, the decimation filter is disabled – use register bit
<DECIMATION ENABLE> to enable it.
Table 12. Decimation Filter Modes
COMBINATION OF DECIMATION RATES AND FILTER TYPES
<DECIMATIO
N FILTER
FREQ
BAND>
<FILTER
COEFF
SELECT
>
<DECIMATI
ON
ENABLE>
DECIMATION
TYPE OF FILTER
<DECIMATION
RATE>
Decimate by 2
In-built low pass filter (pass band = 0 to Fs/4)
0
0
0
0
0
0
1
In-built high pass filter (pass band = Fs/4 to Fs/2)
0
0
0
0
1
0
1
In-built low pass filter (pass band = 0 to Fs/8)
0
0
1
0
0
0
1
0
0
1
0
1
0
1
In-built 3 band pass filter (pass band = Fs/4 to 3Fs/8)
0
0
1
1
0
0
1
In-built last band pass filter (pass band = 3Fs/8 to Fs/2)
0
0
1
1
1
0
1
Decimate by 2
Custom filter (user programmable coefficients)
0
0
0
X
X
1
1
Decimate by 4
Custom filter (user programmable coefficients)
0
0
1
X
X
1
1
Decimate by 8
Custom filter (user programmable coefficients)
1
0
0
X
X
1
1
No decimation
Custom filter (user programmable coefficients)
0
1
1
X
X
1
0
Decimate by 4
nd
In-built 2
band pass filter (pass band = Fs/8 to Fs/4)
rd
Decimation Filter Equation
The decimation filter is implemented as 24-tap FIR with symmetrical coefficients (each coefficient is 12-bit
signed). The filter equation is:
y(n) +
ǒ21 Ǔ
[h0
11
x(n) ) h1
x(n * 1) ) h2
x(n * 2) ) AAA ) h11
x(n * 11) ) h11
x(n * 12) ) AAA ) h1
x(n * 22) ) h0
x(n * 23)]
(3)
By setting the register bit <ODD TAP ENABLE> = 1, a 23-tap FIR is implemented:
y(n) +
ǒ21 Ǔx[h0
11
x(n) ) h1
x(n * 1) ) h2
x(n * 2) ) AAA ) h10
x(n * 10) ) h11
x(n * 11) ) h10
x(n * 12) ) AAA ) h1
x(n * 21) ) h0
x(n * 22)]
(4)
In the above equations,
h0, h1 …h11 are 12-bit signed representation of the coefficients,
x(n) is the input data sequence to the filter
y(n) is the filter output sequence
Pre-defined Coefficients
The in-built filter types (low pass, high pass and band pass) use pre-defined coefficients. The frequency
response of the in-built filters is shown in Figure 49 and Figure 50.
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5
0
Magnitude − dB
−5
−10
Low Pass
High Pass
−15
−20
−25
−30
−35
−40
−45
0.0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency − f/fS
G025
Figure 49. Decimate by 2 Filter Response
5
0
Magnitude − dB
−5
−10
Low Pass
High Pass
−15
−20
−25
−30
−35
−40
−45
0.0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency − f/fS
G026
Figure 50. Decimate by 4 Filter Response
5
0
Magnitude − dB
−5
−10
−15
−20
−25
−30
−35
−40
−45
0.0
1st Bandpass
2nd Bandpass
0.1
0.2
0.3
0.4
Normalized Frequency − f/fS
0.5
G027
Figure 51. Decimate by 4 Bandpass Response
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Table 13. Predefined Coefficients for Decimation by 2 Filters
COEFFICIENTS
DECIMATE BY 2
LOW PASS FILTER
HIGH PASS FILTER
h0
23
-22
h1
-37
-65
h2
-6
-52
h3
68
30
h4
-36
66
h5
-61
-35
h6
35
-107
h7
118
38
h8
-100
202
h9
-197
-41
h10
273
-644
h11
943
1061
Table 14. Predefined Coefficients for Decimation by 4 Filters
COEFFICIENTS
DECIMATE BY 4
LOW PASS FILTER
1st BAND PASS FILTER
2ND BAND PASS FILTER
h0
-17
-7
-34
HIGH PASS FILTER
32
h1
-50
19
-34
-15
h2
71
-47
-101
-95
h3
46
127
43
22
h4
24
73
58
-8
h5
-42
0
-28
-81
h6
-100
86
-5
106
h7
-97
117
-179
-62
h8
8
-190
294
-97
h9
202
-464
86
310
h10
414
-113
-563
-501
h11
554
526
352
575
Custom Filter Coefficients with Decimation
The filter coefficients can also be programmed by the user (custom). For custom coefficients, set the register bit
(FILTER COEFF SELECT)and load the coefficients (h0 to h11) in registers 1E to 2F using the serial interface
(Table 15) as:
Register content = 12 bit signed representation of [real coefficient value × 211]
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Custom Filter Coefficients without Decimation
The filter with custom coefficients can also be used with the decimation mode disabled. In this mode, the filter
implementation is 12-tap FIR:
y(n) +
ǒ21 Ǔx[h6
11
x(n) ) h7
x(n * 1) ) h8
x(n * 2) ) AAA ) h11
x(n * 5) ) h11
x(n * 6) ) AAA ) h7
x(n * 10) ) h6
x(n * 11)]
(5)
Table 15. Register Map of Custom Coefficients
A7–A0
(hex)
D7
D6
D5
1E
1F
Coefficient h2 <7:0>
Coefficient h2 <11:8>
Coefficient h3 <11:4>
Coefficient h4 <7:0>
Coefficient h5 <3:0>
26
Coefficient h4 <11:8>
Coefficient h5 <11:4>
27
Coefficient h6 <7:0>
Coefficient h7 <3:0>
29
Coefficient h6 <11:8>
Coefficient h7 <11:4>
2A
Coefficient h8 <7:0>
Coefficient h9 <3:0>
2C
Coefficient h8 <11:8>
Coefficient h9 <11:4>
2D
2E
D0
Coefficient h0 <11:8>
Coefficient h3 <3:0>
24
2B
D1
Coefficient h1 <11:4>
23
28
D2
Coefficient h0 <7:0>
21
25
D3
Coefficient h1 <3:0>
20
22
D4
Coefficient h10 <7:0>
Coefficient h11 <3:0>
2F
Coefficient h10 <11:8>
Coefficient h11 <11:4>
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BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the EVM User Guide (SLAU237) for details on layout and grounding.
Supply Decoupling
As the ADS62P15 already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that decoupling capacitors can help filter external power supply noise, so the optimum
number of capacitors would depend on the actual application. The decoupling capacitors should be placed very
close to the converter supply pins.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching
noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to
AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being
routed to DRVDD.
Exposed Thermal Pad
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON
PCB Attachment (SLUA271).
50
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay will be different across channels. The maximum variation is specified as
aperture delay variation (channel-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit line
determined by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The
gain error is given as a percentage of the ideal input full-scale range. The gain error does not include the error
caused by the internal reference deviation from ideal value. This is specifed separately as internal reference
error. The maximum variation of the gain error across devices and across channels within a device is specified
separately.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual average
idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at DC and the first nine harmonics.
P
SNR + 10Log10 S
PN
(6)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
PS
SINAD + 10Log10
PN ) PD
(7)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's
full-scale range.
Effective Number of Bits (ENOB) – The ENOB is a measure of a converter’s performance as compared to the
theoretical limit based on quantization noise.
ENOB + SINAD * 1.76
6.02
(8)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
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ADS62P15
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SLAS572 – OCTOBER 2007
THD + 10Log10
PS
PD
(9)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in
units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to
full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a
change in analog supply voltage. The DC PSRR is typically given in units of mV/V.
AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVsup is the change in supply voltage and ΔVout is the resultant change of the
ADC output code (referred to the input), then
PSRR + 20Log10 DVout , expressed in dBc
DVsup
(10)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and
negative overload. The deviation of the first few samples after the overload (from their expected values) is noted.
Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔVout
is the resultant change of the ADC output code (referred to the input), then
CMRR + 20Log10 DVout , expressed in dBc
DVcm_in
(11)
Cross-Talk (only for multi-channel ADC)– This is a measure of the internal coupling of a signal from adjacent
channel into the channel of interest. It is specified separately for coupling from the immediate neighbouring
channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured
by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal
(as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel
input. It is typically expressed in dBc.
52
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS62P15IRGCR
ACTIVE
QFN
RGC
64
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS62P15IRGCRG4
ACTIVE
QFN
RGC
64
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS62P15IRGCT
ACTIVE
QFN
RGC
64
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS62P15IRGCTG4
ACTIVE
QFN
RGC
64
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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Addendum-Page 1
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