Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal transparent latch (3-State) FEATURES MB2373 one setup time before the High-to-Low enable transition. DESCRIPTION • 16-bit transparent latch • Multiple VCC and GND pins minimize The MB2373 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. switching noise • Power-up 3-State • Live insertion/extraction permitted • Power-up reset • 3-State output buffers • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. Each active-Low Output Enable (nOE) controls eight 3-State buffers independent of the latch operation. The MB2373 device is a dual octal transparent latch coupled to two sets of eight 3-State output buffers. The two sections of the device are controlled independently by Enable (nE) and Output Enable (nOE) control gates. When nOE is Low, the latched or transparent data appears at the outputs. When nOE is High, the outputs are in the High–impedance “OFF” state, which means they will neither drive nor load the bus. The data on each set of D inputs are transferred to the latch outputs when the Latch Enable (nE) input is High. The latch remains transparent to the data inputs while nE is High, and stores the data that is present JEDEC JC40.2 Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH tPHL Propagation delay Dn to Qn CL = 50pF; VCC = 5V 2.9 ns CIN Input capacitance VI = 0V or VCC 4 pF COUT Output capacitance VO = 0V or VCC; 3-State 7 pF ICCZ Total supply current Outputs disabled; VCC = 5.5V 500 nA ORDERING INFORMATION PACKAGES 52–pin plastic Quad Flat Pack TEMPERATURE RANGE ORDER CODE DRAWING NUMBER –40°C to +85°C MB2373BB 1418B 52 51 50 49 48 47 46 45 44 43 42 1D3 1D2 GND 1D1 1D0 1E GND 1OE LOGIC SYMBOL 1Q0 1Q1 GND 1Q2 1Q3 PIN CONFIGURATION 41 40 VCC 1 39 V CC 1Q4 2 38 1D4 È È È 47 45 È È È 1Q5 3 37 1D5 GND 4 36 GND 48 1Q0 1OE 1Q6 5 35 1D6 49 1Q1 1Q7 6 34 1D7 51 GND 7 MB2373 52–pin PQFP 33 GND 2Q0 8 32 2D0 2Q1 9 31 2D1 19 21 1E 1D0 44 8 2Q0 2OE 1D1 43 9 2Q1 2D21 31 1Q2 1D2 41 11 2Q2 2D2 29 52 1Q3 1D3 40 12 2Q3 2D3 28 2 1Q4 1D4 38 14 2Q4 2D4 26 3 1Q5 1D5 37 15 2Q5 2D5 25 2E 2D0 32 GND 10 30 GND 2Q2 11 29 2D2 5 1Q6 1D6 35 17 2Q6 2D6 23 2Q3 12 28 2D3 6 1Q7 1D7 34 18 2Q7 2D7 22 August 23, 1993 2D4 2D5 GND 2D6 2D7 2E GND 2Q6 2OE 26 2Q7 21 22 23 24 25 GND 17 18 19 20 2Q5 14 15 16 2Q4 VCC 27 V CC 13 1 853-1669 10587 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal transparent latch (3-State) MB2373 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 44, 43, 41, 40,38, 37, 35, 34, 32, 31, 29, 28, 26, 25, 23, 22 1D0 – 1D7 2D0 – 2D7 Data inputs 48, 49, 51, 52, 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18 1Q0 – 1Q7 2Q0 – 2Q7 Data outputs 47, 19 1OE, 2OE Output enable inputs (active–Low) 45, 21 1E, 2E 4, 7, 10, 16, 20, 24, 30, 33, 36, 42, 46, 50 GND Ground (0V) 1, 13, 27, 39 VCC Positive supply voltage Enable inputs (active–High) LOGIC SYMBOL (IEEE/IEC) 47 19 EN EN 21 45 C1 C1 48 32 43 49 31 9 41 51 29 11 40 52 28 12 38 2 26 14 37 3 25 15 35 5 23 17 34 6 22 18 44 1D 8 1D LOGIC DIAGRAM nD0 nD1 D E nD2 D Q E nD3 D Q E nD4 D Q nD5 D E Q E nD6 D Q E nD7 D Q E D Q E Q nE nOE nQ0 August 23, 1993 nQ1 nQ2 nQ3 2 nQ4 nQ5 nQ6 nQ7 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal transparent latch (3-State) MB2373 FUNCTION TABLE INPUTS H = h = L = l = NC= X = Z = ↓ = INTERNAL OUTPUTS nOE nE nDx OPERATING MODE REGISTER nQ0 – nQ7 L L H H L H L H L H Enable and read register L L ↓ ↓ i h L H L H Latch and read register L L X NC NC Hold H L X NC Z H H Dn Dn Z High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don’t care High impedance “off” state High-to-Low E transition Disable outputs ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC IIK CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. August 23, 1993 3 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal transparent latch (3-State) MB2373 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT MIN MAX 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 10 ns/V –40 +85 °C 2.0 ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range V DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA TYP MAX –0.9 –1.2 MIN UNIT MAX –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC; VOE = GND ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA Output current1 VCC = 5.5V; VO = 2.5V –70 –180 –180 mA Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA VCC = 5.5V; Outputs High, VI = GND or VCC 120 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 44 60 60 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 120 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA II IOFF IPU/PD IO ICEX ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a transition time of up to 100µsec is permitted. August 23, 1993 4 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal transparent latch (3-State) MB2373 AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM UNIT MIN TYP MAX MIN MAX 2 1.3 1.3 2.8 2.9 4.1 4.1 1.3 1.3 4.8 4.8 ns Propagation delay nE to nQx 1 1.8 2.0 3.5 3.5 4.9 4.9 1.8 2.0 5.7 5.5 ns tPZH tPZL Output enable time to High and Low level 4 5 1.2 2.1 2.9 3.8 4.1 5.3 1.2 2.1 5.1 6.1 ns tPHZ tPLZ Output disable time from High and Low level 4 5 1.4 2.0 3.7 3.6 5.0 4.6 1.4 2.0 5.5 5.1 ns tPLH tPHL Propagation delay nDx to nQx tPLH tPHL AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER +25oC Tamb = VCC = +5.0V WAVEFORM Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT MIN TYP MIN 3 1.0 1.0 0.0 0.3 1.0 1.0 ns Hold time, High or Low nDx to nE 3 0.5 0.5 –0.2 0.0 0.5 0.5 ns Enable pulse width High 1 2.5 1.0 2.5 ns ts(H) ts(L) Setup time, High or Low nDx to nE th(H) th(L) tw(H) August 23, 1993 5 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal transparent latch (3-State) MB2373 AC WAVEFORMS nE VM VM VM tw(H) tPHL VM nDx VM tPLH tPHL tPLH nQx nQx VM VM VM ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ Waveform 1. Propagation Delay, Enable to Output, and Enable Pulse Width nDx VM ts(H) nE VM ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ Waveform 2. Propagation Delay for Data to Outputs VM VM VM ts(L) th(H) VM th(L) VM Waveform 3. Data Setup and Hold Times nOE VM tPZH nQx nOE VM tPHZ VM VM VM tPZL VOH –0.3V nQx tPLZ VM 0V Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. August 23, 1993 VOL +0.3V 0V 6 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal transparent latch (3-State) MB2373 TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN VOUT PULSE GENERATOR tW 90% VM NEGATIVE PULSE 10% 0V tTHL (tF) CL tTLH (tR) tTLH (tR) RL tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. MB RT = Termination resistance should be equal to ZOUT of pulse generators. August 23, 1993 AMP (V) VM 10% RL D.U.T RT 90% 7 Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal transparent latch (3-State) MB2373 tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nDx to nQx 6 Adjustment of tPLH for Load Capacitance and # of Outputs Switching nDx to nQx 4 5 3 MAX 16 switching 8 switching 1 switching 2 Offset in ns ns 4 4.5VCC 5.5VCC 3 1 2 0 MIN 1 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 150 Adjustment of tPHL for Load Capacitance and # of Outputs Switching nDx to nQx 4 5 3 16 switching 8 switching 1 switching MAX 2 Offset in ns 4 ns 200 pF tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nDx to nQx 6 100 4.5VCC 3 5.5VCC 1 2 0 MIN 1 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 150 Adjustment of tPLH for Load Capacitance and # of Outputs Switching nE to nQx 4 6 3 16 switching 8 switching MAX 2 Offset in ns 5 ns 200 pF tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nE to nQx 7 100 4.5VCC 5.5VCC 4 3 1 switching 1 0 MIN 2 –1 1 –55 –2 –35 –15 5 25 45 65 85 105 125 0 °C August 23, 1993 50 100 pF 8 150 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal transparent latch (3-State) MB2373 tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nE to nQx 7 Adjustment of tPHL for Load Capacitance and # of Outputs Switching nE to nQx 4 6 3 MAX 4 4.5VCC 5.5VCC 3 MIN 2 16 switching 8 switching 1 switching 2 Offset in ns ns 5 1 0 –1 1 –2 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 150 Adjustment of tPZH for Load Capacitance and # of Outputs Switching nOE to nQx 5 4 5 MAX 16 switching 8 switching 1 switching 3 Offset in ns 4 4.5VCC ns 200 pF tPZH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx 6 100 3 5.5VCC 2 2 1 0 MIN 1 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 0 125 50 °C 6 4 MAX Offset in ns 5 ns 4.5VCC 4 5.5VCC 3 MIN 2 200 Adjustment of tPZL for Load Capacitance and # of Outputs Switching nOE to nQx 3 16 switching 8 switching 2 1 switching 1 0 –1 1 –55 150 pF tPZL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx 7 100 –2 –35 –15 5 25 45 65 85 105 125 0 °C August 23, 1993 50 100 pF 9 150 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal transparent latch (3-State) MB2373 tPHZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx 7 Adjustment of tPHZ for Load Capacitance and # of Outputs Switching nOE to nQx 5 6 4 MAX 4 3 Offset in ns 5 ns 4.5VCC 5.5VCC 3 16 switching 8 switching 1 switching 2 2 1 0 MIN 1 –1 0 –55 –2 –35 –15 5 25 45 65 85 105 125 0 50 °C 150 200 pF tPLZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx 6 100 Adjustment of tPLZ for Load Capacitance and # of Outputs Switching nOE to nQx 6 5 5 MAX Offset in ns 4 ns 4.5VCC 5.5VCC 3 3 2 1 0 MIN 2 16 switching 8 switching 1 switching 4 –1 1 –55 –2 –35 –15 5 25 45 65 85 105 125 0 50 °C 150 Adjustment of tTLH for Load Capacitance and # of Outputs Switching 9 7 16 switching 8 switching 1 switching 4 Offset in ns 5 ns 200 pF tTLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching 5 100 4.5VCC 3 5.5VCC 3 1 2 –1 1 –55 –3 –35 –15 5 25 45 65 85 105 0 125 °C August 23, 1993 50 100 pF 10 150 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal transparent latch (3-State) MB2373 tTHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching 4 Adjustment of tTHL for Load Capacitance and # of Outputs Switching 4 3 16 switching 8 switching 1 switching 3 Offset in ns ns 2 4.5VCC 5.5VCC 2 1 0 1 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 150 200 pF VOHV and VOLP vs Load Capacitance VCC = 5V, VIN = 0 to 3V 4.0 100 VOHP and VOLV vs Load Capacitance VCC = 5V, VIN = 0 to 3V 5 3.5 125°C 25°C –55°C 3.0 4 125°C 25°C –55°C 3 2.0 Volts Volts 2.5 1.5 2 1 1.0 125°C 25°C –55°C 0 0.5 125°C 25°C –55°C 0.0 –1 –0.5 –2 0 50 100 150 200 0 pF August 23, 1993 50 100 pF 11 150 200