Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) FEATURES • Two 8-bit octal transceivers with D-type MB2543 • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per latch • Live insertation/extraction permitted • Power-up 3-State • Power-up reset • Multiple VCC and GND pins minimize power dissipation with high speed and high output drive. The MB2543 dual octal registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (nLEAB, nLEBA) and Output Enable (nOEAB, nOEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64mA. Jedec JC40.2 Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model switching noise DESCRIPTION • Back-to-back registers for storage • Separate controls for data flow in each The MB2543 high-performance BiCMOS device combines low static and dynamic direction QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 3.3 ns tPLH tPHL Propagation delay nAx to nBx CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 4 pF CI/O I/O capacitance VO = 0V or VCC; 3-State 7 pF ICCZ Total supply current Outputs disabled; VCC = 5.5V 120 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 52-pin plastic Quad Flat Pack –40°C to +85°C MB2543BB 1418B PIN CONFIGURATION LOGIC SYMBOL 52 51 1A2 1A3 50 49 48 47 46 45 44 43 42 Vcc 1B1 1B0 GND 1EBA 1LEBA 1OEBA 1OEAB 1LEAB 1EAB 1A0 1A1 Vcc 50 39 1B2 38 1B3 2 1A4 3 37 1B4 GND 4 36 1B5 1A5 5 35 1B6 1A6 6 MB2543 52-pin PQFP 1 2 3 5 6 7 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 41 40 1 51 49 1EAB 44 1EBA 1OEAB 47 48 1LEAB 1OEBA 46 45 1LEBA 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 34 1B7 42 41 39 38 37 36 35 34 8 9 10 11 12 13 15 16 33 2B0 1A7 7 2A0 8 32 2B1 2A1 9 31 2B2 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A2 10 30 GND 2A3 11 29 2B3 18 2EAB 2A4 12 28 2B4 23 2EBA 2OEAB 20 2A5 13 27 2B5 19 2LEAB 2OEBA 21 22 2LEBA 26 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 Vcc 2B6 2B7 2EBA 2LEBA 21 22 23 24 25 2OEBA 2OEAB 2LEAB 2EAB 17 18 19 20 GND 2A7 Vcc 2A6 14 15 16 33 August 23, 1993 1 32 31 29 28 27 25 24 853–1656 10584 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) MB2543 LOGIC DIAGRAM DETAIL A D nB0 Q LE nA0 Q D LE nA1 nB1 nA2 nB2 nA3 nB3 DETAIL A X 7 nA4 nB4 nA5 nB5 nA6 nB6 nA7 nB7 nOEBA nOEAB nEBA nEAB nLEBA nLEAB LOGIC SYMBOL (IEEE/IEC) 47 49 48 46 44 45 50 August 23, 1993 20 & & 18 EN1(AB) 19 21 & & 23 EN2(BA) 22 & & EN1(AB) & & EN2(BA) 42 8 51 41 9 32 1 39 10 31 2 38 11 29 3 37 12 28 5 36 13 27 6 35 15 25 7 34 16 24 ∇1 2∇ 2 ∇1 2∇ 33 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) A subsequent Low-to-High transition of the nLEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and nOEAB both Low, the 3-State B output FUNCTIONAL DESCRIPTION The MB2543 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B Enable (nEAB) input and the A-to-B Latch Enable (nLEAB) input are Low the A-to-B path is transparent. MB2543 buffers are active and display the data present at the outputs of the A latches. Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs. PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 50, 51, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16 1A0 – 1A7, 2A0 – 2A7 Data inputs/outputs 42, 41, 39, 38, 37, 36, 35, 34, 33, 32, 31, 29, 28, 27, 25, 24 1B0 – 1B7, 2B0 – 2B7 Data inputs/outputs 47, 46, 20, 21 1OEAB, 1OEBA, 2OEAB, 2OEBA 49, 44, 18, 23 1EAB, 1EBA, 2EAB, 2EBA 48, 45, 19, 22 1LEAB, 1LEBA, 2LEAB, 2LEBA 4, 17, 30, 43 GND Ground (0V) 14, 26, 40, 52 VCC Positive supply voltage A to B / B to A Output Enable inputs (active-Low) A to B / B to A Enable inputs (active-Low) A to B / B to A Latch Enable inputs (active-Low) FUNCTION TABLE INPUTS H = h = L = l = X = ↑ = NC= Z = OUTPUTS STATUS nOEXX nEXX nLEXX nAx or nBx nBx or nAx H X X X Z Disabled X H X X Z Disabled L L ↑ ↑ L L h l Z Z Disabled + Latch L L L L ↑ ↑ h l H L Latch + Display L L L L L L H L H L Transparent L L H X NC Hold High voltage level High voltage level one set-up time prior to the Low-to-High transition of nLEXX or nEXX (XX = AB or BA) Low voltage level Low voltage level one set-up time prior to the Low-to-High transition of nLEXX or nEXX (XX = AB or BA) Don’t care Low-to-High transition of nLEXX or nEXX (XX = AB or BA) No change High impedance or “off” state August 23, 1993 3 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) MB2543 ABSOLUTE MAXIMUM RATINGS1 , 2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1 . Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 . The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3 . The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 10 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range August 23, 1993 2.0 4 V Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) MB2543 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA TYP MAX –0.9 –1.2 MIN UNIT MAX –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA II Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC; VOE = Don’t care ±5.0 ±50 ±50 µA IIH + IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IIL + IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA –100 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 120 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 38 60 60 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 120 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA IOFF IPU/PD ICEX IO Output current1 ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 5.5V; VO = 2.5V –50 –50 NOTES: 1 . Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2 . This is the increase in supply current for each input at 3.4V. 3 . For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4 . This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a transition time of up to 100µsec is permitted. August 23, 1993 5 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) MB2543 AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM UNIT MIN TYP MAX MIN MAX 2 1.5 1.6 3.2 3.3 4.6 4.6 1.5 1.6 5.2 5.2 ns tPLH tPHL Propagation delay nAx to nBx, nBx to nAx tPLH tPHL Propagation delay LEBA to nAx, LEAB to nBx 1, 2 1.9 2.1 3.9 4.1 5.3 5.5 1.9 2.1 6.1 6.2 ns tPZH tPZL Output enable time OEBA to nAx, OEAB to nBx 4 5 1.6 2.3 3.6 4.5 5.0 5.9 1.6 2.3 5.8 6.6 ns tPHZ tPLZ Output disable time OEBA to nAx, OEAB to nBx 4 5 1.0 1.4 3.6 3.2 5.0 4.6 1.0 1.4 5.7 5.2 ns tPZH tPZL Output enable time EBA to nAx, EAB to nBx 4 5 1.6 2.3 3.6 4.5 5.0 5.9 1.6 2.3 5.8 6.6 ns tPHZ tPLZ Output disable time EBA to nAx, EAB to nBx 4 5 1.0 1.4 3.6 3.2 5.0 4.6 1.0 1.4 5.7 5.2 ns AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER +25oC Tamb = VCC = +5.0V WAVEFORM Tamb = -40 to +85oC VCC = +5.0V ±0.5V MIN TYP MIN UNIT ts(H) ts(L) Setup time nAx to LEAB, nBx to LEBA 3 1.0 0.5 0.4 –0.1 1.0 0.5 ns th(H) th(L) Hold time nAx to LEAB, nBx to LEBA 3 1.0 0.5 0.2 –0.3 1.0 0.5 ns ts(H) ts(L) Setup time nAx to EAB, nBx to EBA 3 1.0 0.5 0.2 –0.3 1.0 0.5 ns th(H) th(L) Hold time nAx to EAB, nBx to EBA 3 1.0 0.5 0.3 –0.2 1.0 0.5 ns tw(L) Latch enable pulse width, Low 3 4.0 3.1 4.0 ns August 23, 1993 6 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) MB2543 AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V VIN VM tPHL VOUT VIN VM VM tPLH VM tPLH ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ VM ts(H) nLEAB, nLEBA, nEAB, nEBA tPHL VOUT VM Waveform 1. Propagation Delay For Inverting Output nAx, nBx VM VM VM ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Waveform 2. Propagation Delay For Non-Inverting Output VM VM th(H) VM VM ts(L) tw(L) th(L) VM Waveform 3. Data Setup and Hold Times and Latch Enable Pulse Width nOEAB, nOEBA, nEAB, nEBA VM tPZH nAx, nBx nOEAB, nOEBA, nEAB, nEBA VM tPHZ VM VM VM tPZL VOH –0.3V nAx, nBx tPLZ VM 0V Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. August 23, 1993 7 VOL +0.3V 0V Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) MB2543 TEST CIRCUIT AND WAVEFORMS VCC 7.0V VOUT VIN PULSE GENERATOR tW 90% VM NEGATIVE PULSE 10% 0V tTHL (tF) CL tTLH (tR) tTLH (tR) RL tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. MB RT = Termination resistance should be equal to ZOUT of pulse generators. August 23, 1993 AMP (V) VM 10% RL D.U.T RT 90% 8 Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nAx to nBx or nBx to nAx 7 MB2543 Adjustment of tPLH for Load Capacitance and # of Outputs Switching nAx to nBx or nBx to nAx 6 5 6 16 switching 4 MAX 5 8 switching 4.5VCC 5.5VCC 3 2 3 Offset in ns ns 4 1 switching 2 1 MIN 0 1 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 150 Adjustment of tPHL for Load Capacitance and # of Outputs Switching nAx to nBx or nBx to nAx 5 6 4 MAX 5 Offset in ns 4.5VCC 4 ns 5.5VCC 3 2 3 16 switching 8 switching 2 1 switching 1 0 MIN 1 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 7 100 150 tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nLEBA to nAx or nLEAB to nBx Adjustment of tPLH for Load Capacitance and # of Outputs Switching nLEBA to nAx or nLEAB to nBx 6 5 MAX 16 switching 4 Offset in ns 5 4.5VCC 4 5.5VCC 3 MIN 8 switching 3 1 switching 2 1 0 2 –1 1 –55 200 pF 6 ns 200 pF tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nAx to nBx or nBx to nAx 7 100 –2 –35 –15 5 25 45 65 85 105 125 0 °C August 23, 1993 50 100 pF 9 150 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nLEBA to nAx or nLEAB to nBx 8 MB2543 Adjustment of tPHL for Load Capacitance and # of Outputs Switching nLEBA to nAx or nLEAB to nBx 5 7 4 MAX 5 4.5VCC ns 16 switching 8 switching 3 Offset in ns 6 4 5.5VCC 1 switching 2 1 3 0 MIN 2 –1 1 –2 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 150 200 pF tPZH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOEBA to nAx or nOEAB to nBx 7 100 Adjustment of tPZH for Load Capacitance and # of Outputs Switching nOEBA to nAx or nOEAB to nBx 5 16 switching 8 switching 4 6 MAX 3 1 switching Offset in ns ns 5 4.5VCC 4 5.5VCC 3 2 1 0 MIN 2 –1 1 –2 –55 –35 –15 5 25 45 65 85 105 0 125 50 °C 8 100 150 tPZL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOEBA to nAx or nOEAB to nBx Adjustment of tPZL for Load Capacitance and # of Outputs Switching nOEBA to nAx or nOEAB to nBx 5 7 4 16 switching 8 switching MAX 3 5 Offset in ns 6 ns 4.5VCC 4 5.5VCC 3 1 switching 2 1 0 MIN 2 –1 1 –55 200 pF –2 –35 –15 5 25 45 65 85 105 125 0 °C August 23, 1993 50 100 pF 10 150 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) tPHZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOEBA to nAx or nOEAB to nBx 7 6 Adjustment of tPHZ for Load Capacitance and # of Outputs Switching nOEBA to nAx or nOEAB to nBx MAX Offset in ns 5 ns 4 4.5VCC 5.5VCC 3 2 1 MIN 0 –55 –35 –15 5 25 45 65 85 105 MB2543 11 10 9 8 7 6 5 4 3 2 1 0 –1 –2 –3 –4 125 16 switching 8 switching 1 switching 0 50 °C 150 200 pF tPLZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOEBA to nAx or nOEAB to nBx 7 100 Adjustment of tPLZ for Load Capacitance and # of Outputs Switching nOEBA to nAx or nOEAB to nBx 7 6 6 16 switching 8 switching 1 switching 5 MAX 5 Offset in ns 4 4 2 MIN ns 3 4.5VCC 5.5VCC 3 2 1 0 1 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 150 200 pF tPZH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nEBA to nAx or nEAB to nBx 7 100 6 Adjustment of tPZH for Load Capacitance and # of Outputs Switching nEBA to nAx or nEAB to nBx 5 4 MAX 5 16 switching 8 switching 3 3 5.5VCC 2 MIN ns 4.5VCC Offset in ns 1 switching 4 1 0 1 –1 0 –55 2 –2 –35 –15 5 25 45 65 85 105 125 0 °C August 23, 1993 50 100 pF 11 150 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) tPZL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nEBA to nAx or nEAB to nBx 8 MB2543 Adjustment of tPZL for Load Capacitance and # of Outputs Switching nEBA to nAx or nEAB to nBx 5 7 4 MAX 6 16 switching 8 switching 3 ns 4.5VCC 4 5.5VCC 3 1 switching Offset in ns 5 2 1 0 MIN 2 –1 1 –2 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 150 200 pF tPHZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nEBA to nAx or nEAB to nBx 7 100 Adjustment of tPHZ for Load Capacitance and # of Outputs Switching nEBA to nAx or nEAB to nBx 12 16 switching 8 switching 1 switching 10 6 MAX 8 5 4.5VCC 3 6 Offset in ns ns 4 5.5VCC 4 2 2 0 1 MIN –2 0 –4 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 150 200 pF tPLZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nEBA to nAx or nEAB to nBx 7 100 7 Adjustment of tPLZ for Load Capacitance and # of Outputs Switching nEBA to nAx or nEAB to nBx 6 6 MAX 5 16 switching 8 switching 1 switching 5 Offset in ns 4 4 2 MIN ns 3 4.5VCC 5.5VCC 3 2 1 0 1 –1 0 –55 –2 –35 –15 5 25 45 65 85 105 125 0 °C August 23, 1993 50 100 pF 12 150 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual octal latched transceivers with dual enable (3-State) tTLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching 4 MB2543 Adjustment of tTLH for Load Capacitance/# of Outputs 11 16 switching 8 switching 1 switching 9 3 Offset in ns ns 7 4.5VCC 5.5VCC 2 5 3 1 1 –1 0 –3 –55 –35 –15 5 25 45 65 85 105 0 125 50 °C 150 200 pF tTHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching 4 100 Adjustment of tTHL for Load Capacitance and # of Outputs Switching 6 5 16 switching 8 switching 1 switching 4 4.5VCC 2 3 Offset in ns ns 3 5.5VCC 2 1 1 0 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 200 VOHP and VOLV vs Load Capacitance VCC = 5V, VIN = 0 to 3V 6 3.5 5 125°C 25°C –55°C 3.0 125°C 25°C –55°C 4 3 Volts 2.5 Volts 150 pF VOHV and VOLP vs Load Capacitance VCC = 5V, VIN = 0 to 3V 4.0 100 2.0 1.5 2 1 0 1.0 0.5 125°C 25°C –55°C –1 125°C 25°C –55°C –2 0 –3 0 50 100 150 0 200 pF August 23, 1993 50 100 pF 13 150 200