INTEGRATED CIRCUITS PCA9501 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins Product data Supersedes data of 2002 Sep 27 Philips Semiconductors 2003 Sep 12 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 DESCRIPTION The PCA9501 is an 8-bit I/O expander with an on-board 2-kbit EEPROM. The I/O expandable eight quasi bidirectional data pins can be independently assigned as inputs or outputs to monitor board level status or activate indicator devices such as LEDs. The system master writes to the I/O configuration bits in the same way as for the PCF8574. The data for each Input or Output is kept in the corresponding Input or Output register. The system master can read all registers. FEATURES The EEPROM can be used to store error codes or board manufacturing data for read-back by application software for diagnostic purposes and are included in the I/O expander package. • 8 general purpose input/output expander/collector • Replacement for PCF8574 with integrated 2-kbit EEPROM • Internal 256 × 8 EEPROM • Self timed write cycle (5 ms typ) • 16 byte page write operation • I2C and SMBus interface logic • Internal power-on reset • Noise filter on SCL/SDA inputs • Active low interrupt output • 6 address pins allowing up to 64 devices on the I2C/SMBus • No glitch on power-up • Supports hot insertion • Power-up with all channels configured as inputs • Low standby current • Operating power supply voltage range of 2.5 V to 3.6 V • 5 V tolerant inputs/outputs • 0 to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, The PCA9501 Active-LOW open-drain interrupt output is activated when any input state differes from its corresponding input port register state. It is used to indicate to the system master that an input state has changed and the device needs to be interrogated. The PCA9501 has six address pins with internal pull-up resistors allowing up to 64 devices to share the common two wire I2C software protocol serial data bus. The fixed GPIO address starts with “1” and the fixed EEPROM I2C address starts with “0”, so the PCA9501 appears as two separate devices to the bus master. The PCA9501 supports hot insertion to facilitate usage in removable cards on backplane systems. 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA • Packages offered: SO20, TSSOP20, HVQFN20 ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER 20-pin plastic SO -40 to +85 °C PCA9501D PCA9501D SOT163-1 20-Pin Plastic TSSOP -40 to +85 °C PCA9501PW PCA9501 SOT360-1 20-Pin Plastic HVQFN -40 to +85 °C PCA9501BS 9501 SOT662-1 Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent. I2C is a trademark of Philips Semiconductors Corporation. 2003 Sep 12 2 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins 18 SCL 16 19 SDA A2 3 A0 VDD SDA SCL 17 A1 2 A1 18 20 VDD 19 A0 1 PIN CONFIGURATION - HVQFN 20 PIN CONFIGURATION - SO, TSSOP PCA9501 A2 1 15 WC 14 I/O7 3 13 I/O6 I/O2 6 15 I/O6 I/O2 4 12 I/O5 I/O3 7 14 I/O5 I/O3 13 I/O4 5 11 I/O4 INT 8 6 PCA9501 A5 9 12 A3 VSS 10 11 A4 INT A5 VSS A4 10 2 I/O1 9 I/O0 8 17 WC 16 I/O7 7 I/O0 4 I/O1 5 A3 TOP VIEW SW00903 SW02017 Figure 1. Pin configuration - SO, TSSOP Figure 2. Pin configuration - HVQFN PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION SO, TSSOP HVQFN 1, 2, 3, 9, 11, 12 19, 20, 1, 7, 9, 10 A0-5 4, 5, 6, 7 2, 3, 4, 5 I/O0-3 8 6 INT Active low interrupt output (open drain) Supply ground Address lines (internal pull-up) Quasi-bidirectional I/O pins 10 8 VSS 13, 14, 15, 16 11, 12, 13, 14 I/O4-7 Quasi-bidirectional I/O pins 17 15 WC Active low write control pin 18 16 SCL I2C serial clock 19 17 SDA I2C serial data 20 18 VDD Supply voltage 2003 Sep 12 3 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 BLOCK DIAGRAM PCA9501 300 k Ω A0 A1 I/O0 A2 I/O1 I/O2 A3 8-BIT I2C/SMBus CONTROL A4 A5 INPUT/ OUTPUT PORTS WRITE pulse SCL SDA INPUT FILTER I/O3 I/O4 I/O5 READ pulse I/O6 I/O7 VCC VDD VSS WC LP FILTER POWER-ON RESET INT EEPROM 256 x 8 SW01077 Figure 3. Block diagram 2003 Sep 12 4 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 FUNCTIONAL DESCRIPTION VDD WRITE PULSE 100 µA DATA FROM SHIFT REGISTER D Q FF I/O0 TO I/O7 CI S POWER-ON RESET VSS D Q FF CI READ PULSE S TO INTERRUPT LOGIC DATA TO SHIFT REGISTER SW00788 Figure 4. Simplified schematic diagram of each I/O DEVICE ADDRESSING Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9501 is shown in Figure 5. Internal pullup resistors are incorporated on the hardware selectable address pins. SLAVE ADDRESS 0 FIXED (a) I/O EXPANDER A5 A4 A3 A2 SLAVE ADDRESS A1 A0 R/W 1 HARDWARE PROGRAMMABLE (b) MEMORY FIXED A5 A4 A3 A2 A1 A0 R/W HARDWARE PROGRAMMABLE a. b. SW02006 Figure 5. PCA9501 slave addresses The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write operation. CONTROL REGISTER The PCA9501 contains a single 8-bit register called the Control Register, which can be written and read via the I2C bus. This register is sent after a successful acknowledgment of the slave address. It contains the I/O operation information. 2003 Sep 12 5 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 I/O OPERATIONS (see also Figure 4) Each of the PCA9501’s eight I/Os can be independently used as an input or output. Output data is transmitted to the port by the I/O WRITE mode (see Figure 6). Input I/O data is transferred from the port to the microcontroller by the READ mode (See Figure 7). SCL 1 2 3 4 5 6 7 8 SLAVE ADDRESS (I/O EXPANDER) SDA S 0 A5 A4 A3 A2 A1 A0 0 A R/W START CONDITION DATA TO PORT DATA TO PORT DATA 1 A ACKNOWLEDGE FROM SLAVE DATA 2 A ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE WRITE TO PORT DATA OUT FROM PORT DATA 1 VALID t pv DATA 2 VALID t pv SW00649 Figure 6. I/O WRITE mode (output) SLAVE ADDRESS (I/O EXPANDER) SDA S 0 A5 A4 A3 A2 START CONDITION A1 A0 DATA FROM PORT 1 R/W A DATA FROM PORT DATA 1 A DATA 4 ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM SLAVE 1 P STOP CONDITION READ FROM PORT DATA INTO PORT DATA 1 DATA 2 DATA 3 t ph DATA 4 t ps INT t iv t ir SW00650 Figure 7. I/O READ mode (input) 2003 Sep 12 6 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 Quasi-bidirectional I/Os (see Figure 8) A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. SLAVE ADDRESS (I/O EXPANDER) SDA S 0 A5 A4 A3 A2 A1 A0 SCL 1 2 0 R/W START CONDITION 3 4 5 6 7 DATA TO PORT DATA TO PORT 1 A ACKNOWLEDGE FROM SLAVE A I/O3 ACKNOWLEDGE FROM SLAVE 0 A P I/O3 8 I/O3 OUTPUT VOLTAGE I/O3 PULL-UP OUTPUT CURRENT IOHt IOH SW00904 Figure 8. Transient pull-up current IOHt while I/O3 changes from LOW-to-HIGH and back to LOW 2003 Sep 12 7 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 Resetting occurs as follows: Interrupt (see Figs 9 and 12) • In the READ mode at the acknowledge bit after the rising edge of The PCA9501 provides an open drain output (INT) which can be fed to a corresponding input of the microcontroller. This gives these chips a type of master function which can initiate an action elsewhere in the system. the SCL signal • In the WRITE mode at the acknowledge bit after the HIGH-to-LOW transition of the SCL signal An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv the signal INT is valid. • Returning of the port data to its original setting. • Interrupts which occur during the acknowledge clock pulse may Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from or written to the port which has generated the interrupt. be lost (or very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting will be detected and, after the next rising clock edge, will be transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit. PCA9501 (2) PCA9501 (1) VDD INT PCA9501 (16) INT INT MICROCONTROLLER INT SW00790 Figure 9. Application of multiple PCA9501s with interrupt SLAVE ADDRESS (I/O EXPANDER) SDA S 0 A5 A4 A3 A2 A1 DATA FROM PORT A0 R/W START CONDITION SCL 1 1 2 3 4 5 6 7 A 1 ACKNOWLEDGE FROM SLAVE I/O5 1 P STOP CONDITION 8 DATA INTO I/O5 INT t iv t ir Figure 10. Interrupt generated by a change of input to I/O5 2003 Sep 12 8 SW00791 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins the word address and the eight bits after the word address as the data. The PCA9501 will issue an acknowledge after the receipt of both the word address and the data. To terminate the data transfer the master issues the stop condition, initiating the internal write cycle to the non-volatile memory. Only write and read operations to the quasi-bidirectional I/Os are allowed during the internal write cycle. MEMORY OPERATIONS Write operations Write operations require an additional address field to indicate the memory address location to be written. The address field is eight bits long providing access to any one of the 256 words of memory. There are two types of write operations, byte write and page write. Page Write (see Figure 12) A page write is initiated in the same way as the byte write, if after sending the first word of data, the stop condition is not received the PCA9501 considers subsequent words as data. After each data word the PCA9501 responds with an acknowledge and the four least significant bits of the memory address field are incremented. Should the master not send a stop condition after 16 data words the address counter will return to its initial value and overwrite the data previously written. After the receipt of the stop condition the inputs will behave as with the byte write during the internal write cycle. Write operation is possible when WC control pin put at a low logic level (0). When this control signal is set at 1, write operation is not possible and data in the memory is protected. Byte Write and Page Write explained below assume that Write Control pin (WC) is set to 0. Byte Write (see Figure 11) To perform a byte write the start condition is followed by the memory slave address and the R/W bit set to 0. The PCA9501 will respond with an acknowledge and then consider the next eight bits sent as SLAVE ADDRESS (MEMORY) SDA S 1 DATA WORD ADDRESS A5 A4 A3 A2 A1 A0 0 START CONDITION PCA9501 A A R/W ACKNOWLEDGE FROM SLAVE A ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE P STOP CONDITION. WRITE TO THE MEMORY IS PERFORMED SW00651 Figure 11. Byte write SLAVE ADDRESS (MEMORY) SDA S 1 A5 A4 A3 A2 A1 A0 0 START CONDITION DATA TO MEMORY WORD ADDRESS A R/W ACKNOWLEDGE FROM SLAVE DATA n A ACKNOWLEDGE FROM SLAVE DATA TO MEMORY A ACKNOWLEDGE FROM SLAVE DATA n + 3 2003 Sep 12 9 P STOP CONDITION. WRITE TO THE MEMORY IS PERFORMED SW00652 Figure 12. Page Write A Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins The master must perform a byte write to the address location to be read, but instead of transmitting the data after receiving the acknowledge from the PCA9501 the master reissues the start condition and memory slave address with the R/W bit set to one. The PCA9501 will then transmit an acknowledge and use the next eight clock cycles to transmit the data contained in the addressed location. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge. Read operations PCA9501 read operations are initiated in an identical manner to write operations with the exception that the memory slave address’ R/W bit is set to a one. There are three types of read operations; current address, random and sequential. Current Address Read (see Figure 13) The PCA9501 contains an internal address counter that increments after each read or write access, as a result if the last word accessed was at address n then the address counter contains the address n+1. Sequential Read (see Figure 15) The PCA9501 sequential read is an extension of either the current address read or random read. If the master doesn’t issue a stop condition after it has received the eighth data bit, but instead issues an acknowledge, the PCA9501 will increment the address counter and use the next eight cycles to transmit the data from that location. The master can continue this process to read the contents of the entire memory. Upon reaching address 255 the counter will return to address 0 and continue transmitting data until a stop condition is received. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge. When the PCA9501 receives its memory slave address with the R/W bit set to one it issues an acknowledge and uses the next eight clocks to transmit the data contained at the address stored in the address counter. The master ceases the transmission by issuing the stop condition after the eighth bit. There is no ninth clock cycle for the acknowledge. Random Read (see Figure 14) The PCA9501’s random read mode allows the address to be read from to be specified by the master. This is done by performing a dummy write to set the address counter to the location to be read. SLAVE ADDRESS (MEMORY) SDA S 1 A5 A4 A3 A2 DATA FROM MEMORY A1 A0 START CONDITION PCA9501 1 R/W A P ACKNOWLEDGE FROM SLAVE STOP CONDITION SW00653 Figure 13. Current Address Read SLAVE ADDRESS (MEMORY) SDA S 1 A5 A4 A3 A2 A1 A0 0 START CONDITION SLAVE ADDRESS (MEMORY) WORD ADDRESS A A S 1 A5 A4 A3 A2 A1 A0 ACKNOWLEDGE FROM SLAVE R/W ACKNOWLEDGE FROM SLAVE DATA FROM MEMORY 1 R/W P A ACKNOWLEDGE FROM SLAVE START CONDITION STOP CONDITION SW00654 Figure 14. Random Read SLAVE ADDRESS (MEMORY) SDA S 1 A5 A4 A3 A2 A1 A0 START CONDITION R/W DATA FROM MEMORY 1 A DATA n ACKNOWLEDGE FROM SLAVE DATA FROM MEMORY DATA FROM MEMORY A DATA n+1 ACKNOWLEDGE FROM MASTER A DATA n+X STOP CONDITION ACKNOWLEDGE FROM MASTER SW00655 Figure 15. Sequential Read 2003 Sep 12 10 P Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 17). Bit transfer One data bit is transferred during each clock phase. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (See Figure 16). System configuration A device generating a message is a “transmitter”, a device receiving is the “receiver”. The device that controls the message is the “master” and the devices which are controlled by the master are the “slaves” (see Figure 18). SDA SCL DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED SW00542 Figure 16. Bit transfer SDA SDA SCL SCL S P START CONDITION STOP CONDITION SW00543 Figure 17. Definition of start and stop conditions SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SW00544 Figure 18. System configuration 2003 Sep 12 11 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. Acknowledge (see Figure 19) The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked DATA OUTPUT BY TRANSMITTER NOT ACKNOWLEDGE DATA OUTPUT BY RECEIVER ACKNOWLEDGE SCL FROM MASTER 1 2 8 9 S CLOCK PULSE FOR ACKNOWLEDGEMENT START CONDITION Figure 19. Acknowledgment on the I2C-bus 2003 Sep 12 12 SW00545 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 TYPICAL APPLICATION Applications • Board version tracking and configuration • Board health monitoring and status reporting • Multi-card systems in Telecom, Networking, and Base Station • General-purpose integrated I/O with memory • Replacement for PCF8574 with integrated 2-kbit EEPROM • Bus master sees GPIO and EEPROM as two separate devices • Six hardware address pins allow up to 64 PCA9501s to be located Infrastructure Equipment • Field recall and troubleshooting functions for installed boards in the same I2C/SMBus UP TO 64 CARDS I2C ASIC CPU OR µC I2C BACKPLANE I2C I2C CONFIGURATION CONTROL I2C PCA9501 CONTROL INPUTS I2C ALARM GPIO LEDs EEPROM MONITORING AND CONTROL CARD ID, SUBROUTINES, CONFIGURATION DATA, OR REVISION HISTORY SW02007 Figure 20. Typical application manufacturer identification, configuration option data… Alternately, these devices can be used as convenient interface for board configuration, thereby utilizing the I2C/SMBus as an intra-system communication bus. A central processor/controller typically located on the system main board can use the 400 kHz I2C/SMBus to poll the PCA9501 devices located on the system cards for status or version control type of information. The PCA9501 may be programmed at manufacturing to store information regarding board build, firmware version, 2003 Sep 12 13 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 TYPICAL APPLICATION VDD 2 kΩ VDD 1.6 kΩ 1.6 kΩ 1.1 kΩ 2 kΩ (optional) VDD MASTER CONTROLLER SCL SCL SDA SDA INT INT SUBSYSTEM 1 (e.g. temp sensor) I/00 INT I/01 I/02 RESET GND I/03 PCA9501 SUBSYSTEM 2 (e.g. counter) I/04 A5 I/05 A4 A Controlled Switch (e.g. CBT device) I/06 ENABLE A3 I/07 A2 B A1 A0 VSS ALARM SUBSYSTEM 3 (e.g. alarm system) NOTE: GPIO device address configured as 0110000 for this example EEPROM device address configured as 1110000 for this example I/00, I/02, I/03, configured as outputs I/01, I/04, I/05, configured as inputs I/006, I/07, are not used and have to be configured as outputs VDD SW01078 Figure 21. Typical application 2003 Sep 12 14 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. SYMBOL VCC PARAMETER Supply Voltage VI Input Voltage II DC Input Current MIN MAX UNIT -0.5 4.0 V VSS - 0.5 5.5 V -20 20 mA IO DC Output Current -25 25 mA IDD Supply Current -100 100 mA ISS Supply Current -100 100 mA Ptot Total Power Dissipation — 400 mW PO Total Power Dissipation per Output — 100 mW TSTG Storage Temperature -65 +150 _C TAMB Operating Temperature -40 +85 _C MIN TYP MAX UNIT DC ELECTRICAL CHARACTERISTICS Tamb = -40 _C to +85 _C unless otherwise specified; VCC = 3.3 V SYMBOL PARAMETER Supply VDD Supply Voltage 2.5 3.3 3.6 V IDDQ Standby Current; A0 thru A5, WC = HIGH — — 60 µA IDD1 Supply Current Read — — 1 mA IDD2 Supply Current Write — — 2 mA VPOR Power on Reset Voltage — — 2.4 V V Input SCL; input, output SDA VIL Input LOW voltage -0.5 — 0.3 VDD VIH Input HIGH voltage 0.7 VDD — 5.5 V IOL Output LOW current @ VOL = 0.4 V 3 — — mA IL Input leakage current @ VI = VDD or VSS -1 — 1 µA CI Input capacitance @ VI = VSS — — 7 pF I/O Expander Port VIL Input LOW voltage -0.5 — 0.3 VDD V VIH Input HIGH voltage 0.7 VDD — 5.5 V -400 — 400 µA IOL Output LOW current @ VOL = 1 V 10 25 — mA IOH Output HIGH current @ VOH = Vss 30 100 300 µA IOHt Transient pull-up current — 2 — mA CI Input Capacitance — — 10 pF CO Output Capacitance — — 10 pF V IIHL(max) Input current through protection diodes Address Inputs A0 thru A5, WC input VIL Input LOW voltage -0.5 — 0.3 VDD VIH Input HIGH voltage 0.7 VDD — 5.5 V Input leakage current @ VI = VDD -1 — 1 µA Input leakage (pull-up) current @ VI = VSS 10 25 100 µA IL Interrupt output INT IOL Low level output current; VOL = 0.4 V 1.6 — — mA IL Leakage current @ VI = VDD or VSS -1 — +1 µA 2003 Sep 12 15 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 NON-VOLATILE STORAGE SPECIFICATIONS PARAMETER SPECIFICATION Memory cell data retention 10 years minimum Number of memory cell write cycles 100,000 cycles minimum I2C-BUS TIMING CHARACTERISTICS SYMBOL PARAMETER MIN. TYP. MAX. UNIT kHz I2C-bus timing (see Figure 22; Note 1) fSCL SCL clock frequency — — 400 tSW tolerable spike width on bus — — 50 ns tBUF bus free time 1.3 — — µs tSU;STA START condition set-up time 0.6 — — µs tHD;STA START condition hold time 0.6 — — µs tr SCL and SDA rise time — — 0.3 µs tf SCL and SDA fall time — — 0.3 µs 250 — — ns tSU;DAT data set-up time tHD;DAT data hold time 0 — — ns tVD;DAT SCL LOW to data out valid — — 1.0 µs tSU;STO STOP condition set-up time 0.6 — — µs NOTE: 1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD. PORT TIMING CHARACTERISTICS SYMBOL PARAMETER MIN TYP MAX UNIT tpv Output data valid; CL ≤ 100 pF — — 4 µs tps Input data setup time; CL ≤ 100 pF 0 — — µs tph Input data hold time; CL ≤ 100 pF 4 — — µs tiv Interrupt input data valid time; CL ≤ 100 pF — — 4 µs tir Interrupt reset time; CL ≤ 100 pF — — 4 µs 2003 Sep 12 16 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins handbook, full pagewidth PROTOCOL t START CONDITION (S) BIT 7 MSB (A7) PCA9501 BIT 6 (A6) SU;STA BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1 / f SCL SCL t t t r BUF f SDA t t HD;STA t SU;DAT t HD;DAT VD;DAT MBD820 t SU;STO SW00561 Figure 22. POWER-UP TIMING SYMBOL 1 tPUW1 tPUR PARAMETER MAX. UNIT Power-up to Read Operation 1 ms Power-up to Write Operation 5 ms NOTE: 1. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are guaranteed by design. WRITE CYCLE LIMITS SYMBOL tWR1 PARAMETER Write Cycle Time MIN. TYP. (5) MAX. UNIT — 5 10 ms NOTE: 1. tWR is the maximum time that the device requires to perform the internal write operation. Write Cycle Timing SCL SDA 8th Bit ACK Word n MEMORY ADDRESS tWR Stop Condition Start Condition SW00560 Figure 23. 2003 Sep 12 17 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 SOLDERING seconds depending on heating method. Typical reflow temperatures range from 215 to 250°C. Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45°C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our IC Package Databook (order code 9398 652 90011). If wave soldering cannot be avoided, the following conditions must be observed: DIP • A double-wave (a turbulent wave with high upward pressure Soldering by dipping or by wave The maximum permissible temperature of the solder is 260°C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300°C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400°C, contact may be up to 5 seconds. Maximum permissible solder temperature is 260°C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150°C within 6 seconds. Typical dwell time is 4 seconds at 250°C. SO and SSOP A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Reflow soldering Reflow soldering techniques are suitable for all SO and SSOP packages. Repairing soldered joints Fix the component by first soldering two diagonally opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320°C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 2003 Sep 12 18 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 2003 Sep 12 19 PCA9501 SOT360-1 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins HVQFN20: plastic, heatsink very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm 2003 Sep 12 20 PCA9501 SOT662-1 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins REVISION HISTORY Rev Date PCA9501 Description _2 20030912 Product data (9397 750 12058); ECN 853-2370 30128 dated 18 July 2003. Supersedes data of 2002 September 27 (9397 750 10327). Modifications: • Addition of HVQFN package type. _1 2002 Sep 27 Product data (9397 750 10327); initial version Engineering Change Notice: 853-2370 28875 (2002 Sep 09) 2003 Sep 12 21 Philips Semiconductors Product data 8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins PCA9501 Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Level Data sheet status[1] Product status[2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 09-03 For sales offices addresses send e-mail to: [email protected]. Document order number: Philips Semiconductors 2003 Sep 12 22 9397 750 12058