INTEGRATED CIRCUITS DATA SHEET PCF85116-3 2048 × 8-bit CMOS EEPROM with I2C-bus interface Product specification Supersedes data of 1997 Feb 24 File under Integrated Circuits, IC12 1997 Apr 02 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface CONTENTS 1 FEATURES 2 DESCRIPTION 2.1 Remark 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 DEVICE SELECTION 6 BLOCK DIAGRAM 7 PINNING 8 I2C-BUS PROTOCOL 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.5 8.5.1 Bus conditions Data transfer Device addressing Write operations Byte/word write Page Write Remark Read operations Remark 1997 Apr 02 2 PCF85116-3 9 LIMITING VALUES 10 CHARACTERISTICS 11 I2C-BUS CHARACTERISTICS 12 WRITE CYCLE LIMITS 13 PACKAGE OUTLINES 14 SOLDERING 14.1 14.2 14.2.1 14.2.2 14.3 14.3.1 14.3.2 14.3.3 Introduction DIP Soldering by dipping or by wave Repairing soldered joints SO Reflow soldering Wave soldering Repairing soldered joints 15 DEFINITIONS 16 LIFE SUPPORT APPLICATIONS 17 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface 1 2 FEATURES PCF85116-3 DESCRIPTION The PCF85116-3 is an 16 kbits (2048 × 8-bit) floating gate Electrically Erasable Programmable Read Only Memory (EEPROM). By using redundant EEPROM cells it is fault tolerant to single bit errors. In most cases multi bit errors are also covered. This feature dramatically increases reliability compared to conventional EEPROM memories. Power consumption is low due to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier. • Low power CMOS: – maximum operating current 1.0 mA – maximum standby current 10 µA (at 5.5 V), typical 4 µA • Non-volatile storage of 16 kbits organized as eight blocks of 256 × 8-bit each • Single supply with full operation down to 2.7 V • On-chip voltage multiplier As data bytes are received and transmitted via the serial I2C-bus, a package using eight pins is sufficient. Only one PCF85116-3 device is required to support all eight blocks of 256 × 8-bit each. • Serial input/output I2C-bus (100 kbits/s standard-mode and 400 kbits/s fast-mode) • Write operations: multi byte write mode up to 32 bytes • Write-protection input Timing of the E/W cycle is carried out internally, thus no external components are required. A write-protection input at pin 7 (WP) allows disabling of write-commands from the master by a hardware signal. When pin 7 is HIGH the data bytes received will not be acknowledged by the PCF85116-3 and the EEPROM contents are not changed. • Read operations: – sequential read – random read • Internal timer for writing (no external components) • Power-on-reset • High reliability by using redundant EEPROM cells 2.1 • Endurance: 1000000 Erase/Write (E/W) cycles at Tamb = 22 °C The PCF85116-3 is pin and address compatible to the PCx85xxC-2 family. The PCF85116-3 covers the whole address space of 16 kbits; address inputs are no longer needed. Therefore, pins 1 to 3 are not connected. The write-protection input is at pin 7. • 20 years non-volatile data retention time (minimum) • Pin and address compatible to the PCx85xxC-2 family (see also Section 2.1) Remark • 2 kV ESD protection (Human Body model). 3 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage IDDR supply current read fSCL = 400 kHz; VDD = 5.5 V IDDW supply current E/W fSCL = 400 kHz; VDD = 5.5 V − 1.0 mA Istb standby supply current VDD = 2.7 V − 6 µA VDD = 5.5 V − 10 µA 1997 Apr 02 3 2.7 5.5 V − 1.0 mA Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface 4 PCF85116-3 ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION PCF85116-3P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 PCF85116-3T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 5 DEVICE SELECTION Table 1 Device selection code SELECTION Bit Device DEVICE CODE CHIP ENABLE b6 b5 b4 b3 b2 b1 b0 1 0 1 0 MEM SEL MEM SEL MEM SEL R/W Note 1. The Most Significant Bit (MSB) ‘b7’ is sent first. 1997 Apr 02 R/W b7(1) 4 1997 Apr 02 SCL SDA n INPUT FILTER I2C-BUS CONTROL LOGIC 5 5 SHIFT REGISTER ROW DEC HV GENERATOR Fig.1 Block diagram. EEPROM ARRAY (8 × 256 × 8) PAGE REGISTER COLUMN DECODER ADDRESS COMPARATOR ADDRESS POINTER 6 OSCILLATOR DIVIDER SEQUENCER MBH922 2048 × 8-bit CMOS EEPROM with I2C-bus interface VSS 4 POWER-ON-RESET TEST MODE REGISTER 7 8 PCF85116-3 5 6 WP 6 VDD Philips Semiconductors Product specification PCF85116-3 BLOCK DIAGRAM Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface 7 PINNING SYMBOL PIN DESCRIPTION n.c. 1 not connected n.c. 2 not connected n.c. 3 not connected VSS 4 negative supply voltage SDA 5 serial data input/output (I2C-bus) SCL 6 serial clock input (I2C-bus) WP 7 write-protection input VDD 8 positive supply voltage 8 handbook, halfpage n.c. 2 8 VDD 7 WP n.c. 3 6 SCL VSS 4 5 SDA Fig.2 Pin configuration. Data transfer is unlimited in the read mode. The information is transmitted in bytes and each receiver acknowledges with a ninth bit. I2C-BUS PROTOCOL Within the I2C-bus specifications a low-speed mode (2 kHz clock rate), a high speed mode (100 kHz clock rate) and a fast speed mode (400 kHz clock rate) are defined. The PCF85116-3 operates in all three modes. By definition a device that sends a signal is called a ‘transmitter’, and the device which receives the signal is called a ‘receiver’. The device which controls the signal is called the ‘master’. The devices that are controlled by the master are called ‘slaves’. The following protocol has been defined: • Data transfer may be initiated only when the bus is not busy • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals. Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level, put on the bus by the transmitter. The master generates an extra acknowledge related clock pulse. The slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Bus conditions The following bus conditions have been defined: • Bus not busy: both data and clock lines remain HIGH. The master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • Start data transfer: a change in the state of the data line, from HIGH-to-LOW, while the clock is HIGH, defines the START condition The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. • Stop data transfer: a change in the state of the data line, from LOW-to-HIGH, while the clock is HIGH, defines the STOP condition • Data valid: the state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master generation of the STOP condition. Data transfer Each data transfer is initiated with a START condition and terminated with a STOP condition; the number of the data bytes, transferred between the START and STOP conditions is limited to 32 bytes in the E/W mode. 1997 Apr 02 1 MBH923 Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. 8.2 n.c. PCF85116-3 The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The serial bus consists of two bidirectional lines: one for data signals (SDA), and one for clock signals (SCL). 8.1 PCF85116-3 6 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface 8.3 Device addressing PCF85116-3 8.4.2 PAGE WRITE read: auto increment handbook, halfpage handbook, halfpage 1 0 1 0 B B B R/W B B B WORD ADDRESS MBH924 write: unchanged write: auto increment MBH925 Fig.3 Slave address. Fig.4 Auto increment of memory address. Following a START condition the bus master must output the address of the slave it is accessing. The 4 MSBs of the slave address are the device type identifier (see Fig.3). For the PCF85116-3 this is fixed to ‘1010’. The PCF85116-3 is capable of an 32-byte page write operation. It is initiated in the same manner as the byte write operation. The master can transmit up to 32 data bytes within one transmission. After receipt of each byte the PCF85116-3 will respond with an acknowledge. The master terminates the transfer by generating a STOP condition. The maximum total E/W time in this mode is 10 ms. The next three significant bits of the slave address field are the block selection bits. It is used by the host to select one out of eight blocks (1 block = 256 bytes of memory). These are, in effect, the three most significant bits of the word address. After the receipt of each data byte the six high order bits of the memory address providing access to one of the 64 pages of the memory remain unchanged. The five low order bits of the memory address will be incremented only (see Fig.3). By these five bits a single byte within the page in access is selected. By an increment the memory address may change from 31 to 0, from 63 to 32, etc. If the master transmits more than 32 bytes prior to generating the STOP condition, data within the addressed page may be overwritten and unpredictable results may occur. As in the byte write operation, all inputs are disabled until completion of the internal write cycles. The last bit of the slave address defines the operation to be performed. When R/W is set to logic 1 a read operation is selected. 8.4 8.4.1 Write operations BYTE/WORD WRITE For a write operation the PCF85116-3 requires a second address field. This address field is a word address providing access to any one of the eight blocks of memory. Upon receipt of the word address the PCF85116-3 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. Word address is automatically incremented. The master terminates the transfer by generating a STOP condition. 8.4.3 Write accesses to the EEPROM are enabled if the pin WP is LOW. When WP is HIGH the EEPROM is write-protected and no acknowledge will be given by the PCF85116-3 when data is sent. However, an acknowledge will be given after the slave address and the word address. After this stop condition the E/W cycle starts and the bus is free for another transmission. Its duration is maximum 10 ms. During the E/W cycle the slave receiver does not send an acknowledge bit if addressed via the I2C-bus. 1997 Apr 02 REMARK 7 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface acknowledge from slave acknowledge from slave handbook, full pagewidth B B B 0 A S SLAVE ADDRESS PCF85116-3 A WORD ADDRESS acknowledge from slave DATA acknowledge from slave DATA A A P R/W auto increment word address auto increment word address MBH926 Fig.5 Auto increment memory address; two byte write. acknowledge from slave handbook, full pagewidth S B B B 0 A SLAVE ADDRESS acknowledge from slave WORD ADDRESS acknowledge from slave DATA N A A acknowledge from slave DATA N + 1 A R/W auto increment word address auto increment word address acknowledge from slave DATA N + 31 A P last byte MBH927 Fig.6 Page write operation; 32 bytes. 1997 Apr 02 8 auto increment word address Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface 8.5 Read operations 8.5.1 Read operations are initiated in the same manner as write operations with the exception that the LSB of the slave address (R/W) is set to logic 1. There are three basic read operations; current address read, random read and sequential read. S B B B 0 A WORD ADDRESS A R/W SLAVE ADDRESS REMARK During read operations all bits of the memory address are incremented after each transmission of a data byte. Contrary to write operations an overflow of the memory address occurs from 2047 to 0 (see Fig.3). acknowledge from slave acknowledge from slave handbook, full pagewidth PCF85116-3 acknowledge from slave S B B B 1 A SLAVE ADDRESS R/W acknowledge from master DATA A n bytes auto increment word address at this moment master transmitter becomes master receiver and EEPROM slave receiver becomes slave transmitter no acknowledge from master DATA 1 P last byte auto increment word address MBH928 Fig.7 Master reads PCx85116-3 slave after setting word address (write word address; read data). acknowledge from master acknowledge from slave handbook, full pagewidth S B B B 1 A SLAVE ADDRESS R/W DATA A n bytes no acknowledge from master DATA 1 P last bytes auto increment word address auto increment word address MBH929 Fig.8 Master reads PCx85116-3 immediately after first byte (read mode). 1997 Apr 02 9 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface PCF85116-3 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT −0.3 +6.5 V VSS − 0.8 +6.5 V input current on any pin − 1 mA IO output current − 10 mA Tstg storage temperature −65 +150 °C Tamb operating ambient temperature −40 +85 °C Vesd electrostatic discharge voltage 2 − kV VDD supply voltage VI input voltage on any pin II Zi > 500 Ω note 1 Note 1. ESD Human Body model Q22 at Tamb = 22 °C; discharge procedure according to MIL-STD-883C Method 3015. 10 CHARACTERISTICS VDD = 2.7 to 5.5 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Supplies VDD supply voltage 2.7 5.5 V IDDR supply current read fSCL = 400 kHz; VDD = 5.5 V − 1.0 mA IDDW supply current E/W fSCL = 400 kHz; VDD = 5.5 V − 1.0 mA IDD(stb) standby supply current VDD = 2.7 V − 6 µA VDD = 5.5 V − 10 µA SDA input/output (pin 5) VIL LOW level input voltage −0.8 +0.3VDD V VIH HIGH level input voltage 0.7VDD 6.5 V VOL1 LOW level output voltage IOL = 3 mA; VDD(min) − 0.4 V IOL = 6 mA; VDD(min) − 0.6 V ILO output leakage current VOH = VDD − 1 µA to(f) output fall time from VIHmin to VILmax note 1 VOL2 with up to 3 mA sink current at VOL1 20 + 0.1Cb 250 ns with up to 6 mA sink current at VOL2 20 + 0.1Cb 250 ns 0 100 ns − 10 pF tSP pulse width of spikes suppressed by filter CI input capacitance 1997 Apr 02 VI = VSS 10 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface SYMBOL PARAMETER PCF85116-3 CONDITIONS MIN. MAX. UNIT SCL input (pin 6) VIL LOW level input voltage −0.8 +0.3VDD V VIH HIGH level input voltage 0.7VDD 6.5 V ILI input leakage current − ±1 µA fSCL clock input frequency 0 400 kHz tSP pulse width of spikes suppressed by filter 0 100 ns CI input capacitance − 7 pF VI = VDD or VSS VI = VSS WP input (pin 7) VIL LOW level input voltage −0.8 +0.1VDD V VIH HIGH level input voltage 0.9VDD VDD + 0.8 V 20 − years Data retention time tS Tamb = 55 °C data retention time Note 1. The bus capacitance ranges from 10 to 400 pF (Cb = total capacitance of one bus line in pF). 11 I2C-BUS CHARACTERISTICS All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing from VSS to VDD. STANDARD MODE SYMBOL PARAMETER FAST MODE CONDITIONS UNIT MIN. MAX. MIN. MAX. fSCL clock frequency 0 100 0 400 kHz tBUF time the bus must be free before new transmission can start 4.7 − 1.3 − µs tHD;STA START condition hold time after which first clock pulse is generated 4.0 − 0.6 − µs tLOW LOW level clock period 4.7 − 1.3 − µs tHIGH HIGH level clock period 4.0 − 0.6 − µs tSU; STA set-up time for START condition 4.7 − 0.6 − µs tHD; DAT data hold time 5 − − − µs 0 − 0 − ns data set-up time 250 − 100 − ns 300 ns 300 ns − µs repeated start for CBUS compatible masters for I2C-bus devices tSU; DAT note 1 tr SDA and SCL rise time − 1000 20 + tf SDA and SCL fall time − 300 20 + tSU; STO set-up time for STOP condition 4.0 − 0.6 0.1Cb(2) 0.1Cb(2) Notes 1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by a transmitter. 2. Cb = total capacitance of one bus line in pF. 1997 Apr 02 11 1997 Apr 02 P t BUF S t HD;STA t LOW tr 12 t HIGH handbook, full pagewidth t SU;DAT Fig.9 Timing requirements for the I2C-bus. t HD;DAT tf t SU;STO t SU;STA MBA705 P S t HD;STA 2048 × 8-bit CMOS EEPROM with I2C-bus interface P = STOP condition; S = START condition. SCL SDA Philips Semiconductors Product specification PCF85116-3 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface PCF85116-3 12 WRITE CYCLE LIMITS The Power-on-reset circuit resets the I2C-bus logic with a set-up time of ≤10 µs.Enabling the chip is achieved by connecting the WP input to VSS. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT E/W cycle timing tE/W − − 10 ms Tamb = −40 to +85 °C 100000 − − cycles Tamb = 22 °C 1000000 − − cycles E/W cycle time Endurance NE/W 1997 Apr 02 E/W cycle per byte 13 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface PCF85116-3 13 PACKAGE OUTLINES SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0098 0.014 0.0075 0.20 0.19 0.16 0.15 0.050 0.24 0.23 0.039 0.028 0.041 0.016 0.024 inches 0.0098 0.057 0.069 0.0039 0.049 0.01 0.01 0.028 0.004 0.012 θ Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA 1997 Apr 02 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 14 o 8 0o Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface PCF85116-3 DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 ME seating plane D A2 A A1 L c Z w M b1 e (e 1) b MH b2 5 8 pin 1 index E 1 4 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.14 0.53 0.38 1.07 0.89 0.36 0.23 9.8 9.2 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 1.15 inches 0.17 0.020 0.13 0.068 0.045 0.021 0.015 0.042 0.035 0.014 0.009 0.39 0.36 0.26 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.045 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT97-1 050G01 MO-001AN 1997 Apr 02 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 15 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. 14 SOLDERING 14.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 14.3.2 This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 14.2 14.2.1 • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. 14.3 14.3.1 14.3.3 REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1997 Apr 02 WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. 14.2.2 PCF85116-3 16 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface PCF85116-3 15 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 17 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Apr 02 17 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface NOTES 1997 Apr 02 18 PCF85116-3 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface NOTES 1997 Apr 02 19 PCF85116-3 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA53 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 417067/1200/02/pp20 Date of release: 1997 Apr 02 Document order number: 9397 750 01994