DISCRETE SEMICONDUCTORS DATA SHEET BST84 N-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor DESCRIPTION BST84 QUICK REFERENCE DATA N-channel vertical D-MOS transistor in SOT89 envelope and designed for use as line current interrupter in telephone sets and for application in relay, high-speed and line-transformer drivers. Drain-source voltage VDS max. 200 V Gate-source voltage (open drain) ±VGSO max. 20 V Drain current (DC) ID max. 250 mA Total power dissipation up to Tamb = 25 °C Ptot max. 1 W RDS(on) typ. max. 6 Ω 12 Ω Yfs typ. 250 mS Drain-source ON-resistance ID = 250 mA; VGS = 10 V FEATURES • Direct interface to C-MOS, TTL, etc. Transfer admittance ID = 250 mA; VDS = 15 V • High-speed switching • No second breakdown PINNING - SOT89 1 = source 2 = gate 3 = drain PIN CONFIGURATION handbook, halfpage handbook, 2 columns d g MBB076 - 1 s 1 3 Bottom view Marking: KN Fig.1 Simplified outline and symbol. April 1995 2 2 MSB013 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BST84 RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage VDS max. 200 V Gate-source voltage (open drain) ±VGSO max. 20 V Drain current (DC) ID max. 250 mA Drain current (peak) IDM max. 800 mA Total power dissipation up to Tamb = 25 °C (note 1) Ptot max. 1 W Storage temperature range Tstg Junction temperature Tj max. 150 °C Rth j-a = 125 K/W −65 to + 150 °C THERMAL RESISTANCE From junction to ambient (note 1) Note 1. Transistor mounted on a ceramic substrate with area of 2.5 cm2 and thickness of 0.7 mm. April 1995 3 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BST84 CHARACTERISTICS Tj = 25 °C unless otherwise specified Drain-source breakdown voltage ID = 100 µA; VGS = 0 V(BR)DSS min. 200 V IDSS max. 10 µA IGSS max. 100 nA VGS(th) min. max. 0.8 V 2.8 V RDS(on) typ. max. 6 Ω 12 Ω Yfs typ. 250 mS Ciss typ. max. 70 pF 90 pF Coss typ. max. 20 pF 30 pF Crss typ. max. 5 pF 10 pF ton typ. max. 4 ns 10 ns toff typ. max. 15 ns 25 ns Drain-source leakage current VDS = 160 V; VGS = 0 Gate-source leakage current VGS = 20 V; VDS = 0 Gate threshold voltage ID = 1 mA; VDS = VGS Drain-source ON-resistance ID = 250 mA; VGS = 10 V Transfer admittance ID = 250 mA; VDS = 15 V Input capacitance at f = 1 MHz VDS = 10 V; VGS = 0 Output capacitance at f = 1 MHz VDS = 10 V; VGS = 0 Feedback capacitance at f = 1 MHz VDS = 10 V; VGS = 0 Switching times (see Figs 2 and 3) ID = 250 mA; VDD = 50 V; VGS = 0 to 10 V April 1995 4 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor handbook, halfpage VDD = 50 V handbook, halfpage BST84 90 % INPUT 10 % 90 % 10 V OUTPUT ID 0V 10 % 50 Ω ton MBB691 toff MBB692 Fig.2 Switching times test circuit. 103 handbook, halfpage Fig.3 Input and output waveforms. MDA764 VGS = 10 V 5V ID (A) 0.8 4V ID MDA765 1 handbook, halfpage (mA) 0.6 102 0.4 0.2 10 0 4 6 8 10 12 14 RDSon (Ω) 0 Fig.4 Tj = 25 °C; typical values. April 1995 2 4 6 8 10 VGS (V) Fig.5 Tj = 25 °C; VDS = 10 V; typical values. 5 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor MDA766 1 handbook, halfpage MDA767 1.2 handbook, halfpage VGS = 10 V ID (A) 0.8 BST84 Ptot 5V (W) 0.8 0.6 4V 0.4 0.4 3V 0.2 0 0 2 0 4 6 8 0 10 VDS (V) Fig.6 Tj = 25 °C; typical values. MDA743 handbook, halfpage k k 2.5 1.1 2 1 1.5 0.9 1 0.8 0 50 100 Tj (°C) 0.7 −50 150 Fig.8 April 1995 150 200 Tamb (°C) 1.2 handbook, halfpage 0.5 −50 100 Fig.7 Power derating curve. MDA742 3 50 0 50 100 Tj (°C) 150 Fig.9 R DS (on) at T j k = ------------------------------------------- ; R DS (on) at 25 °C V GS ( th ) at T j k = --------------------------------------------- ; V GS ( th ) at 25 °C at 400 mA/10 V; typical values. VGS(th) at 1 mA; typical values. 6 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor MDA768 120 handbook, halfpage C (pF) 80 Ciss 40 Coss Crss 0 0 10 20 VDS (V) 30 Fig.10 Tj = 25 °C; VGS = 0; f = 1 MHz; typical values. April 1995 7 BST84 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BST84 PACKAGE OUTLINES Plastic surface mounted package; collector pad for good heat transfer; 3 leads SOT89 B D A b3 E HE L 1 2 3 c b2 w M b1 e1 e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A b1 b2 b3 c D E e e1 HE L min. w mm 1.6 1.4 0.48 0.35 0.53 0.40 1.8 1.4 0.44 0.37 4.6 4.4 2.6 2.4 3.0 1.5 4.25 3.75 0.8 0.13 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT89 April 1995 EUROPEAN PROJECTION ISSUE DATE 97-02-28 8 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BST84 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 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