PHILIPS BST82

DISCRETE SEMICONDUCTORS
DATA SHEET
BST82
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
DESCRIPTION
BST82
QUICK REFERENCE DATA
N-channel enhancement mode
vertical D-MOS transistor in SOT23
envelope and designed for use as
Surface Mounted Device (SMD) in
thin and thick-film circuits for
telephone ringer and for application
with relay, high-speed and
line-transformer drivers.
Drain-source voltage
VDS
max.
80 V
Drain-source voltage (non-repetitive peak;
tp ≤ 2 ms)
VDS(SM)
max.
100 V
Gate-source voltage (open drain)
±VGSO
max.
20 V
Drain current (DC)
ID
max.
175 mA
Total power dissipation up to Tamb = 25 °C
Ptot
max.
300 mW
RDS(on)
typ.
max.
7 Ω
10 Ω
 Yfs
typ.
150 mS
Drain-source ON-resistance
ID = 150 mA; VGS = 5 V
FEATURES
• Direct interface to C-MOS, TTL,
etc.
Transfer admittance
ID = 175 mA; VDS = 5 V
• High-speed switching
• No second breakdown
PINNING - SOT23
• Low RDS(on)
1
= gate
2
= source
3
= drain
PIN CONFIGURATION
handbook, 2 columns
3
handbook, halfpage
d
g
1
Top view
2
MBB076 - 1
MSB003
Marking: 02p
Fig.1 Simplified outline and symbol.
April 1995
2
s
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BST82
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage
VDS
max.
80 V
Drain-source voltage (non-repetitive peak; tp ≤ 2 ms)
VDS(SM)
max.
100 V
Gate-source voltage (open drain)
±VGSO
max.
20 V
Drain current (DC)
ID
max.
175 mA
Drain current (peak)
IDM
max.
600 mA
Total power dissipation up to Tamb = 25 °C (note 1)
Ptot
max.
300 mW
Storage temperature range
Tstg
Junction temperature
Tj
max.
150 °C
Rth j-a
=
430 K/W
−65 to + 150 °C
THERMAL RESISTANCE
From junction to ambient (note 1)
Note
1. Transistors mounted on a ceramic substrate of 7 mm x 5 mm x 0.7 mm.
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BST82
CHARACTERISTICS
Tj = 25 °C unless otherwise specified
Drain-source breakdown voltage
ID = 10 µA; VGS = 0
V(BR)DSS
min.
80 V
IDSS
max.
1.0 µA
IGSS
max.
100 nA
V(P)GS
min.
max.
1.5 V
3.5 V
RDS(on)
typ.
max.
7 Ω
10 Ω
 Yfs
typ.
150 mS
Ciss
typ.
max.
15 pF
30 pF
typ.
max.
13 pF
20 pF
typ.
max.
3 pF
6 pF
ton
typ.
max.
4 ns
10 ns
toff
typ.
max.
4 ns
10 ns
Drain-source leakage current
VDS = 60 V; VGS = 0
Gate-source leakage current
VGS = 20 V; VDS = 0
Gate-source cut-off voltage
ID = 1 mA; VDS = VGS
Drain-source ON-resistance
ID = 150 mA; VGS = 5 V
Transfer admittance
ID = 175 mA; VDS = 5 V
Input capacitance at f = 1 MHz
VDS = 10 V; VGS = 0
Output capacitance at f = 1 MHz
VDS = 10 V; VGS = 0
Coss
Feedback capacitance at f = 1 MHz
VDS = 10 V; VGS = 0
Crss
Switching times (see Figs 2 and 3)
ID = 175 mA; VDD = 50 V; VGS = 0 to 10 V
April 1995
4
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
VDD = 50 V
handbook, halfpage
BST82
handbook, halfpage
90 %
INPUT
10 %
90 %
10 V
OUTPUT
ID
0V
50 Ω
10 %
MSA631
ton
toff
MBB692
Fig.2 Switching times test circuit.
Fig.3 Input and output waveforms.
MDA762
103
handbook, halfpage
VGS = 10 V
6V
(mA)
VDS = 10 V
ID
(A)
8V
ID
MDA732
1
handbook, halfpage
5V
0.8
5V
0.6
102
0.4
0.2
10
0
2
4
6
0
8
10
RDSon (Ω)
0
Fig.4 Tj = 25 °C; typical values.
April 1995
2
4
6
8
10
VGS (V)
Fig.5 Tj = 25 °C; typical values.
5
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
MDA763
1
handbook, halfpage
VGS = 10 V
ID
(A)
0.8
BST82
MDA769
400
handbook, halfpage
9V
Ptot
(mW)
8V
300
7V
0.6
6V
200
0.4
5V
100
0.2
4V
3V
0
0
2
0
4
6
8
0
10
VDS (V)
Fig.6 Tj = 25 °C; typical values.
MDA736
handbook, halfpage
k
k
2.5
1.1
2
1
1.5
0.9
1
0.8
0
50
100
Tj (°C)
0.7
−50
150
0
50
100
Tj (°C)
Fig.9
Fig.8
April 1995
150
200
Tamb (°C)
1.2
handbook, halfpage
0.5
−50
100
Fig.7 Power derating curve.
MDA735
3
50
R DS (on) at T j
k = --------------------------------------------- ;
R DS (on) at 25 °C
V GS ( th ) at T j
k = --------------------------------------------- ;
V GS ( th ) at 25 °C
typ. values at 150 mA/5 V.
VGS(th) at 1 mA; typical values.
6
150
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
MDA737
50
handbook, halfpage
C
(pF)
40
30
20
Ciss
Coss
10
Crss
0
0
10
20
VDS (V)
30
Fig.10 Tj = 25 °C; VGS = 0; f = 1 MHz; typical values.
April 1995
7
BST82
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BST82
PACKAGE OUTLINES
Plastic surface mounted package; 3 leads
SOT23
D
E
B
A
X
HE
v M A
3
Q
A
A1
1
2
e1
bp
c
w M B
Lp
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max.
bp
c
D
E
e
e1
HE
Lp
Q
v
w
mm
1.1
0.9
0.1
0.48
0.38
0.15
0.09
3.0
2.8
1.4
1.2
1.9
0.95
2.5
2.1
0.45
0.15
0.55
0.45
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
97-02-28
SOT23
April 1995
EUROPEAN
PROJECTION
8
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BST82
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
April 1995
9
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
NOTES
April 1995
10
BST82
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
NOTES
April 1995
11
BST82
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© Philips Electronics N.V. 1997
SCA54
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137107/00/01/pp12
Date of release: April 1995
Document order number:
9397 750 02499