PHILIPS P87C749EBAA

INTEGRATED CIRCUITS
83C749/87C749
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM,
low pin count
Preliminary specification
Supersedes data of 1998 Jan 06
IC20 Data Handbook
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
DESCRIPTION
83C749/87C749
FEATURES
The Philips 83C749/87C749 offers many of the advantages of the
80C51 architecture in a small package and at low cost.
• Available in erasable quartz lid or One-Time Programmable plastic
The 8XC749 Microcontroller is fabricated with Philips high-density
CMOS technology. Philips epitaxial substrate minimizes CMOS
latch-up sensitivity.
• 80C51 based architecture
• Small package sizes
packages
– 28-pin DIP
The 8XC749 contains a 2k × 8 ROM (83C749) EPROM (87C749), a
64 × 8 RAM, 21 I/O lines, a 16-bit auto-reload counter/timer, a
fixed-priority level interrupt structure, an on-chip oscillator, a five
channel multiplexed 8-bit A/D converter, and an 8-bit PWM output.
– 28-pin Shrink Small Outline Package (SSOP)
– 28-pin PLCC
• Wide oscillator frequency range:
• Low power consumption:
The EPROM version of this device, the 87C749, is available in
plastic one-time programmable (OTP) packages. Once the array
has been programmed, it is functionally equivalent to the masked
ROM 83C749. Thus, unless explicitly stated otherwise, all
references made to the 83C749 apply equally to the 87C749.
3.5MHz to 16MHz
– Normal operation: less than 11mA @ 5V, 12MHz
– Idle mode
– Power-down mode
• 2k × 8 ROM (83C749)
The 83C749 supports two power reduction modes of operation
referred to as the idle mode and the power-down mode.
EPROM (87C749)
• 64 × 8 RAM
• 16-bit auto reloadable counter/timer
• 5-channel 8-bit A/D converter
• 8-bit PWM output/timer
• 10-bit fixed-rate timer
• Boolean processor
• CMOS and TTL compatible
• Well suited for logic replacement, consumer and industrial
applications
PART NUMBER SELECTION
ROM
EPROM1
P83C749EBP N
P87C749EBP N
OTP
P83C749EBA A
P87C749EBA A
OTP
P83C749EBD DB
P87C749EBD DB
OTP
NOTE:
1. OTP = One Time Programmable EPROM.
1998 Apr 23
TEMPERATURE RANGE °C
AND PACKAGE
FREQUENCY
DRAWING
NUMBER
0 to +70, 28-pin Plastic Dual In-line Package
3.5 to 16MHz
SOT117-2
0 to +70, 28-pin Plastic Leaded Chip Carrier
3.5 to 16MHz
SOT261-3
0 to +70, 28-pin Shrink Small Outline Package
3.5 to 16MHz
SOT341-1
2
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
BLOCK DIAGRAM
P0.0–P0.4
PORT 0
DRIVERS
VCC
PWM
VSS
RAM ADDR
REGISTER
PORT 0
LATCH
RAM
B
REGISTER
PORT 2
LATCH
ROM/
EPROM
STACK
POINTER
ACC
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
ALU
PCON
TCON
BUFFER
IE
PSW
TH0
TL0
RTH
RTL
INTERRUPT AND
TIMER BLOCKS
PC
INCREMENTER
RST
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
PROGRAM
COUNTER
DPTR
PD
PORT 1
LATCH
PORT 3
LATCH
PORT 1
DRIVERS
PORT 3
DRIVERS
P1.0–P1.7
P3.0–P3.7
OSCILLATOR
ADC
X1
X2
AVSS
AVCC
SU00305
1998 Apr 23
3
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
PIN CONFIGURATION
P3.4/A4 1
28 VCC
P3.3/A3 2
27 P3.5/A5
P3.2/A2/A10 3
26 P3.6/A6
P3.1/A1/A9 4
25 P3.7/A7
P3.0/A0/A8 5
P0.2/VPP
6
P0.1/OE–PGM
7
P0.0/ASEL
8
RST
9
24 P0.4/PWM OUT
PLASTIC
DUAL
IN-LINE
PACKAGE
AND
SHRINK
SMALL
OUTLINE
PACKAGE
23 P0.3
22 P1.7/T0/D7
21 P1.6/INT1/D6
20 P1.5/INT0/D5
X2 10
19 AVCC
X1 11
18 AVSS
VSS 12
17 P1.4/ADC4/D4
P1.0/ADC0/D0 13
16 P1.3/ADC3/D3
P1.1/ADC1/D1 14
15 P1.2/ADC2/D2
4
1
26
5
25
PLASTIC
LEADED
CHIP
CARRIER
11
19
12
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Function
P3.4/A4
P3.3/A3
P3.2/A2/A10
P3.1/A1/A9
P3.0/A0/A8
P0.2/VPP
P0.1/OE-PGM
P0.0/ASEL
RST
X2
X1
VSS
P1.0/ADC0/D0
P1.1/ADC1/D1
18
Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Function
P1.2/ADC2/D2
P1.3/ADC3/D3
P1.4/ADC4/D4
AVSS
AVCC
P1.5/INT0/D5
P1.6/INT1/D6
P1.7/T0/D7
P0.3
P0.4/PWM OUT
P3.7/A7
P3.6/A6
P3.5/A5
VCC
SU00304
1998 Apr 23
4
83C749/87C749
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
83C749/87C749
PIN DESCRIPTION
PIN NO.
TYPE
VSS
MNEMONIC
12
I
Circuit Ground Potential.
VCC
28
I
Supply voltage during normal, idle, and power-down operation.
8–6
23, 24
I/O
P0.0–P0.4
P1.0–P1.7
6
7
I
I
8
I
13–17,
20–22
I/O
20
21
22
13–17
I
I
I
I
NAME AND FUNCTION
Port 0: Port 0 is a 5-bit bidirectional port. Port 0.0–P0.2 are open drain. Port 0.0–P0.2 pins that have
1s written to them float, and in that state can be used as high-impedance inputs. P0.3–P0.4 are
bidirectional I/O port pins with internal pull-ups. These pins are driven low if the port register bit is
written with a 0. The state of the pin can always be read from the port register by the program. Port 0.3
and 0.4 have internal pull-ups that function identically to port 3. Pins that have 1s written to them are
pulled high by the internal pull-ups and can be used as inputs.
While P0.0 anbd P0.1 differ from “standard TTL” characteristics, they are close enough for the pins to
still be used as general-purpose I/O.
VPP (P0.2) – Programming voltage input. (See Note 2.)
OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. P0.3–P0.4 pins are
bidirectional I/O port pins with internal pull-ups. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also
serves the special function features of the SC80C51 family as listed below:
INT0 (P1.5): External interrupt.
INT1 (P1.6): External interrupt.
T0 (P1.7): Timer 0 external input.
ADC0 (P1.0)–ADC4 (P1.4): Port 1 also functions as the inputs to the five channel multiplexed A/D
converter. These pins can be used as outputs only if the A/D function has been disabled. These pins
can be used as digital inputs while the A/D converter is enabled.
Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs the
value to program into the selected address during the program mode.
P3.0–P3.7
5–1,
27–25
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are
externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also functions as the address input for the EPROM memory location to be
programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL.
RST
9
I
Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An
internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to VCC.
After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device
in the programming state allowing programming address, data and VPP to be applied for programming
or verification purposes. The RESET serial sequence must be synchronized with the X1 input.
X1
11
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1
also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2
10
O
Crystal 2: Output from the inverting oscillator amplifier.
AVCC
1
19
I
Analog supply voltage and reference input.
AVSS
1
18
I
Analog supply and reference ground.
NOTE:
1. AVSS (reference ground) must be connected to 0V (ground). AVCC (reference input) cannot differ from VCC by more than ±0.2V, and must be
in the range 4.5V to 5.5V.
2. When P0.2 is at or close to 0 volt, it may affect the internal ROM operation. We recommend that P0.2 be tied to VCC via a small pullup
(e.g., 2kΩ).
1998 Apr 23
5
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
OSCILLATOR CHARACTERISTICS
DIFFERENCES BETWEEN THE 8XC749 AND THE
80C51
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
Program Memory
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
On the 8XC749, program memory is 2048 bytes long and is not
externally expandable, so the 80C51 instructions MOVX, LJMP, and
LCALL are not implemented. If these instructions are executed, the
appropriate number of instruction cycles will take place along with
external fetches; however, no operation will take place. The LJMP
may not respond to all program address bits. The only fixed
locations in program memory are the addresses at which execution
is taken up in response to reset and interrupts, which are as follows:
Program Memory
Event
Address
Reset
000
003
External INT0
Counter/timer 0
00B
External INT1
013
Timer I
01B
ADC
02B
PWM
033
IDLE MODE
The 8XC749 includes the 80C51 power-down and idle mode
features. In idle mode, the CPU puts itself to sleep while all of the
on-chip peripherals except the A/D and PWM stay active. The
functions that continue to run while in the idle mode are Timer 0,
Timer I, and the interrupts. The instruction to invoke the idle mode is
the last instruction executed in the normal operating mode before
the idle mode is activated. The CPU contents, the on-chip RAM, and
all of the special function registers remain intact during this mode.
The idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset. Upon powering-up the
circuit, or exiting from idle mode, sufficient time must be allowed for
stabilization of the internal analog reference voltages before an A/D
conversion is started.
Memory Organization
The 8XC749 manipulates operands in three memory address
spaces. The first is the program memory space which contains
program instructions as well as constants such as look-up tables.
The program memory space contains 2k bytes in the 8XC749.
The second memory space is the data memory array which has a
logical address space of 128 bytes. However, only the first 64 (0 to
3FH) are implemented in the 8XC749.
Special Function Registers
The special function registers (directly addressable only) contain all
of the 8XC751 registers except the program counter and the four
register banks. Most of the 21 special function registers are used to
control the on-chip peripheral hardware. Other registers include
arithmetic registers (ACC, B, PSW), stack pointer (SP) and data
pointer registers (DPH, DPL). Nine of the SFRs are bit addressable.
The third memory space is the special function register array having
a 128-byte address space (80H to FFH). Only selected locations in
this memory space are used (see Table 2). Note that the
architecture of these memory spaces (internal program memory,
internal data memory, and special function registers) is identical to
the 80C51, and the 8XC749 varies only in the amount of memory
physically implemented.
Data Pointer
The data pointer (DPTR) consists of a high byte (DPH) and a low
byte (DPL). In the 80C51 this register allows the access of external
data memory using the MOVX instruction. Since the 83C749 does
not support MOVX or external memory accesses, this register is
generally used as a 16-bit offset pointer of the accumulator in a
MOVC instruction. DPTR may also be manipulated as two
independent 8-bit registers.
The 8XC749 does not directly address any external data or program
memory spaces. For this reason, the MOVX instructions in the
80C51 instruction set are not implemented in the 83C749, nor are
the alternate I/O pin functions RD and WR.
I/O Ports
The I/O pins provided by the 83C749 consist of port 0, port 1, and
port 3.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON.
Port 0
Port 0 is a 5-bit bidirectional I/O port and includes alternate functions
on some pins of this port. Pins P0.3 and P0.4 are provided with
internal pullups while the remaining pins (P0.0, P0.1, and P0.2) have
open drain output structures. The alternate function for port P0.4 is
PWM output.
If the alternate function PWM is not being used, then this pin may be
used as an I/O port.
Table 1. External Pin Status During Idle and
Power-Down Modes
MODE
Idle
Power-down
*
Port 0*
Port 1
Port 2
Data
Data
Data
Data
Data
Data
Except for PWM output (P0.4).
1998 Apr 23
83C749/87C749
6
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
Port 1
Port 1 is an 8-bit bidirectional I/O port whose structure is identical to
the 80C51, but also includes alternate input functions on all pins.
The alternate pin functions for port 1 are:
interrupt service routine and elsewhere must be explicitly saved).
The Timer I interrupt flag is cleared by setting the CKRTI bit (bit 5 of
the I1CFG register. For more information, see application note
AN427.
P1.0-P1.4 - ADC0-ADC4 - A/D converter analog inputs
P1.5 INT0 - external interrupt 0 input
P1.6 INT1 - external interrupt 1 input
P1.7 - T0 - timer 0 external input
Interrupt Subsystem—Fixed Priority
The IP register and the 2-level interrupt system of the 80C51 are
eliminated. The interrupt structure is a seven-source, one-level
interrupt system similar to the 8XC751. Simultaneous interrupt
conditions are resolved by a single-level, fixed priority as follows:
Highest priority:
Pin INT0
Counter/timer flag 0
Pin INT1
PWM
Timer I
Lowest priority:
ADC
If the alternate functions INT0, INT1, or T0 are not being used, these
pins may be used as standard I/O ports. It is necessary to connect
AVCC and AVSS to VCC and VSS, respectively, in order to use P1.5,
P1.6, and P1.7 pins as standard I/O pins. When the A/D converter is
enabled, the analog channel connected to the A/D may not be used
as a digital input; however, the remaining analog inputs may be used
as digital inputs. They may not be used as digital outputs. While the
A/D is enabled, the analog inputs are floating.
The vector addresses are as follows:
Source
INT0
TF0
INT1
TIMER I
ADC
PWM
Port 3
Port 3 is an 8-bit bidirectional I/O port whose structure is identical to
the 80C51. Note that the alternate functions associated with port 3
of the 80C51 have been moved to port 1 of the 83C749 (as
applicable). See Figure 1 for port bit configurations.
Counter/Timer Subsystem
The 8XC749 has one counter/timer called timer/counter 0. Its
operation is similar to mode 2 operation on the 80C51, but is
extended to 16 bits with 16 bits of autoload. The controls for this
counter are centralized in a single register called TCON.
Interrupt Control Registers
The 80C51 interrupt enable register is modified to take into account
the different interrupt sources of the 8XC749.
Timer I Implementation
Timer I is clocked once per machine cycle, which is the oscillator
frequency divided by 12. The timer operation is enabled by setting
the TIRUN bit (bit 4) in the I2CFG register. Writing a 0 into the
TIRUN bit will stop and clear the timer. The timer is 10 bits wide, and
when it reaches the terminal count of 1024, it carries out and sets
the Timer I interrupt flag. An interrupt will occur if the Timer I
interrupt is enabled by bit ETI (bit 4) of the Interrupt Enable (IE)
register, and global interrupts are enabled by bit EA (bit 7) of the
same IE register.
Interrupt Enable Register
MSB
ALTERNATE
OUTPUT
FUNCTION
LSB
EAD
EA
Position
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
The vector address for the Timer I interrupt is 1Bhex, and the
interrupt service routine must start at this address. As with all 8051
family microcontrollers, only the Program Counter is pushed onto
the stack upon interrupt (other registers that are used both by the
READ
LATCH
Vector Address
0003H
000BH
0013H
001BH
002BH
0033H
ETI
—
Symbol
EA
EAD
ETI
—
EPWM
EX1
ET0
EX0
EX1
ET0
EX0
Function
Global interrupt disable when EA = 0
A/D conversion complete
Timer I
PWM counter overflow
External interrupt 1
Timer 0 overflow
External interrupt 0
ALTERNATE
OUTPUT
FUNCTION
READ
LATCH
VDD
EPWM
INTERNAL
PULL-UP
INT. BUS
D
P1.X
LATCH
WRITE TO
LATCH
READ
PIN
INT. BUS
Q
CL
D
Q
P0.X
LATCH
P1.X
PIN
WRITE TO
LATCH
Q
READ
PIN
ALTERNATE INPUT
FUNCTION
CL
P0.X
PIN
Q
ALTERNATE INPUT
FUNCTION
SU00306
Figure 1. Port Bit Latches and I/O Buffers
1998 Apr 23
7
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
ADCON Register
Pulse Width Modulation Output (P0.4)
The PWM outputs pulses of programmable length and interval. The
repetition frequency is defined by an 8-bit prescaler which generates
the clock for the counter. The prescaler register is PWMP. The
prescaler and counter are not associated with any other timer. The
8-bit counter counts modulo 255, that is from 0 to 254 inclusive. The
value of the 8-bit counter is compared to the contents of a compare
register, PWM. When the counter value matches the contents of this
register, the output of the PWM is set high. When the counter reaches
zero, the output of the PWM is set low. The pulse width ratio (duty
cycle) is defined by the contents of the compare register and is in the
range of 0 to 1 programmed in increments of 1/255. The PWM output
can be set to be continuously high by loading the compare register
with 0 and the output can be set to be continuously low by loading the
compare register with 255. The PWM output is enabled by a bit in a
special function register, PWENA. When enabled, the pin output is
driven with a fully active pull-up. That is, when the output is high, a
strong pull-up is continuously applied. When disabled, the pin
functions as a normal bidirectional I/O pin, however, the counter
remains active.
MSB
X
ADCI
0
0
1
ADCS
0
1
0
1
1
ENADC
ADCI
ADCS
AADR2
AADR1
AADR0
Operation
ADC not busy, a conversion can be started.
ADC busy, start of a new conversion is blocked.
Conversion completed, start of a new conversion is
blocked.
Not possible.
INPUT CHANNEL SELECTION
ADDR2
ADDR1
ADDR0
INPUT PIN
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
P1.0
P1.1
P1.2
P1.3
P1.4
Position Symbol
Function
ADCON.5 ENADC Enable A/D function when ENADC = 1. Reset
forces ENADC = 0.
ADCON.4 ADCI
ADC interrupt flag. This flag is set when an
ADC conversion is complete. If IE.6 = 1, an
interrupt is requested when ADCI = 1. The
ADCI flag is cleared when conversion data is
read. This flag is read only.
ADCON.3 ADCS
ADC start. Setting this bit starts an A/D
conversion. Once set, ADCS remains high
throughout the conversion cycle. On
completion of the conversion, it is reset just
before the ADCI interrupt flag is cleared.
ADCS cannot be reset by software. ADCS
should not be used to monitor the A/D
converter status. ADCI should be used for this
purpose.
ADCON.2 AADR2 Analog input select.
ADCON.1 AADR1 Analog input select.
ADCON.0 AADR0 Analog input select. This binary coded
address selects one of the five analog input
port pins of P1 to be input to the converter. It
can only be changed when ADCI and ADCS
are both low. AADR2 is the most significant
bit.
The PWM function is disabled during RESET and remains disabled
after reset is removed until re-enabled by software. The PWM output
is high during power down and idle. The counter is disabled during
idle. The repetition frequency of the PWM is given by:
fPWM = fOSC / 2 (1 + PWMP) 255
The low/high ratio of the PWM signal is PWM / (255 – PWM) for
PWM not equal to 255. For PWM = 255, the output is always low.
The repetition frequency range is 92Hz to 23.5kHz for an oscillator
frequency of 12MHz.
An interrupt will be asserted upon PWM counter overflow if the
interrupt is not masked off.
The PWM output is an alternative function of P0.4. In order to use
this port as a bidirectional I/O port, the PWM output must be
disabled by clearing the enable/disable bit in PWENA. In this case,
the PWM subsystem can be used as an interval timer by enabling
the PWM interrupt.
Special Function Register Addresses
Special function registers for the 8XC749 are identical to those of
the 80C51, except for the changes listed below:
80C51 special function registers not present in the 8XC749 are
TMOD (89), P2 (A0) and IP (B8). Additional special function
registers are ADCON (A0), ADAT (84), PWM (8E), PWMP (8F), and
PWENA (FE).
The completion of the 8-bit ADC conversion is flagged by ADCI in
the ADCON register, and the result is stored in the special function
register ADAT.
A/D Converter
An ADC conversion in progress is unaffected by an ADC start. The
result of a completed conversion remains unaffected provided ADCI
remains at a logic 1. While ADCS is a logic 1 or ADCI is a logic 1, a
new ADC START will be blocked and consequently lost. An ADC
conversion in progress is aborted when the idle or power-down
mode is entered. The result of a completed conversion (ADCI = logic
1) remains unaffected when entering the idle mode. See Figure 2 for
an A/D input equivalent circuit.
The analog input circuitry consists of a 5-input analog multiplexer and
an A to D converter with 8-bit resolution. The conversion takes 40
machine cycles, i.e., 40µs at 12MHz oscillator frequency. The A/D
converter is controlled using the ADCON control register. Input
channels are selected by the analog multiplexer through ADCON
register bits 0–2.
The 83C749 contains a five-channel multiplexed 8-bit A/D converter.
The conversion requires 40 machine cycles (40µs at 12MHz
oscillator frequency).
The analog input pins ADC0-ADC4 may be used as digital inputs
and outputs when the A/D converter is disabled by a 0 in the
ENADC bit in ADCON. When the A/D is enabled, the analog input
channel that is selected by the ADDR2-ADDR0 bits in ADCON
cannot be used as a digital input. Reading the selected A/D channel
as a digital input will always return a 1. The unselected A/D inputs
The A/D converter is controlled by the A/D control register, ADCON.
Input channels are selected by the analog multiplexer by bits
ADCON.0 through ADCON.2. The ADCON register is not bit
addressable.
1998 Apr 23
LSB
X
8
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
supply pins. AVSS must be connected to 0V and AVCC must be
connected to a supply voltage between 4.5V and 5.5V. A/D
measurements may be made in the range of 4.5V to 5.5V.
Increasing the voltage on the A/D ground reference above 0V or
reducing the voltage on the positive A/D reference below 4.5V is not
permitted.
may always be used as digital inputs. Unselected analog inputs will
be floating and may not be used as digital outputs.
The A/D reference inputs on the 8XC749 are tied together with the
analog supply pins AVCC and AVSS. This means that the reference
voltage on the A/D cannot be varied separately from the analog
Table 2.
SYMBOL
8XC749 Special Function Registers
DESCRIPTION
DIRECT
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
ADDRESS MSB
LSB
ACC*
Accumulator
E0H
ADAT#
A/D result
84H
ADCON#
A/D control
A0H
–
–
ENADC
ADCI
ADCS
AADR2
AADR1
AADR0
C0H
B*
B register
F0H
F7
F6
F5
F4
F3
F2
F1
F0
00H
DPTR:
Data pointer
(2 bytes)
Data pointer low
Data pointer high
82H
83H
DPL
DPH
IE*#
Interrupt enable
ADH
E7
E6
E5
E4
E3
E2
E1
E0
RESET
VALUE
00H
00H
00H
00H
AF
AE
AD
AC
AB
AA
A9
A8
EA
EAD
–
–
ETI
—
EPWM
EX1
ET0
EX0
–
84
83
82
81
80
–
–
PWM0
–
–
–
–
xxx11111B
FFH
00H
P0*#
Port 0
80H
–
97
96
95
94
93
92
91
90
P1*#
Port 1
90H
T0
INT1
INT0
ADC4
ADC3
ADC2
ADC1
ADC0
P3*
Port 3
B0H
B7
B6
B5
B4
B3
B2
B1
B0
FFH
PCON#
Power control
87H
–
–
–
–
–
–
PD
IDL
xxxx0000B
D7
D6
D5
D4
D3
D2
D1
D0
PSW*
Program status word
D0H
CY
AC
F0
RS1
RS0
OV
–
P
PWCM#
PWM compare
8EH
PWENA#
PWM enable
FEH
–
–
–
–
–
–
–
PWE
PWMP#
PWM prescaler
8FH
00H
RTL#
Timer low reload
8BH
00H
RTH#
Timer high reload
8DH
00H
SP
Stack pointer
81H
07H
TL#
Timer low
8AH
00H
TH#
Timer high
8CH
TICON*#
Timer I control
xxxxxxxxB
FEH
00H
DF
DE
D8H/RD
–
WR
–
8F
TCON*#
Timer control
88H
GATE
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
1998 Apr 23
00H
DD
DC
DB
DA
D9
D8
–
0
TIRUN
–
–
–
–
–
CLRTI
TIRUN
–
–
–
–
8E
8D
8C
8B
8A
89
88
C/T
TF
TR
IE0
IT0
IE1
IT1
9
0000xx00B
00H
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
SmN+1
RmN+1
SmN
RmN
IN+1
IN
To Comparator
+
Multiplexer
RS
CC
CS
VANALOG
INPUT
Rm = 0.5 - 3 kΩ
CS + CC = 15pF maximum
RS = Recommended < 9.6 kΩ for 1 LSB @ 12MHz
NOTE:
Because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. When a conversion
is initiated, switch Sm closes for 8tcy (8µs @ 12MHz crystal frequency) during which time capacitance Cs + Cc is charged. It should
be noted that the sampling causes the analog input to present a varying load to an analog source.
SU00199
Figure 2. A/D Input: Equivalent Circuit
A/D CONVERTER PARAMETER DEFINITIONS
Offset Error
The following definitions are included to clarify some specifications
given and do not represent a complete set of A/D parameter
definitions.
Offset error is the difference between the actual input voltage that
causes the first code transition and the ideal value to cause the first
code transition. This ideal value is 1/2 LSB above Vref–.
Absolute Accuracy Error
Channel to Channel Matching
Absolute accuracy error of a given output is the difference between
the theoretical analog input voltage to produce a given output and
the actual analog input voltage required to produce the same code.
Since the same output code is produced by a band of input voltages,
the “required input voltage” is defined as the midpoint of the band of
input voltage that will produce that code. Absolute accuracy error
not specified with a code is the maximum over all codes.
Channel to channel matching is the maximum difference between
the corresponding code transitions of the actual characteristics
taken from different channels under the same temperature, voltage
and frequency conditions.
Crosstalk
Crosstalk is the measured level of a signal at the output of the
converter resulting from a signal applied to one deselected channel.
Nonlinearity
Total Error
If a straight line is drawn between the end points of the actual
converter characteristics such that zero offset and full scale errors
are removed, then non-linearity is the maximum deviation of the
code transitions of the actual characteristics from that of the straight
line so constructed. This is also referred to as relative accuracy and
also integral non-linearity.
Maximum deviation of any step point from a line connecting the ideal
first transition point to the ideal last transition point.
Relative Accuracy
Relative accuracy error is the deviation of the ADC’s actual code
transition points from the ideal code transition points on a straight
line which connects the ideal first code transition point and the final
code transition point, after nullifying offset error and gain error. It is
generally expressed in LSBs or in percent of FSR.
Differential Non-Linearity
Differential non-linearity is the maximum difference between the
actual and ideal code widths of the converter. The code widths are
the differences expressed in LSB between the code transition
points, as the input voltage is varied through the range for the
complete set of codes.
Gain Error
Gain error is the deviation between the ideal and actual analog input
voltage required to cause the final code transition to a full-scale
output code after the offset error has been removed. This may
sometimes be referred to as full scale error.
1998 Apr 23
10
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
These flags are functionally identical to the corresponding 80C51
flags except that there is only one of the 80C51 style timers, and the
flags are combined into one register.
COUNTER/TIMER
The 8XC749 counter/timer is designated Timer 0 and is separate
from Timer I and from the PWM. Its operation is similar to mode 2 of
the 80C51 counter/timer, extended to 16 bits. When Timer 0 is used
in the external counter mode, the T0 input (P1.7) is sampled every
S4P1. The counter/timer function is controlled using the timer control
register (TCON).
Note that the positions of the IE0/IT0 and IE1/IT1 bits are
transposed from the positions used in the standard 80C51 TCON
register.
Timer I may be used as a fixed time base timer or watchdog timer.
TCON Register
MSB
GATE
Timer T0 is a 16-bit autoreloadable timer/counter, that operates
similar to mode 2 operation on the 80C51, but is extended to 16 bits.
The timer/counter is clocked by either 1/12 the oscillator frequency
or by transitions on the T0 pin. The C/T bit in special function
register TCON selects between these two modes. When the TCON
TR bit is set, the timer/counter is enabled. Register pair TH and TL
are incremented by the clock source. When the register pair
overflows, the register pair is reloaded with the values in registers
RTH and RTL. The value in the reload registers is left unchanged.
The TF bit in special function register TCON is set on counter
overflow and, if the interrupt is enabled, will generate an interrupt
(see Figure 3).
LSB
C/T
TF
TR
IE0
IT0
IE1
IT1
Position Symbol
Function
TCON.7 GATE 1 – Timer 0 is enabled only when INT0 pin is
high and TR is 1.
0 – Timer 0 is enabled only when TR is 1.
TCON.6 C/T
1 – Counter operation from T0 pin.
0 – Timer operation from internal clock.
TCON.5 TF
1 – Set on overflow of T0.
0 – Cleared when processor vectors to interrupt
routine and by reset.
TCON.4 TR
1 – Enable timer 0
0 – Disable timer 0
TCON.3 IE0
1 – Edge detected on INT0
TCON.2 IT0
1 – INT0 is edge triggered.
0 – INT0 is level sensitive.
TCON.1 IE1
1 – Edge detected on INT1
TCON.0 IT1
1 – INT1 is edge triggered.
0 – INT1 is level sensitive.
÷ 12
OSC
C/T = 0
TL
TH
TF
Int.
C/T = 1
T0 Pin
TR
Reload
Gate
RTL
RTH
INT0 Pin
SU00300
Figure 3. 83C749 Counter/Timer Block Diagram
ABSOLUTE MAXIMUM RATINGS1, 3, 4
PARAMETER
Storage temperature range
Voltage from VCC to VSS
Voltage from any pin to VSS (except VPP)
Power dissipation
Voltage from VPP pin to VSS
NOTES ON PAGE 13.
1998 Apr 23
11
RATING
UNIT
–65 to +150
°C
–0.5 to +6.5
V
–0.5 to VCC + 0.5
V
1.0
W
–0.5 to + 13.0
V
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C, AVCC = 5V ±5, AVSS = 0V4
VCC = 5V ± 10%, VSS = 0V
LIMITS4
TEST
SYMBOL
ICC
PARAMETER
CONDITIONS
MIN
TYP1
MAX
UNIT
Supply current (see Figure 6)
Inputs
VIL
VIH
VIH1
Input low voltage
Input high voltage, except X1, RST
Input high voltage, X1, RST
(0 to 70°C)
(0 to 70°C)
(0 to 70°C)
–0.5
0.2VCC+0.9
0.7VCC
0.2VCC–0.1
VCC+0.5
VCC+0.5
V
V
V
VIL1
VIH2
P0.2
Input low voltage
Input high voltage
(0 to 70°C)
(0 to 70°C)
–0.5
0.7VCC
0.3VCC
VCC+0.5
V
V
0.45
0.45
V
V
Outputs
VOL
VOL1
Output low voltage, ports 1, 3, 0.3, and 0.4
(PWM disabled)
Output low voltage, port 0.2
VOH
Output high voltage, ports 1, 3, 0.3, and 0.4
(PWM disabled)
VOH2
Output high voltage, P0.4 (PWM enabled)
VOL2
Port 0.0 and 0.1 – Drivers
Output low voltage
Driver, receiver combined:
Capacitance
C
IIL
ILI
Logical 0 input current,
ports 1, 3, 0.3, and 0.4 (PWM disabled)11
Logical 1 to 0 transition current,
ports 1, 3, 0.3 and 0.411
Input leakage current, port 0.0, 0.1 and 0.2
RRST
Reset pull-down resistor
CIO
Pin capacitance
IPD
Power-down current5
VPP
VPP program voltage (87C749 only)
IPP
Program current (87C749 only)
ITL
IOL = 1.6mA2
IOL = 3.2mA2
IOH = –60µA,
IOH = –25µA
IOH = –10µA
IOH = –400µA
IOH = –40µA
2.4
0.75VCC
0.9VCC
2.4
0.9VCC
V
V
V
V
V
IOL = 3mA
((over VCC range))
0.4
10
pF
VIN = 0.45V (0 to 70°C)
–50
µA
VIN = 2V (0 to 70°C)
–650
µA
V
±10
µA
175
kΩ
Test freq = 1MHz,
Tamb = 25°C
10
pF
VCC = 2 to 5.5V
VCC = 2 to 6.0V
(83C749)
50
µA
13.0
V
50
mA
5.5
V
39
mA
AVCC+0.2
V
15
pF
0.45 < VIN < VCC
25
VSS = 0V
VCC = 5V±10%
Tamb = 21°C to 27°C
12.5
VPP = 13.0V
Analog Inputs (A/D guaranteed only with quartz window covered.)
AVCC
Analog supply voltage10
AVCC = VCC±0.2V
4.5
AICC
Analog operating supply current
AVIN
Analog input voltage
AVCC = 5.12V
CIA
Analog input capacitance
tADS
Sampling time
8tCY
s
tADC
Conversion time
40tCY
s
AVSS–0.2
NOTES ON FOLLOWING PAGE.
1998 Apr 23
12
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
DC ELECTRICAL CHARACTERISTICS (Continued)
Tamb = 0°C to +70°C, AVCC = 5V ±5, AVSS = 0V4
VCC = 5V ± 10%, VSS = 0V
LIMITS4
TEST
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP1
MAX
UNIT
Analog Inputs (A/D guaranteed only with quartz window covered.) (Continued)
R
Resolution
8
bits
ERA
Relative accuracy
±1
LSB
OSe
Zero scale offset
±1
LSB
Ge
Full scale gain error
0.4
%
MCTC
Channel to channel matching
±1
LSB
Ct
Crosstalk
–60
dB
0–100kHz
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10mA
(NOTE: This is 85°C spec.)
26mA
Maximum IOL per 8-bit port:
Maximum total IOL for all outputs:
67mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
5. Power-down ICC is measured with all output pins disconnected; port 0 = VCC; X2, X1 n.c.; RST = VSS.
6. ICC is measured with all output pins disconnected; X1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;
RST = port 0 = VCC. ICC will be slightly higher if a crystal oscillator is used.
7. Idle ICC is measured with all output pins disconnected; X1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;
port 0 = VCC; RST = VSS.
8. Load capacitance for ports = 80pF.
9. The resistor ladder network is not disconnected in the power down or idle modes. Thus, to conserve power, the user may remove AVCC.
10. If the A/D function is not required, or if the A/D function is only needed periodically, AVCC may be removed without affecting the operation of
the digital circuitry. Contents of ADCON and ADAT are not guaranteed to be valid. If AVCC is removed, the A/D inputs must be lowered to
less than 0.5V. Digital inputs on P1.0–P1.4 will not function normally.
11. These parameters do not apply to P1.0–P1.4 if the A/D function is enabled.
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V4, 8
16MHz CLOCK
SYMBOL
1/tCLCL
PARAMETER
MIN
MAX
Oscillator frequency:
VARIABLE CLOCK
MIN
MAX
UNIT
3.5
16
MHz
External Clock (Figure 4)
tCHCX
High time
20
tCLCX
Low time
20
tCLCH
Rise time
20
20
ns
tCHCL
Fall time
20
20
ns
1998 Apr 23
13
20
ns
20
ns
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
EXPLANATION OF THE AC SYMBOLS
L –
Q–
T –
V–
X–
Z –
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal.
The designations are:
C – Clock
D – Input data
H – Logic level high
Logic level low
Output data
Time
Valid
No longer a valid logic level
Float
tCLCX
VCC –0.5
0.2 VCC + 0.9
0.2 VCC – 0.1
tCHCX
0.45V
tCLCH
tCHCL
tCLCL
SU00297
Figure 4. External Clock Drive
VCC –0.5
0.2 VCC + 0.9
0.2 VCC – 0.1
0.45V
SU00307
Figure 5. AC Testing Input/Output
MAX ACTIVE ICC6
22
20
18
16
14
ICC mA
TYP ACTIVE ICC6
12
10
8
6
MAX IDLE ICC7
4
2
TYP IDLE ICC7
4MHz
8MHz
12MHz
16MHz
FREQ
SU00308
Figure 6. ICC vs. FREQ
Maximum ICC values taken at VCC = 5.5V and worst case temperature.
Typical ICC values taken at VCC = 5.0V and 25°C.
Notes 6 and 7 refer to AC Electrical Characteristics.
1998 Apr 23
14
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
repeated until a total of 25 programming pulses have occurred. At
the conclusion of the last pulse, the PGM/ signal should remain high.
PROGRAMMING CONSIDERATIONS
EPROM Characteristics
The VPP signal may now be driven to the VOH level, placing the
87C749 in the verify mode. (Port 1 is now used as an output port).
After four machine cycles (48 clock periods), the contents of the
addressed location in the EPROM array will appear on Port 1.
The 87C749 is programmed by using a modified Quick-Pulse
Programming algorithm similar to that used for devices such as the
87C451 and 87C51. It differs from these devices in that a serial data
stream is used to place the 87C749 in the programming mode.
The next programming cycle may now be initiated by placing the
address information at the inputs of the multiplexed buffers, driving
the VPP pin to the VPP voltage level, providing the byte to be
programmed to Port1 and issuing the 26 programming pulses on the
PGM/ pin, bringing VPP back down to the VC level and verifying the
byte.
Figure 7 shows a block diagram of the programming configuration
for the 87C749. Port pin P0.2 is used as the programming voltage
supply input (VPP signal). Port pin P0.1 is used as the program
(PGM/) signal. This pin is used for the 25 programming pulses.
Port 3 is used as the address input for the byte to be programmed
and accepts both the high and low components of the eleven bit
address. Multiplexing of these address components is performed
using the ASEL input. The user should drive the ASEL input high
and then drive port 3 with the high order bits of the address. ASEL
should remain high for at least 13 clock cycles. ASEL may then be
driven low which latches the high order bits of the address internally.
The high address should remain on port 3 for at least two clock
cycles after ASEL is driven low. Port 3 may then be driven with the
low byte of the address. The low address will be internally stable 13
clock cycles later. The address will remain stable provided that the
low byte placed on port 3 is held stable and ASEL is kept low. Note:
ASEL needs to be pulsed high only to change the high byte of the
address.
Programming Modes
The 87C749 has four programming features incorporated within its
EPROM array. These include the USER EPROM for storage of the
application’s code, a 16-byte encryption key array and two security
bits. Programming and verification of these four elements are
selected by a combination of the serial data stream applied to the
RESET pin and the voltage levels applied to port pins P0.1 and
P0.2. The various combinations are shown in Table 3.
Encryption Key Table
The 87C749 includes a 16-byte EPROM array that is programmable
by the end user. The contents of this array can then be used to
encrypt the program memory contents during a program memory
verify operation. When a program memory verify operation is
performed, the contents of the program memory location is
XNOR’ed with one of the bytes in the 16-byte encryption table. The
resulting data pattern is then provided to port 1 as the verify data.
The encryption mechanism can be disable, in essence, by leaving
the bytes in the encryption table in their erased state (FFH) since
the XNOR product of a bit with a logical one will result in the original
bit. The encryption bytes are mapped with the code memory in
16-byte groups. the first byte in code memory will be encrypted with
the first byte in the encryption table; the second byte in code
memory will be encrypted with the second byte in the encryption
table and so forth up to and including the 16the byte. The encryption
repeats in 16-byte groups; the 17th byte in the code memory will be
encrypted with the first byte in the encryption table, and so forth.
Port 1 is used as a bidirectional data bus during programming and
verify operations. During programming mode, it accepts the byte to
be programmed. During verify mode, it provides the contents of the
EPROM location specified by the address which has been supplied
to Port 3.
The XTAL1 pin is the oscillator input and receives the master system
clock. This clock should be between 1.2 and 6MHz.
The RESET pin is used to accept the serial data stream that places
the 87C749 into various programming modes. This pattern consists
of a 10-bit code with the LSB sent first. Each bit is synchronized to
the clock input, X1.
Programming Operation
Figures 8 and 9 show the timing diagrams for the program/verify
cycle. RESET should initially be held high for at least two machine
cycles. P0.1 (PGM/) and P0.2 (VPP) will be at VOH as a result of the
RESET operation. At this point, these pins function as normal
quasi-bidirectional I/O ports and the programming equipment may
pull these lines low. However, prior to sending the 10-bit code on the
RESET pin, the programming equipment should drive these pins
high (VIH). The RESET pin may now be used as the serial data input
for the data stream which places the 87C749 in the programming
mode. Data bits are sampled during the clock high time and thus
should only change during the time that the clock is low. Following
transmission of the last data bit, the RESET pin should be held low.
Security Bits
Two security bits, security bit 1 and security bit 2, are provided to
limit access to the USER EPROM and encryption key arrays.
Security bit 1 is the program inhibit bit, and once programmed
performs the following functions:
1. Additional programming of the USER EPROM is inhibited.
2. Additional programming of the encryption key is inhibited.
3. Verification of the encryption key is inhibited.
4. Verification of the USER EPROM and the security bit levels may
still be performed.
Next the address information for the location to be programmed is
placed on port 3 and ASEL is used to perform the address
multiplexing, as previously described. At this time, port 1 functions
as an output.
(If the encryption key array is being used, this security bit should be
programmed by the user to prevent unauthorized parties from
reprogramming the encryption key to all logical zero bits. Such
programming would provide data during a verify cycle that is the
logical complement of the USER EPROM contents).
A high voltage VPP level is then applied to the VPP input (P0.2).
(This sets Port 1 as an input port). The data to be programmed into
the EPROM array is then placed on Port 1. This is followed by a
series of programming pulses applied to the PGM/ pin (P0.1). These
pulses are created by driving P0.1 low and then high. This pulse is
1998 Apr 23
83C749/87C749
Security bit 2, the verify inhibit bit, prevents verification of both the
USER EPROM array and the encryption key arrays. The security bit
levels may still be verified.
15
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
Verification occurs in a similar manner using the RESET serial
stream shown in Table 3. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
Programming and Verifying Security Bits
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 3. When
programming either security bit, it is not necessary to provide
address or data information to the 87C749 on ports 1 and 3.
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if not programmed. Likewise, P1.6
contains the security bit 2 data and is a logical one if programmed
and a logical zero if not programmed.
Table 3. Implementing Program/Verify Modes
OPERATION
Program user EPROM
Verify user EPROM
Program key EPROM
Verify key EPROM
Program security bit 1
Program security bit 2
Verify security bits
SERIAL CODE
P0.1 (PGM/)
P0.2 (VPP)
296H
296H
292H
292H
29AH
298H
29AH
–*
VIH
–*
VIH
–*
–*
VIH
VPP
VIH
VPP
VIH
VPP
VPP
VIH
NOTE:
* Pulsed from VIH to VIL and returned to VIH.
EPROM PROGRAMMING AND VERIFICATION
Tamb = 21°C to +27°C, VCC = 5V ±10%, VSS = 0V
PARAMETER
SYMBOL
1/tCLCL
tAVGL
1
Oscillator/clock frequency
Address setup to P0.1 (PROG–) low
MIN
MAX
UNIT
1.2
6
MHz
10µs + 24tCLCL
tGHAX
Address hold after P0.1 (PROG–) high
48tCLCL
tDVGL
Data setup to P0.1 (PROG–) low
38tCLCL
tDVGL
Data setup to P0.1 (PROG–) low
38tCLCL
tGHDX
Data hold after P0.1 (PROG–) high
36tCLCL
tSHGL
VPP setup to P0.1 (PROG–) low
10
tGHSL
VPP hold after P0.1 (PROG–)
10
tGLGH
P0.1 (PROG–) width
90
tAVQV
2
VPP low (VCC) to data valid
µs
110
µs
48tCLCL
tGHGL
P0.1 (PROG–) high to P0.1 (PROG–) low
tSYNL
P0.0 (sync pulse) low
4tCLCL
tSYNH
P0.0 (sync pulse) high
8tCLCL
tMASEL
ASEL high time
13tCLCL
tMAHLD
Address hold time
2tCLCL
tHASET
Address setup to ASEL
13tCLCL
10
tADSTA
Low address to address stable
13tCLCL
NOTES:
1. Address should be valid at least 24tCLCL before the rising edge of P0.2 (VPP).
2. For a pure verify mode, i.e., no program mode in between, tAVQV is 14tCLCL maximum.
1998 Apr 23
µs
16
µs
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
87C749
A0–A10
ADDRESS STROBE
P3.0–P3.7
VCC
P0.0/ASEL
VSS
PROGRAMMING
PULSES
P0.1
VPP/VIH VOLTAGE
SOURCE
P0.2
CLK SOURCE
+5V
P1.0–P1.7
DATA BUS
XTAL1
RESET
CONTROL
LOGIC
RESET
SU00309
Figure 7. Programming Configuration
XTAL1
MIN 2 MACHINE
CYCLES
RESET
TEN BIT SERIAL CODE
BIT 0
P0.2
UNDEFINED
P0.1
UNDEFINED
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
SU00302
Figure 8. Entry into Program/Verify Modes
12.75V
P0.2 (VPP)
5V
5V
tSHGL
tGHSL
25 PULSES
P0.1 (PGM)
tGLGH
tMASEL
tGHGL
98µs MIN
10µs MIN
P0.0 (ASEL)
tHASET
PORT 3
tHAHLD
HIGH ADDRESS
LOW ADDRESS
tADSTA
PORT 1
INVALID DATA
tDVGL
VALID DATA
tGHDX
DATA TO BE PROGRAMMED
VERIFY MODE
PROGRAM MODE
tAVQV
INVALID DATA
VALID DATA
VERIFY MODE
SU00310
Figure 9. Program/Verify Cycle
1998 Apr 23
17
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, PWM, low pin count
DIP28: plastic dual in-line package; 28 leads (600 mil); long body
1998 Apr 23
18
83C749/87C749
SOT117-2
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, PWM, low pin count
PLCC28: plastic leaded chip carrer; 28 leads; pedestal
1998 Apr 23
19
83C749/87C749
SOT261-3
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, PWM, low pin count
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm
1998 Apr 23
20
83C749/87C749
SOT341-1
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, PWM, low pin count
NOTES
1998 Apr 23
21
83C749/87C749
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, PWM, low pin count
83C749/87C749
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 05-98
Document order number:
1998 Apr 23
22
9397 750 03856