INTEGRATED CIRCUITS DATA SHEET 74ALVC573 Octal D-type transparent latch; 3-state Product specification Supersedes data of 2002 Mar 01 2003 Jun 25 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state FEATURES 74ALVC573 The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. • Wide supply voltage range from 1.65 to 3.6 V • Complies with JEDEC standards: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). The 74ALVC573 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. • 3.6 V tolerant inputs and outputs • CMOS low power consumption • Direct interface with TTL levels (2.7 to 3.6 V) • Power-down mode When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. • Latch-up performance exceeds 250 mA • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. DESCRIPTION The 74ALVC573 is functionally identical to the 74ALVC373, but the has a different pin arrangement. The 74ALVC573 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay input Dn to output Qn CI input capacitance CPD power dissipation capacitance per buffer CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ UNIT 2.5 ns VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.0 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.3 ns VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.2 ns 3.5 pF outputs enabled 37 pF outputs disabled 7 pF VCC = 3.3 V; notes and 1 Notes CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 1. The condition is VI = GND to VCC. 2003 Jun 25 TYPICAL 2 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 FUNCTION TABLE See note 1 INPUT OUTPUT OE LE Dn INTERNAL LATCH Enable and read register (transparent mode) L H L L L L H H H H Latch and read register L L l L L L L h H H H L l L Z H L h H Z OPERATING MODES Latch register and disable outputs Qn Note 1. H = HIGH voltage level; a) h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; b) L = LOW voltage level; c) l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; d) Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74ALVC573D −40 to +85 °C 20 SO20 plastic SOT163-1 74ALVC573PW −40 to +85 °C 20 TSSOP20 plastic SOT360-1 74ALVC573BQ −40 to +85 °C 20 DHVQFN20 plastic SOT764-1 PINNING PIN 1 SYMBOL OE PIN SYMBOL 11 LE output enable input (active LOW) latch enable input (active HIGH) 12 Q7 3-state latch output DESCRIPTION DESCRIPTION 2 D0 data input 13 Q6 3-state latch output 3 D1 data input 14 Q5 3-state latch output 4 D2 data input 15 Q4 3-state latch output 5 D3 data input 16 Q3 3-state latch output 6 D4 data input 17 Q2 3-state latch output 7 D5 data input 18 Q1 3-state latch output 8 D6 data input 19 Q0 3-state latch output 9 D7 data input 20 VCC supply voltage 10 GND ground (0 V) 2003 Jun 25 3 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 handbook, halfpage OE VCC 1 20 D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 handbook, halfpage OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 GND(1) 16 Q3 D3 5 573 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 LE D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 MNA806 Top view 10 11 GND LE MNA979 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO20 and TSSOP20. Fig.2 Pin configuration DHVQFN20. handbook, halfpage handbook, halfpage 1 1 2 3 4 5 6 7 8 9 OE D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 C1 EN1 19 19 18 2 17 3 18 4 17 5 16 13 6 15 12 7 14 8 13 9 12 16 1D 15 14 LE 11 11 MNA807 MNA808 Fig.3 Logic symbol. 2003 Jun 25 Fig.4 IEC logic symbol. 4 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 handbook, halfpage 2 D0 Q0 19 3 D1 Q1 18 4 D2 Q2 17 5 D3 6 D4 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 LATCH 1 to 8 LE handbook, halfpage Q3 16 3-STATE OUTPUTS Q4 15 LE LE D Q MNA692 LE 11 LE 1 OE MNA809 Fig.5 Function diagram. D0 D1 Fig.6 Logic diagram (one latch). D2 D3 D4 D5 D6 D7 handbook, full pagewidth D Q D Q D Q D Q D Q D Q D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MNA810 Fig.7 Logic diagram. 2003 Jun 25 5 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 1.65 3.6 V VI input voltage 0 3.6 V VO output voltage VCC V Tamb operating ambient temperature tr, tf input rise and fall times VCC = 1.65 to 3.6 V; enable mode 0 VCC = 1.65 to 3.6 V; disable mode 0 3.6 V VCC = 0 V; Power-down mode 0 3.6 V −40 +85 °C VCC = 1.65 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER VCC supply voltage IIK input diode current VI input voltage IOK output diode current VO output voltage CONDITIONS MIN. MAX. UNIT −0.5 +4.6 V − −50 mA −0.5 +4.6 V VO > VCC or VO < 0 − ±50 mA enable mode; notes 1 and 2 −0.5 VCC + 0.5 V disable mode −0.5 +4.6 V Power-down mode; note 2 −0.5 +4.6 V VO = 0 to VCC − ±50 mA VI < 0 IO output source or sink current ICC, IGND VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 500 mW Tamb = −40 to +85 °C; note 3 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. 3. For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. a) For TSSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. b) For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 2003 Jun 25 6 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP.(1) MAX. UNIT VCC (V) Tamb = −40 to +85°C VIH VIL VOL VOH 1.65 to 1.95 0.65 × VCC − − V 2.3 to 2.7 1.7 − − V 2.7 to 3.6 2 − − V 1.65 to 1.95 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V 2.7 to 3.6 − − 0.8 V IO = 100 µA 1.65 to 3.6 − − 0.2 V IO = 6 mA 1.65 − − 0.3 V IO = 12 mA 2.3 − − 0.4 V IO = 18 mA 2.3 − − 0.6 V IO = 12 mA 2.7 − − 0.4 V IO = 18 mA 3.0 − − 0.4 V IO = 24 mA 3.0 − − 0.55 V IO = −100 µA 1.65 to 3.6 VCC − 0.2 − − V IO = −6 mA 1.65 1.25 − − V IO = −12 mA 2.3 1.8 − − V IO = −18 mA 2.3 1.7 − − V IO = −12 mA 2.7 2.2 − − V IO = −18 mA 3.0 2.4 − − V IO = −24 mA 3.0 2.2 − − V HIGH-level input voltage LOW-level input voltage LOW-level output voltage HIGH-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = 3.6 V or GND 3.6 − ±0.1 ±5 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 3.6 V or GND; note 2 1.65 to 3.6 − 0.1 ±10 µA Ioff power OFF leakage current VI or VO = 0 to 3.6 V 0.0 − ±0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 − 0.2 10 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 0.6 V; IO = 0 3.0 to 3.6 − 5 750 µA Notes 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2. For transceivers, the parameter IOZ includes the input leakage current. 2003 Jun 25 7 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 AC CHARACTERISTICS TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; see note 1 tPHL/tPLH tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th propagation delay Dn to Qn propagation delay LE to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn LE pulse with HIGH set-up time Dn to LE hold time Dn to LE see Figs 8 and 12 see Figs 9 and 12 see Figs 10 and 12 see Figs 10 and 12 see Figs 9 and 12 see Figs 11 and 12 see Figs 11 and 12 Note 1. All typical values are measured at Tamb = 25 °C. 2003 Jun 25 8 1.65 to 1.95 1.0 2.5 5.4 ns 2.3 to 2.7 1.0 2.0 3.5 ns 2.7 1.0 2.3 3.6 ns 3.0 to 3.6 1.0 2.2 3.3 ns 1.65 to 1.95 1.0 2.8 6.0 ns 2.3 to 2.7 1.0 2.1 3.8 ns 2.7 1.0 2.4 3.7 ns 3.0 to 3.6 1.0 2.3 3.3 ns 1.65 to 1.95 1.5 3.0 6.4 ns 2.3 to 2.7 1.0 2.4 4.5 ns 2.7 1.5 3.0 4.6 ns 3.0 to 3.6 1.0 2.3 4.0 ns 1.65 to 1.95 1.5 3.4 7.0 ns 2.3 to 2.7 1.0 2.2 4.4 ns 2.7 1.5 2.8 4.4 ns 3.0 to 3.6 1.0 2.7 4.4 ns 1.65 to 1.95 3.8 − − ns 2.3 to 2.7 3.3 − − ns 2.7 3.3 − − ns 3.0 to 3.6 3.3 − − ns 1.65 to 1.95 0.8 − − ns 2.3 to 2.7 0.8 − − ns 2.7 0.8 − − ns 3.0 to 3.6 0.8 − − ns 1.65 to 1.95 0.8 − − ns 2.3 to 2.7 0.8 − − ns 2.7 0.8 − − ns 3.0 to 3.6 0.7 − − ns Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 AC WAVEFORMS handbook, halfpage VI VM Dn input GND tPLH tPHL VOH VM Qn output VOL MNA811 INPUT VCC VI VM tr = tf VCC ≤ 2.0 ns 0.5 × VCC 2.3 to 2.7 V VCC ≤ 2.0 ns 0.5 × VCC 2.7 V 2.7 V ≤ 2.5 ns 1.5 V 3.0 to 3.6 V 2.7 V ≤ 2.5 ns 1.5 V 1.65 to 1.95 V Fig.8 Input Dn to output Qn propagation delay times. 1/fmax handbook, full pagewidth VI LE input VM GND tW t PHL t PLH VOH VM Qn output VOL MNA812 INPUT VCC VM VI tr = tf 1.65 to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns Fig.9 Latch Enable (LE) input pulse width and latch enable input to output (Qn) propagation delays. 2003 Jun 25 9 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 VI handbook, full pagewidth OE input VM GND t PLZ t PZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY Qn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled MNA813 INPUT VCC VI tr = tf VM VX VY 1.65 to 1.95 V VCC ≤ 2.0 ns 0.5 × VCC VOL + 0.15 V VOH − 0.15 V 2.3 to 2.7 V VCC ≤ 2.0 ns 0.5 × VCC VOL + 0.15 V VOH − 0.15 V 2.7 V 2.7 V ≤ 2.5 ns 1.5 V VOL + 0.3 V VOH − 0.3 V 3.0 to 3.6 V 2.7 V ≤ 2.5 ns 1.5 V VOL + 0.3 V VOH − 0.3 V VOL and VOH are typical output voltage drop that occur with the output load. Fig.10 3-state enable and disable times. 2003 Jun 25 10 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 VI handbook, full pagewidth VM Dn input GND th th t su t su VI LE input VM GND MNA814 INPUT VCC VM VI tr = tf 1.65 to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.11 Data set-up and hold times for Dn input to LE input. VEXT handbook, full pagewidth VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL MNA616 VCC RL VEXT VI CL 1.65 to 1.95 V VCC 30 pF 1 kΩ open GND 2 × VCC 2.3 to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6V 3.0 to 3.6 V 2.7 V 50 pF 500 Ω open GND 6V tPLH/tPHL tPZH/tPHZ tPZL/tPLZ Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.12 Load circuitry for switching times. 2003 Jun 25 11 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.043 0.055 0.394 0.016 0.039 0.01 0.01 0.004 0.035 0.016 inches 0.1 Z (1) θ Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 2003 Jun 25 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 12 o 8 0o Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 2003 Jun 25 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 13 o Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 0.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- 2003 Jun 25 14 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 To overcome these problems the double-wave soldering method was specifically developed. SOLDERING Introduction to soldering surface mount packages If wave soldering is used the following conditions must be observed for optimal results: This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. • below 220 °C (SnPb process) or below 245 °C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. – for all BGA and SSOP-T packages – for packages with a thickness ≥ 2.5 mm Manual soldering – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. • below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2003 Jun 25 15 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA not suitable suitable(4) DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(5), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP REFLOW(2) suitable suitable suitable not recommended(5)(6) suitable not recommended(7) suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2003 Jun 25 16 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC573 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Jun 25 17 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state NOTES 2003 Jun 25 18 74ALVC573 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state NOTES 2003 Jun 25 19 74ALVC573 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/02/pp20 Date of release: 2003 Jun 25 Document order number: 9397 750 11268