INTEGRATED CIRCUITS DATA SHEET SAA7191B Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) Product specification File under Integrated Circuits, IC22 August 1996 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 8 LIMITING VALUES 9 CHARACTERISTICS 10 I2C-BUS FORMAT 11 PROGRAMMING EXAMPLE 12 PACKAGE OUTLINE 13 SOLDERING 14 DEFINITIONS 15 LIFE SUPPORT APPLICATIONS 16 PURCHASE OF PHILIPS I2C COMPONENTS August 1996 2 SAA7191B Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) 1 SAA7191B 2 FEATURES • Separate 8-bit luminance (Y or CVBS) and 8-bit chrominance inputs (CVBS or C) from CVBS, Y/C, S-Video (S-VHS or Hi8) sources GENERAL DESCRIPTION The SAA7191B is a digital multistandard colour decoder suitable for 8-bit CVBS input signals or for 8-bit luminance and 8-bit chrominance input signals (Y/C). • Luminance and chrominance signal processing for standards PAL-B/G, NTSC-M, SECAM The SAA7191B is down-compatible with SAA7191. The SAA7191B has additional outputs RTCO, GPSW0 and ODD. These new outputs are in high-impedance state when NFEN-bit = 0. • Horizontal and vertical sync detection for all standards • Real-time control output RTCO to be used for frequency-locked digital video encoder (SAA7199B). RTCO contains serialized information about actual clock frequency, subcarrier frequency and PAL/SECAM sequence. • Controls via the I2C-bus • User programmable aperture correction (horizontal peaking) • Compatible with memory-based features (line-locked clock) • Cross-colour reduction by chrominance comb-filtering (NTSC) or by special cross colour cancellation (SECAM) • 8-bit quantization of input signals • 768/640 active samples per line equals 50/60 Hz (SQP) • The YUV bus supports data rates of 780 × fH equal to 12.2727 MHz for 60 Hz (NTSC-M) and 944 × fH equal to 14.75 MHz for 50 Hz (PAL-B/G, SECAM) in 4 : 1 : 1 or 4 : 2 : 2 formats (via the I2C-bus) • One crystal oscillator of 26.8 MHz 3 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. VDD positive supply voltage (pins 5, 18, 28, 37 and 52) IDD total supply current (pins 5, 18, 28, 37 and 52) VIL input levels TTL-compatible VOL output levels TTL-compatible Tamb operating ambient temperature 4 4.5 0 5 5.5 V 100 250 mA - °C 70 ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER SAA7191B August 1996 PINS 68 PIN POSITION PLCC MATERIAL plastic 3 UNIT CODE SOT188-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... VDD1 to VDD4 VSS1 to VSS4 5, 18. 28, 52 19, 38, 51, 67 RTCO 66 internally connected 68 test pins 44 1, 2 SAA7191B CVBS7 to CVBS0 14 to 17 20 to 23 45 to 50, 53, 54 CHROMINANCE PROCESSOR 55 to 62 4 INPUT INTERFACE CHR7 to CHR0 GPSW0 OUTPUT INTERFACE Y output (Y7 to Y0) UV output (UV7 to UV0) 42 6 to 13 LUMINANCE PROCESSOR GPSW1 24 GPSW2 25 HREF 63 FEON 64 65 PORT AND STATUS REGISTER 37 clock FEIN +5 V status 35 SDA 41 33 CLOCK SYNCHRONIZATION CONTROL XTAL XTALI 34 43 3 26 29 30 31 32 36 39 4 27 VS HS HL LFCO ODD CREF LLC MEH435 Fig.1 Block Blockdiagram. diagram. Fig.1 Product specification HSY RESN SAA7191B IICSA HCL VDDA VSSA 40 I 2 C-BUS Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) BLOCK DIAGRAM PLIN Philips Semiconductors 5 handbook, full pagewidth August 1996 +5 V Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) 6 SAA7191B PINNING SYMBOL PIN DESCRIPTION SP 1 connected to ground (shift pin for testing) AP 2 connected to ground (action pin for testing) RESN 3 reset, active LOW CREF 4 clock reference, sync from external to ensure in-phase signals on the YUV-bus VDD1 5 +5 V supply input 1 CHR0 6 CHR1 7 CHR2 8 CHR3 9 CHR4 10 CHR5 11 CHR6 12 CHR7 13 CVBS0 14 CVBS1 15 CVBS2 16 chrominance input data bits CHR7 to CHR0 from a Y/C (VHS, Hi8) source in two’s complement format luminance respectively CVBS lower input data bits CVBS3 to CVBS0 (CVBS with luminance, chrominance and all sync information in two’s complement format) CVBS3 17 VDD2 18 +5 V supply input 2 VSS1 19 ground 1 (0 V) CVBS4 20 CVBS5 21 CVBS6 22 CVBS7 23 GPSW1 24 Port 1 output for general purpose (programmable) GPSW2 25 Port 2 output for general purpose (programmable) HCL 26 black level clamp pulse (programmable), e.g. for TDA8708 (ADC) LLC 27 line-locked clock input signal (29.5 MHz for 50 Hz system; 24.5454 MHz for 60 Hz system) VDD3 28 +5 V supply input 3 HSY 29 horizontal sync indicator output signal (programmable), e.g. for TDA8708 (ADC) luminance respectively CVBS upper input data bits CVBS7 to CVBS4 (CVBS with luminance, chrominance and all sync information in two’s complement format) VS 30 vertical sync output signal HS 31 horizontal sync output signal (programmable) HL 32 horizontal lock flag, HIGH = PLL locked XTAL 33 26.8 MHz clock output XTALI 34 26.8 MHz connection for crystal or external oscillator (TTL compatible squarewave) VSSA 35 analog ground LFCO 36 line frequency control output signal, multiple of horizontal frequency (7.375 MHz/6.136363 MHz) VDDA 37 +5 V supply input for analog part VSS2 38 ground 2 (0 V) ODD 39 odd/even field identification output (odd = HIGH); active only at NFEN-bit = 1 SDA 40 I2C-bus data line August 1996 5 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SYMBOL SAA7191B PIN DESCRIPTION SCL 41 I2C-bus HREF 42 horizontal reference output for valid YUV data (for active line 768Y or 640Y samples long) IICSA 43 set module address input (LOW = 1000 101X; HIGH = 1000 111X) i.c. 44 internally connected Y7 45 Y6 46 Y5 47 Y4 48 Y3 49 Y2 50 VSS3 51 ground 3 (0 V) VDD4 52 +5 V supply input 4 Y1 53 Y0 54 UV7 55 UV6 56 UV5 57 UV4 58 UV3 59 UV2 60 UV1 61 UV0 62 FEON 63 output active flag (active LOW when Y and UV data in high-impedance state) FEIN 64 fast enable input (active LOW to control fast switching due to YUV data) clock line Y signal output bits Y7 to Y2 (luminance), part of the digital YUV-bus Y signal output bits Y1 to Y0 (luminance), part of the digital YUV-bus UV signal output bits UV7 to UV0 (colour-difference), part of the digital YUV-bus GPSW0 65 Port 0 output for general purpose (programmable); active only at NFEN-bit = 1 PLIN 66 PAL flag (active LOW at inverted line); SECAM flag (LOW equals DR, HIGH equals DB line) VSS4 67 ground 4 (0 V) RTCO 68 real-time control output active at NFEN-bit = 1; Fig.8 August 1996 6 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) 6.1 SAA7191B Pin configuration UV2 UV3 UV4 UV5 UV6 UV7 Y0 Y1 V DD4 V SS3 Y2 Y3 Y4 Y5 Y6 Y7 i.c. handbook, full pagewidth 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 UV1 61 43 IICSA UV0 62 42 HREF FEON 63 41 SCL FEIN 64 40 SDA GPSW0 65 39 ODD PLIN 66 38 V SS2 V SS4 67 37 V DDA RTCO 68 36 LFCO SAA7191B 35 V SSA CHR1 7 29 HSY CHR2 8 28 V DD3 CHR3 9 27 LLC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 HCL 30 VS GPSW2 6 GPSW1 CHR0 CVBS7 31 HS CVBS6 5 CVBS5 V DD1 CVBS4 32 HL V SS1 4 V DD2 CREF CVBS3 33 XTAL CVBS2 3 CVBS1 RESN CVBS0 34 XTALI CHR7 2 CHR6 AP CHR5 1 CHR4 SP Fig.2 Pin configuration. August 1996 7 MEH436 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) 7 7.1 SAA7191B FUNCTIONAL DESCRIPTION Chrominance processor The 8-bit chrominance input signal (CVBS or chrominance format) passes a bandpass filter to eliminate DC components and to decimate the sample rate before it is fed to the two multipliers (quadrature demodulator), Fig.3. Two subcarrier signals from a local oscillator (0 to 90 degree) are fed to the multiplicator inputs of the multipliers. The multipliers operate as a quadrature demodulator for all PAL and NTSC signals; it operates as a frequency down-mixer for SECAM signals. The two multiplier output signals are converted to a serial data stream and applied to three low-pass filter stages, then to a gain controlled amplifier. A final multiplexed low-pass filter achieves, together with the preceding stages, the required bandwidth performance. The signals, originated from PAL and NTSC, are applied to a comb-filter. The signals, originated from SECAM, are fed through a Cloche filter (0 Hz centre frequency), a phase demodulator and a differentiator to obtain frequency-demodulated colour-difference signals.The SECAM signals are fed after de-emphasis to a cross-over switch, to provide the both serial-transmitted colour-difference signals. These signals are fed finally to the output formatter stages and to the output interface. August 1996 8 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... CHROMINANCE BANDPASS QUADRATURE DEMODULATOR CHR (7-0) GAIN CONTROLLED AMPLIFIER LOWPASS FILTER QUAM COMB FILTERS AND SECAM RECOMBINATION LOWPASS FILTER OUTPUT FORMATTER AND OUTPUT INTERFACE RTCO CHRS HUEC FISE SECS NFEN DISCRETE TIME OSCILLATOR (DTO1) AND DIVIDER 68 LOOP FILTER PI1 FISE FEON FEIN SECS HRMV CKTS (4-0) CHCV (7-0) CKTO (4-0) LFIS (1-0) SECS LOOP FILTER PI2 9 BURST GATE ACCUMULATOR PLIN 64 HREF Y (7-0) CODE BYPS 63 OFTS COLO OEDY OEDC OEHS CLOCHE FILTER PHASE DEMODULATOR AND AMPLITUDE DETECTOR Philips Semiconductors INPUT INTERFACE UV (7-0) 42 Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) handbook, full pagewidth August 1996 CVBS (7-0) SEQUENCE PROCESSOR 66 DIFFERENTIATOR SAA7191B PLSE(7-0) SESE(7-0) FISE SECS SEQA SXCR CHROMINANCE DE-EMPHASIS MEH437 Fig.3 Detailed block diagram; continued in Fig.4. Fig.3(a) Detailed block diagram; continued in Fig.3(b). Product specification from luminance SAA7191B to luminance This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... handbook, full pagewidth SAMPLE RATE CONVERTER CHROMINANCE TRAP PREFILTER PREF VARIABLE BANDPASS FILTER BPSS (1-0) BYPS FISE WEIGHTING AND ADDING STAGE CORING PREF BYPS CORI (1-0) VARIABLE DELAY COMPENSATION APER (0-1) YDEL (2-0) MATCHING AMPLIFIER LUMINANCE FISE internal clocks 4 PREFILTER SYNC SYNC SLICER PHASE DETECTOR FINE PHASE DETECTOR COARSE PROGRAMMABLE DELAY LINE-LOCKED CLOCK GENERATOR HLCK VTRC HPLL FISE DISCRETE TIME OSCILLATOR (DTO2) CRYSTAL CLOCK GENERATOR 27 CREF LLC 10 LOOP FILTER HRMV SCEN OEVS OEHS FISE SAA7191B RESN 3 SCL 41 SDA 40 IICSA 43 VTRC FISE HCLB (7-0) HCLS (7-0) HSYB (7-0) HSYS (7-0) HPHI (7-0) IDEL (7-0) HLCK STTC SYNC VERTICAL PROCESSOR COUNTER NFEN 34 XTAL XTAL I 29 HCL HSY 30 VS 31 HS 32 HL 39 ODD DAC FIDT VNOI (1-0) HLCK VTRC FSEL AUFD NFEN 36 LFCO Fig.4 Detailed block diagram; continued from Fig.3. Fig.3(b) Detailed block diagram; continued from Fig.3(a). MEH438-1 Product specification 26 FISE SAA7191B GPSW(2-0) 33 FISE I2C-BUS CONTROL 65,24,25 Philips Semiconductors to output interface Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) August 1996 from input interface Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) 7.2 Table 1 Luminance processor The luminance input signal, a digital CVBS format or an 8-bit luminance format (S-VHS, Hi8), is fed through a sample rate converter to reduce the data rate to 14.75 MHz for PAL and SECAM (12.2727 MHz for NTSC), Fig.4. 60 Hz 29.5 24.545454 LLC2 14.75 12.272727 LLC4 7.375 6.136136 LLC8 3.6875 3.068181 Line locked clock frequency LFCO is required in an external PLL (SAA7197) to generate the line locked clock frequency. 7.6 YUV-bus, digital outputs The 16-bit YUV-bus transfers digital data from the output interfaces to a feature box, or to the digital-to-analog converter (DAC). Outputs are controlled via the I2C-bus in normal selections, or they are controlled by output enable chain (FEIN on pin 64, Fig.5). The YUV-bus data rate equals LLC2 in Table 1. Timing is achieved by marking each second positive rising edge of the clock LLC in conjunction with CREF (clock reference). YUV-bus formats 4:2:2 and 4:1:1 The output signals Y7 to Y0 are the bits of the digital luminance signal. The output signals UV7 to UV0 are the bits of the multiplexed colour-difference signals (B−Y) and (R−Y). The frame in the following tables is the time, required to transfer a full set of samples. In case of 4 : 2 : 2 format two luminance samples are transmitted in comparison to one U and one V sample within one frame. Processing delay Synchronization The luminance output signal is fed to the synchronization stage. Its bandwidth is reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors to be compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Adjustable output signals (e. g. HCL and HSY) are generated according to peripheral requirements (TDA8708A, TDA8709A). The output signals HS, VS and PLIN are locked to the timing reference signal HREF (Figures 7 and 8). There is no absolute timing reference guaranteed between the input signal and the HREF signal as further improvements to the circuit may change the total processing delay. It is therefore not recommended to use them for applications, which ask for absolute timing accuracy to the input signals. The loop filter signal drives an oscillator to generate the line frequency control output signal LFCO. August 1996 50 Hz LLC 7.5 The delay from input to output is 220 LLC cycles if YDEL is set to 0. The processing delay will be influenced in future enhancements. 7.4 Clock frequencies in MHz for 50/60 Hz systems CLOCK Sample rate is converted by means of a switchable pre-filter. High frequency components are emphasized to compensate for loss in the following chrominance trap filter. This chrominance trap filter (fo = 4.43 MHz or fo = 3.58 MHz centre frequency selectable) eliminates most of the colour carrier signal, therefore, it must be by-passed for S-Video (S-VHS and Hi8) signals. The high frequency components of the luminance signal can be “peaked” (control for sharpness improvement via the I2C-bus) in two bandpass filters with selectable transfer characteristic. A coring circuit with selectable characteristic improves the signal once more, this signal is then added to the original (“unpeaked”) signal. A switchable amplifier achieves a common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed to the variable delay compensation. 7.3 SAA7191B 11 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) Table 2 4 : 2 : 2 format (768 pixels per line for 50 Hz system; 640 pixels per line for 60 Hz system) OUTPUT PIXEL BYTE SEQUENCE Y0 (LSB) Y1 Y2 Y3 Y4 Y5 Y6 Y7 (MSB) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 UV0 (LSB) UV1 UV2 UV3 UV4 UV5 UV6 UV7(MSB) U0 U1 U2 U3 U4 U5 U6 U7 V0 V1 V2 V3 V4 V5 V6 V7 U0 U1 U2 U3 U4 U5 U6 U7 V0 V1 V2 V3 V4 V5 V6 V7 U0 U1 U2 U3 U4 U5 U6 U7 V0 V1 V2 V3 V4 V5 V6 V7 Y frame 0 1 2 3 4 5 UV frame 0 2 4 Notes 1. Data rate: LLC2 2. Sample frequency: Y LLC2 U LLC4 V LLC4 The quoted frequencies are valid on the YUV-bus. The time frames are controlled by the HREF signal. August 1996 12 SAA7191B Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) Table 3 SAA7191B 4 : 1 : 1 format (768 pixels per line for 50 Hz system and 640 pixels per line for 60 Hz system) OUTPUT PIXEL BYTE SEQUENCE Y0 (LSB) Y1 Y2 Y3 Y4 Y5 Y6 Y7 (MSB) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 UV0 (LSB) UV1 UV2 UV3 UV4 UV5 UV6 UV7 (MSB) 0 0 0 0 V6 V7 U6 U7 0 0 0 0 V4 V5 U4 U5 0 0 0 0 V2 V3 U2 U3 0 0 0 0 V0 V1 U0 U1 0 0 0 0 V6 V7 U6 U7 0 0 0 0 V4 V5 U4 U5 0 0 0 0 V2 V3 U2 U3 0 0 0 0 V0 V1 U0 U1 Y frame 0 1 2 3 4 5 6 7 UV frame 0 4 Notes 1. Data rate: sample frequency: Y U V LLC2 LLC2 LLC8 LLC8 Fast enable is achieved by setting input FEIN to LOW. This signal is used to control fast switching on the digital YUV-bus. HIGH on this pin forces the Y and U/V outputs to a high-impedance state. The signal FEON is LOW when the Y and U/V outputs are in this high-impedance state (Fig.5). The quoted frequencies are valid on the YUV-bus. The time frames are controlled by the HREF signal. Table 4 OEDY X 0 0 1 1 Digital output control OEDC X 0 1 0 1 August 1996 FEIN 0 1 1 1 X Y(7:0) active Z Z active active UV(7:0) active Z active Z active FEON 1 0 1 1 1 13 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B handbook, full pagewidth LLC to 3-state from 3-state CREF HREF tSU tHD FEIN t OH t OS YUV FEON MEH441-1 Fig.5 Timing example of fast enable input FEIN. August 1996 14 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B handbook, full LLC pagewidth CREF internal bus clock HREF start of active line Byte numbers for pixels: 0 1 2 3 4 5 6 7 U and V signal U0 V0 U2 V2 U4 V4 U6 V6 Y signal 0 1 2 3 4 5 6 7 U0 V0 U2 V2 U4 V4 U6 V6 Y signal 50 Hz 60 Hz U and V signal MEH233-2 handbook, full pagewidth LLC CREF HREF end of active line Byte number for pixels: Y signal 762 763 764 765 766 767 U762 V762 U764 V764 U766 V766 634 635 636 637 638 639 U634 V634 U636 V636 U638 V638 50 Hz U and V signal Y signal 60 Hz U and V signal MEH234-3 Fig.6 Line control by HREF in 4:2:2 format for 50 Hz and 60 Hz systems. August 1996 15 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) handbook, full pagewidth (a) 1st field 625 1 2 3 SAA7191B 4 5 6 7 8 9 input CVBS HREF 541 x 2/LLC VS ODD 2 x 2/LLC 313 (b) 2nd field 314 315 316 317 318 319 320 321 input CVBS HREF 69 x 2/LLC VS 2 x 2/LLC ODD 50 Hz handbook, full pagewidth (a) 1st field 525 1 2 3 MEH224-1 4 5 6 7 8 9 input CVBS HREF 449x 2/LLC VS ODD (b) 2nd field 2 x 2/LLC 263 264 265 266 267 268 269 270 271 input CVBS HREF 59 x 2/LLC VS 2 x 2/LLC ODD 60 Hz Fig.7 Vertical timing diagram for 50 / 60 Hz. August 1996 16 MEH225-1 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) handbook, full pagewidth H/L transition (counter start) SAA7191B 4 bits reserve HPLL increment bits 13 to 0 128 clocks 13 0 bit 22 14 19 20 15 3 bits sequence bit (1) reserve FSCPLL increment bits 21 to 0 10 reserved (2) 1 0 5 RTCO 4 0 (1)Sequence bit: SECAM: 0 equals DB-line 1 equals DR-line PAL: 0 equals (R-Y) line normal 1 equals (R-Y) line inverted NTSC: 0 (no change) 8 63 time slot (LLC/4) valid 67 not valid MEH442 (2) Reserve bits: 276 for 50 Hz systems; 188 for 60 Hz systems Fig.8 RTCO timing. 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); ground pins 19, 35, 38, 51 and 67 as well as supply pins 5, 18, 28, 37 and 52 connected together. SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage (pins 5, 18, 28, 37, 52) −0.5 7.0 V Vdiff GND difference voltage VSS A − VSS (1 to 4) − ±100 mV VI voltage on all inputs −0.5 VDD+0.5 V VO voltage on all outputs (IO max = 20 mA) −0.5 VDD+0.5 V Ptot total power dissipation − 2.5 W Tstg storage temperature range −65 150 °C Tamb operating ambient temperature range 0 70 °C VESD electrostatic handling(1) for all pins − ±2000 V Note 1. Equivalent to discharging a 100 pF capacitor through an 1.5 kΩ series resistor. August 1996 17 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B 9 CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = 0 to 70 °C unless otherwise specified. SYMBOL PARAMETER VDD supply voltage range (pins 5, 18, 28, 37, 52) IDD total supply current (pins 5, 18, 28, 37, 52) CONDITIONS MIN. 4.5 VDD = 5 V; inputs LOW; − outputs not connected TYP. MAX. UNIT 5 5.5 V 100 250 mA V I2C-bus, SDA and SCL (pins 40 and 41) VIL input voltage LOW −0.5 − 1.5 VIH input voltage HIGH 3 − VDD+0.5 V I40,41 input current − − ±10 µA IACK output current on pin 40 acknowledge 3 − - mA VOL output voltage at acknowledge I40 = 3 mA − − 0.4 V Data clock and control inputs (pins 3, 4, 6 to 17, 20 to 23, 27, 34, 43 and 64), Fig.11 VIL VIH LLC input voltage LOW (pin 27) LLC input voltage HIGH −0.5 2.4 − − 0.6 V VDD+0.5 V VIL VIH other input voltage LOW other input voltage HIGH −0.5 2.0 − − 0.8 V VDD+0.5 V ILI input leakage current − − 10 µA CI input capacitance data inputs; note 1 I/O high-ohmic clock inputs − − − − − − 8 8 10 pF pF pF tSU.DAT input data set-up time Fig.9 tHD.DAT input data hold time 11 − − ns 3 − − ns 1.4 − 2.6 V 1 − VDD V LFCO output (pin 36) Vo output signal (peak-to-peak value) V36 output voltage range note 2 YUV-bus, HREF and VS outputs (pins 30, 42, 45 to 50 and pins 53 to 62) Figures 10 and 15 to 25 VOL output voltage LOW 0 − 0.6 V VOH output voltage HIGH 2.4 − VDD V CL load capacitance 15 − 50 pF 0 − 0.6 V notes 1 and 2 Control outputs (pins 24 to 26, 29, 31, 32, 39, 63, 65, 66 and 68); Fig.12 VOL output voltage LOW VOH output voltage HIGH 2.4 − VDD V CL load capacitance 7.5 − 25 pF August 1996 notes 1 and 2 18 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SYMBOL PARAMETER Timing of YUV-bus and control outputs tOH output signal hold time SAA7191B CONDITIONS MIN. TYP. MAX. UNIT Fig.8 YUV, HREF, VS at CL = 15 pF 13 − − ns controls at CL = 7.5 pF 13 − − ns YUV, HREF, VS at CL = 50 pF; 14 − − ns tOS output set-up time controls at CL = 25 pF 14 − − ns tSZ data output disable transition time to 3-state condition 16 − − ns tZS data output enable transition time from 3-state condition 14 − − ns tRTCO RTCO timing Fig.8 Chrominance PLL fC catching range Crystal oscillator ±400 − − Hz − 26.8 − MHz Fig.10 fn nominal frequency ∆f / fn permissible deviation fn − − ±50 10−6 temperature deviation from fn − − ±20 10−6 temperature range Tamb 0 − 70 °C load capacitance CL 8 − − pF series resonance resistance RS − 50 80 Ω motional capacitance C1 − 1.1±20% − fF parallel capacitance C0 − 3.5±20% − pF X1 3rd harmonic crystal specification: Philips catalogue number 9922 520 30004 Line locked clock input LLC (pin 27) Fig.9 tLLC cycle time note 3 tp duty factor tLLCH / tLLC 40 − 60 % tr rise time − − 5 ns tf fall time − − 6 ns 31 − 45 ns Notes 1. Data output signals are Y7 to Y0 and UV7 to UV0. All others are control output signals. 2. Levels are measured with load circuit. YUV-bus, HREF and VS outputs with 1.2 kΩ in parallel to 50 pF at 3 V (TTL load); LFCO output with 10 kΩ in parallel to 15 pF and other outputs with 1.2 kΩ in parallel to 25 pF at 3 V (TTL load). 3. tSU, tHD, tOH and tOD include tr and tf. August 1996 19 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B t LLC handbook, full pagewidth t LLC H 2.4 V clock input LLC 1.5 V 0.6 V t SU tf t HD tr not valid 2.0 V input data 0.8 V 2.0 V input CREF 0.8 V t ZS t OS t SU t OH t HD not valid 2.4 V output data 0.6 V t SZ t SU t HD 2.4 V input FEIN 0.6 V MEH231-1 Fig.9 Data input and output timing diagram. handbook, full pagewidth 26.8 MHz (3rd harmonic) XTAL 10 pF X1 10 µH ± 20 % 33 SAA7191B XTALI 1 nF XTAL 33 (1) 10 pF SAA7191B XTALI 34 34 (1) (1) value depends on crystal parameters (a) (b) MEH439 Fig.10 Oscillator application (a) and optional clock from external source (b). August 1996 20 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) handbook, full pagewidth SAA7191B +127 +106 +95 +127 reserved +76 luminance NTSC luminance PAL, SECAM chrominance PAL and SECAM 0 -52 -64 chrominance input range (red, cyan 75 %) chrominance NTSC 0 blanking level -76 -91 -103 sync -128 -132 -128 (a) CVBS7 to CVBS0 input signal range. +255 (b) CHR7 to CHR0 input signal range. +255 +235 +255 white 100 % +212 blue 75 % +212 red 75 % luminance output range +128 +128 +128 U-component output range +44 +16 V-component output range yellow 75 % +44 cyan 75 % black 0 0 (c) Y output signal range. 0 (d) U output signal range (B-Y). (e) V output signal range (R-Y). MEH254-1 1. All levels are related to EBU colour bar. 2. Values in decimal at 100% luminance and 75% chrominance amplitude. Fig.11 Input and output signal ranges. August 1996 21 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) handbook, full pagewidth SAA7191B 62 x 2/LLC burst CVBS HSY HSY programming + 191 range (step size: 2/LLC) – 64 0 HCL HCL programming + 127 range (step size: 2/LLC) – 128 0 220 LLC 10 x 2/LLC processing delay CVBS - YUV at YDEL = 000 b Y-output HREF (50 Hz) 768 x 2/LLC 176 x 2/LLC PLIN (50 Hz ) 38 x 2/LLC 100 x 2/LLC HS (50 Hz) 64 x 2/LLC HS (50 Hz) programming range (step size: 8/LLC) + 117 – 118 0 38 x 2/LLC HREF (60 Hz) 640 x 2/LLC 140 x 2/LLC HS (60 Hz) 64 x 2/LLC HS (60 Hz) programming range (step size: 8/LLC) + 97 – 97 0 MEH226-2 Fig.12 Horizontal sync at HRMV = 0 and HRFS = 0 for 50/60 Hz (signals HSY, HCL, HREF and PLIN). August 1996 22 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... + 75 Ω chrominance Vi , source 2 75 Ω + + Y or CVBS Vi , source 1 75 Ω 16 17 13 12 1 µF + Y or CVBS Vi , source 2 75 Ω 18 11 19 10 20 9 680 Ω 680 Ω 14 1 µF 17 12 18 11 19 10 20 9 21 8 + 21 23 VDDA 2.2 k Ω CVBS2 VDDA 23 VDDO 6 VDDD 24 5 + 10 µF HSY 10 Ω 25 4 26 3 27 2 28 1 22 7 23 6 24 5 25 4 26 3 27 2 28 1 0.1 µF 0.1 µF 7 0.22 µF TDA8709A 0.1 µF CVBS3 8 TDA8708A 22 CHR0 CHR1 CHR2 CHR3 1 µF CVBS1 1 µF 0.1 µF CHR7 to CHR0 CVBS0 + 15 HCL 13 1 µF digital 5.6 Ω 16 1 µF chrominance Vi , source 1 2.2 k Ω 14 4.7 k Ω analog 68 pF CLK 2.7 k Ω 18 Ω CVBS4 CVBS3 0.1 µF 0.1 µF 120 Ω 5.6 Ω 5.6 Ω VDDO 0.1 µF VDDD 0.1 µF CLK 68 pF CHR4 CHR5 Philips Semiconductors digital 15 Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) full pagewidth August 1996 signal source selected by GPSW1-bit (LOW = source 1) CHR6 CHR7 1 kΩ CVBS2 CVBS7 to CVBS0 CVBS7 analog 5.6 Ω 120 Ω 18 Ω LLCA MEH443 Fig.13 Application circuit for analog-to-digital conversions. SAA7191B +5 V (digital supply) Product specification +5 V (analog supply) Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B VSS horizontal lock flag i.c. HL 0.1 µ F 5 67 51 38 19 44 32 0.1 µ F 18 0.1 µ F 28 0.1 µ F 52 digital VDD +5 V chrominance CHR7 to CHR0 CHR0 CHR1 CHR2 CHR3 CHR4 CHR5 CHR6 CHR7 luminance CVBS7 to CVBS0 L0 L1 L2 L3 L4 L5 L6 handbook, full pagewidth XTAL: Philips 9922 520 30004 L7 6 7 8 9 10 11 12 13 14 15 16 17 20 21 22 23 26.8 MHz 10 pF 1 nF UV4 YUV-bus UV5 UV6 UV7 Y7 to Y0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 ODD HS VS HSY HCL 64 IICSA 43 2 1 34 10 µH UV3 HREF SCL SDA I 2 C-bus RTCO GPSW0 FEIN reset 10 pF UV2 42 41 40 68 65 63 FEON 33 X1 UV1 54 53 50 49 48 47 46 45 39 31 30 29 26 SAA7191B UV7 to UV0 UV0 62 61 60 59 58 57 56 55 3 27 4 digital VSSA 24 25 36 35 VDDA 37 66 +5 V PLIN digital 0.1 µ F LFCO 2.2 µH VDD analog +5 V 11 19 16 S2 RESN LLCA CREF LLCB LLC2A LLC2B 12 7 15 10 14 20 SAA7197 S1 5 2 3 4 8 17 1 6 9 13 18 + 0.1 µ F 10 µ F 0.1 µ F analog VDD digital 0.1 µ F 0.1 µ F digital MEH440-1 Fig.14 Application circuit for digital multistandard colour decoder. August 1996 24 +5 V Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B 10 I2C-BUS FORMAT S SLAVE ADDRESS S = A SUBADDRESS A DATA0 A DATAn A P start condition SLAVE ADDRESS = 1000 101X (IICSA = LOW) or 1000 111X (IICSA = HIGH) A = acknowledge, generated by the slave SUBADDRESS(1) = subaddress byte (Table 5) DATA = data byte (Table 5) P = stop condition X = read/write control bit X = 0, order to write (the circuit is slave receiver) X = 1, order to read (the circuit is slave transmitter) Note 1. If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed. Table 5 I2C-bus; DATA for status byte (X = 1 in address byte; 8Bh at IICSA = LOW or 8Fh at IICSA = HIGH). DATA FUNCTION status byte D7 D6 D5 STTC HLCK FIDT D4 X D3 X D2 X D1 X D0 CODE Function of the bits: STTC Horizontal time constant information for future application with logical combfilter only: 0 = TV time constant (slow); 1 = VCR time constant (fast) HLCK Horizontal PLL information: FIDT Field information: 0 = 50 Hz system detected; 1 = 60 Hz system detected CODE Colour information: 0 = no colour detected; 1 = colour detected August 1996 0 = HPLL locked; 1 = HPLL unlocked 25 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) Table 6 SAA7191B I2C-bus; subaddress and data bytes for writing (X = 0 in address byte; 8Ah at IICSA = LOW or 8Eh at IICSA = HIGH). DATA FUNCTION SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Increment delay H sync begin, 50 Hz H sync stop, 50 Hz 00 01 02 IDEL7 IDEL6 IDEL5 HSYB7 HSYB6 HSYB5 HSYS7 HSYS6 HSYS5 IDEL4 HSYB4 HSYS4 IDEL3 HSYB3 HSYS3 IDEL2 HSYB2 HSYS2 IDEL1 HSYB1 HSYS1 IDEL0 HSYB0 HSYS0 H clamp begin, 50 Hz H clamp stop, 50 Hz H sync after PHI1, 50 Hz 03 04 05 HCLB7 HCLB6 HCLB5 HCLS7 HCLS6 HCLS5 HPHI7 HPHI6 HPHI5 HCLB4 HCLS4 HPHI4 HCLB3 HCLS3 HPHI3 HCLB2 HCLS2 HPHI2 HCLB1 HCLS1 HPHI1 HCLB0 HCLS0 HPHI0 Luminance control Hue control Colour killer threshold QAM 06 07 08 BYPS PREF BPSS1 HUEC7 HUEC6 HUEC5 CKTQ4 CKTQ3 CKTQ2 BPSS0 HUEC4 CKTQ1 CORI1 HUEC3 CKTQ0 CORI0 APER1 HUEC2 HUEC1 0 0 APER0 HUEC0 0 Colour-killer threshold SECAM 09 PAL switch sensitivity 0A SECAM switch sensitivity 0B CKTS4 CKTS3 CKTS2 PLSE7 PLSE6 PLSE5 SESE7 SESE6 SESE5 CKTS1 PLSE4 SESE4 CKTS0 PLSE3 SESE3 0 PLSE2 SESE2 0 PLSE1 SESE1 0 PLSE0 SESE0 Chroma gain control settings Standard/mode control I/O and clock control 0C 0D 0E COLO VTRC HPLL 0 0 OEVS 0 NFEN OEDY 0 HRMV CHRS 0 0 GPSW0 SECS GPSW2 GPSW1 Control #1 Control #2 Chroma gain reference 0F 10 11 AUFD FSEL SXCR 0 0 0 CHCV7 CHCV6 CHCV5 SCEN 0 CHCV4 OFTS 0 CHCV3 YDEL2 YDEL1 HRFS VNOI1 CHCV2 CHCV1 YDEL0 VNOI0 CHCV0 Not used, is acknowledged Not used, is acknowledged 12 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H sync begin, 60 Hz H sync stop, 60 Hz 14 15 HS6B7 HS6S7 HS6B6 HS6S6 HS6B5 HS6S5 HS6B4 HS6S4 HS6B3 HS6S3 HS6B2 HS6S2 HS6B1 HS6S1 HS6B0 HS6S0 H clamp begin, 60 Hz H clamp stop, 60 Hz H sync after PHI1, 60 Hz 16 17 18 HC6B7 HC6B6 HC6B5 HC6S7 HC6S6 HC6S5 HP6I7 HP6I6 HP6I5 HC6B4 HC6S4 HP6I4 HC6B3 HC6S3 HP6I3 HC6B2 HC6S2 HP6I2 HC6B1 HC6S1 HP6I1 HC6B0 HC6S0 HP6I0 LFIS1 0 OEDC LFIS0 0 OEHS Notes 1. Default values of register contents to obtain a picture see Table 6. 2. All unused control bits must be programmed with “0” (zero) as indicated in Table 5. August 1996 26 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B Function of the bits of Table 5 IDEL7 “00” to IDEL0 Increment delay time (dependent on application), step size = 4 / LLC. The delay time is selectable from −4 / LLC (−1 decimal multiplier) to −1024 / LLC (−256 decimal multiplier) equals data FF to 00 (hex). Different processing times in the chrominance channel and the clock generation could result in phase errors in the chrominance processing by transients in clock frequency. An adjustable delay (IDEL) is necessary if the processing time in the clock generation is unknown. HSYB7 “01” to HSYB0 Horizontal sync begin for 50 Hz, step size = 2 / LLC. The delay time is selectable from −382/LLC (+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) equals data BF to C0 (hex). Two’s complement numbers with “hidden” sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB−1 bits. HSYS7 “02” to HSYS0 Horizontal sync stop for 50 Hz, step size = 2 / LLC. The delay time is selectable from −382/LLC (+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) equals data BF to C0 (hex). Two’s complement numbers with “hidden” sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB−1 bits. HCLB7 “03” to HCLB0 Horizontal clamp start for 50 Hz, step size = 2 / LLC. The delay time is selectable from −254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) equals data 7F to 80 (hex). HCLS7 “04” to HCLS0 Horizontal clamp stop for 50 Hz, step size = 2 / LLC. The delay time is selectable from −254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) equals data 7F to 80 (hex). HPHI7 “05” to HPHI0 Horizontal sync after PHI1 for 50 Hz, step size = 8 / LLC. The delay time is selectable from −936 /LLC (+117 decimal multiplier) to +944/LLC (−118 decimal multiplier) equals data 75 to 8A (hex). BYPS “06” input mode select bit: 0 = CVBS mode (chrominance trap active) 1 = S-Video mode (chrominance trap bypassed) −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− PREF use of pre-filter: 0 = pre-filter off; 1 = pre-filter on; PREF may be used if chrominance trap is active. −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− BPSS1 to BPSS0 Aperture bandpass to select different characteristics with maximums (0.2 to 0.3 × LLC / 2): BPSS1 0 0 1 1 BPSS0 characteristics 0 1 0 1 ) ) ) ) Figures 16 to 25 −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− CORI1 “06” to CORI0 Coring range for high frequency components according to 8-bit luminance, Fig.15. CORI1 0 0 1 1 August 1996 CORI0 coring 0 1 0 1 coring off ±1 LSB ±2 LSB ±3 LSB 27 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) APER1 to APER0 “06” SAA7191B Aperture bandpass filter weights high frequency components of luminance signal: APER1 APER0 0 0 1 1 0 1 0 1 factor 0 0.25 0.5 1 ) ) ) ) Figure 16 to 25 HUE7 “07” to HUE0 Hue control from +178.6° to −180.0°, equals data bytes 7F to 80 (hex); 0° equals 00. CKTQ4 “08” to CKTQ0 Colour-killer threshold QAM from approximately −30 dB to −18 dB, equals data bytes F8 to 07 (hex) CKTS4 “09” to CKTS0 Colour-killer threshold SECAM from approximately −30 dB to −18 dB, equals data bytes. F8 to 07 (hex) PLSE7 “0A” to PLSE0 PAL switch sensitivity from LOW-to-HIGH (HIGH means immediate sequence correction), equals FF to 00 (hex), MEDIUM equals 80. SESE7 “0B” to SESE0 SECAM switch sensitivity from LOW-to-HIGH (HIGH means immediate sequence correction), equals FF to 00 (hex), MEDIUM equals 80. COLO “0C” Colour on bit: 0 = automatic colour-killer enabled; 1 = forced colour on. −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− LFIS1 “0C” to LFIS0 Chrominance gain control (AGC filter): LFIS1 0 0 1 1 VTRC “0D” LFIS0 0 1 0 1 loop filter time constant = = = = slow medium fast actual gain, stored for test purposes only VTR/TV mode bit : 0 = TV mode (slow time constant); 1 = VTR mode (fast time constant) −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− NFEN SAA7191B-specified functions enable (RTCO, ODD and GPSW0 outputs) 0 = outputs set to high-impedance (circuit equals SAA7191); 1 = outputs active −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− HRMV HREF generation: 0 = like SAA7191; GPSWO General purpose switch 0: 1 = HREF is 8 x LLC2 clocks earlier 0 = output pin 65 LOW; 1 = output pin 65 HIGH −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− SECS August 1996 SECAM mode bit : 0 = other standards; 1 = SECAM 28 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) HPLL “0E” SAA7191B Horizontal clock PLL: 0 = PLL closed; 1 = PLL circuit open and horizontal frequency fixed. −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− OEDC Colour-difference output enable: 0 = data outputs UV7 to UV0 can be set to high-impedance via FEIN 1 = data outputs UV7 to UV0 active. −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− OEHS H-sync output enable (pins 31 and 42): 0 = HS and HREF outputs high-impedance 1 = HS and HREF outputs active. −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− OEVS V-sync output enable (pin 30): 0 = VS output high-impedance 1 = VS output active. OEDY Luminance output enable: 0 = data outputs Y7 to Y0 can be set to high-impedance via FEIN 1 = data outputs Y7 to Y0 active. −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− CHRS S-VHS bit (chrominance from CVBS or from chrominance input): 0 = controlled by BYPS-bit (subaddress 06) 1 = chrominance from chrominance input (CHR7 to CHR0) −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− GPSW2 to “0E” August 1996 to GPSW1 General purpose switches: GPSW2 GPSW1 0 0 1 1 0 1 0 1 set port output pins 24 (GPSW2) and 25 (GPSW1) use is dependent on application 29 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) AUFD “0F” SAA7191B Automatic field detection: 0 = field selection by FSEL-bit; 1 = automatic field detection. −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− FSEL Field select (AUFD-bit = 0): 0 = 50 Hz (625 lines); 1 = 60 Hz (525 lines) −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− SXCR SECAM cross-colour reduction: 0 = reduction off; 1 = reduction on. −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− SCEN Sync and clamping pulse enable: 0 = HCL and HSY outputs HIGH (pins 26 and 29); 1 = HCL and HSY outputs active −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− OFTS Select output format: 0 = 4 : 1 : 1 format; 1 = 4 : 2 : 2 format. −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− YDEL2 to YDEL0 HFRS “10” Luminance delay compensation: YDEL2 YDEL1 YDEL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Select HREF position: figure 0 × 2 / LLC +1 × 2 / LLC +2 × 2 / LLC +3 × 2 / LLC −4 × 2 / LLC −3 × 2 / LLC −2 × 2 / LLC −1 × 2 / LLC step size = 2 / LLC = 67.8 ns for 50 Hz 81.5 ns for 60 Hz 0 = normal, HREF is matched to YUV output port; 1 = HREF is matched to CVBS input port. −−−−−−−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− VNOI1 CHCV7U V to to VNOI0 CHCV0 “11” Vertical noise reduction VNOI1 VNOI0 mode 0 0 1 1 0 1 0 1 normal searching window auto-deflection vertical noise reduction bypassed Chrominance gain control (nominal values) for QAM-modulated input signals, effects output amplitude (SECAM with fixed gain): D7 D6 D5 D4 1 0 0 0 August 1996 1 : 1 : 0 : 0 D3 D2 D1 D0 gain 1 1 1 0 1 1 1 0 1 0 0 0 maximum gain to CCIR level for PAL) to CCIR level for NTSC) to minimum gain 1 : 0 : 1 : 0 1 1 0 1 0 0 0 0 30 ) ) default programmed ) values dependent ) on application ) Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B HS6B7 “14” to HS6B0 Horizontal sync begin for 60 Hz, step size = 2 / LLC. The delay time is selectable from −382/LLC (+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) equals data BF to C0 (hex). Two’s complement numbers with “hidden” sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB−1 bits. HS6S7 “15” to HS6S0 Horizontal sync begin for 60 Hz, step size = 2 / LLC. The delay time is selectable from −382/LLC (+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) equals data BF to C0 (hex). Two’s complement numbers with “hidden” sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB−1 bits. HC6B7 “16” to HC6B0 Horizontal clamp begin for 60 Hz, step size = 2 / LLC. The delay time is selectable from −254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) equals data 7F to 80 (hex). HC6S7 “17” to HC6S0 Horizontal clamp stop for 60 Hz, step size = 2 / LLC. The delay time is selectable from −254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) equals data 7F to 80 (hex). HP6I7 “18” to HP6I0 Horizontal sync after PHI1 for 60 Hz, step size = 8 / LLC. The delay time is selectable from −776/LLC (+97 decimal multiplier) to +776 /LLC (−97 decimal multiplier) equals data 61 to 9F (hex). MEH228 handbook, full pagewidth bits +64 (c) +32 (b) (a) 0 (a) (b) –32 (c) –64 –64 (a) (b) (c) –32 0 +32 +64 bits CORI1 = 0; CORI0 = 1 CORI1 = 1; CORI0 = 0 CORI1 = 1; CORI0 = 1 Fig.15 Coring function adjustment by subaddress 06 to affect the bandfilter output signal. The thresholds are related to the 13-bit word width in the luminance processing part and influence the 1LSB to 3LSB (Y0 to Y2) with respect to the 8-bit luminance output August 1996 31 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) handbook, full pagewidth SAA7191B MEH214 18 73h 63h 12 VY (dB) 43h 43h 53h 6 53h 0 73h -6 63h -12 -18 -24 -30 0 1 2 3 4 5 6 f Y (MHz) Fig.16 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; maximum aperture bandpass filter characteristic. MEH215 handbook, full pagewidth 18 62h 61h 42h 12 VY (dB) 6 42h 41h 41h 0 62h 40h -6 61h 40h -12 -18 -24 -30 0 1 2 3 4 5 6 f Y (MHz) Fig.17 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; other aperture bandpass filter characteristics. August 1996 32 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) handbook, full pagewidth SAA7191B MEH216 18 23h 33h 12 VY (dB) 6 13h 03h 0 03h 33h 13h -6 23h 00h -12 00h -18 -24 -30 0 1 2 3 4 5 6 f Y (MHz) Fig.18 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter off and coring off; maximum aperture bandpass filter characteristic. handbook, full pagewidth MEH217 18 73h 12 63h VY (dB) 43h 6 53h 53h 43h 0 63h 73h -6 -12 -18 -24 -30 0 1 2 3 4 5 6 f Y (MHz) Fig.19 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; maximum aperture bandpass filter characteristic. August 1996 33 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) handbook, full pagewidth SAA7191B MEH218 18 61h 12 VY (dB) 42h 62h 6 43h 41h 50h 42h 62h 0 -6 50h 61h -12 -18 -24 -30 0 1 2 3 4 5 6 f Y (MHz) Fig.20 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; other aperture bandpass filter characteristics. handbook, full pagewidth MEH219 18 33h 12 VY (dB) 23h 13h 6 03h 13h 03h 33h 0 -6 23h 00h 00h -12 -18 -24 -30 0 1 2 3 4 5 6 f Y (MHz) Fig.21 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter off and coring off; maximum and minimum aperture bandpass filter characteristics. August 1996 34 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B MEH220 18 MEH221 18 handbook, halfpage handbook, halfpage C3h C2h VY (dB) 12 83h VY (dB) 82h 6 12 6 C1h 0 0 81h 80h -6 -6 -12 -12 -18 C0h -18 0 2 6 4 8 0 2 6 4 8 f Y (MHz) f Y (MHz) Fig.22 Luminance control in 50 Hz / S-VHS mode controllable by subaddress byte 06; pre-filter off and coring off; different aperture bandpass filter characteristics. Fig.23 Luminance control in 50 Hz / S-VHS mode controllable by subaddress byte 06; pre-filter on and coring off; different aperture bandpass filter characteristics. MEH222 18 VY (dB) MEH223 18 handbook, halfpage handbook, halfpage 12 VY (dB) 82h 83h C3h 12 C2h 6 6 0 0 C1h 81h C0h 80h -6 -6 -12 -12 -18 -18 0 2 4 6 8 0 f Y (MHz) 4 6 8 f Y (MHz) Fig.24 Luminance control in 60 Hz / S-VHS mode controllable by subaddress byte 06; pre-filter off and coring off; different aperture bandpass filter characteristics. August 1996 2 Fig.25 Luminance control in 60 Hz / S-VHS mode controllable by subaddress byte 06; pre-filter on and coring off; different aperture bandpass filter characteristics. 35 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B 11 PROGRAMMING EXAMPLE Coefficients to set operation for application circuits Figures 13 and 14. (All numbers of the Table 6 are hex values). Slave address byte is 8A at pin 43 = 0 V (or 8E at pin 43 = +5 V). Table 7 Recommended default values SUBADDRESS BIT NAME FUNCTION VALUE (HEX) 00 01 02 IDEL(7-0) HSYB(7-0) HSYS(7-0) increment delay H sync beginning for 50 Hz H sync stop for 50 Hz 50 30 00 03 04 05 HCLB(7-0) HCLS(7-0) HPHI(7-0) H clamping beginning for 50 Hz H clamping stop for 50 Hz H sync position for 50 Hz E8 B6 F4 −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅− 06 BYPS, PREF, BPSS(1-0) 07 08 09 CORI(1-0), APER(1-0) HUEC(7-0) CKTQ(4-0) CKTS(4-0) luminance bandwidth control: hue control (0 degree) colour-killer threshold QUAM colour-killer threshold SECAM 01(1) 00 F8 F8 PLSE(7-0) SESE(7-0) COLO, LFIS(1-0) VTRC, NFEN,HRMV, GPSW0 and SECS PAL switch sensitivity SECAM switch sensitivity chroma gain control settings 90 90 00 standard/mode control 00(2)(4), 01(3)(4) 0E HPLL, OEDC, OEHS, OEVS OEDY, CHRS, GPSW(2-1) I/O and clock control 79, 7E(5) 0F AUFD, FSEL, SXCR, SCEN, OFTS, YDEL(2-0) miscellaneous control #1 91(6), 99(7) 10 11 HRFS, VNOI(1-0) CHCV(7-0) miscellaneous control #2 chrominance gain nominal value 00 2C(8), 59(9) 12 13 − − set to zero set to zero 00 00 0A 0B 0C 0D −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅ −⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅−⋅− 14 15 HS6B(7-0) HS6S(7-0) H sync beginning for 60 Hz H sync stop for 60 Hz 34 0A 16 17 18 HC6B(7-0) HC6S(7-0) HP6I(7-0) H clamping beginning for 60 Hz H clamping stop for 60 Hz H sync position for 60 Hz F4 CE F4 Notes 1. dependent on application (Figures 16 to 25) 7. 4:2:2 format 2. for QUAM standards 8. nominal value for UV CCIR level with NTSC source 3. for SECAM 9. nominal value for UV CCIR level with PAL source 4. HPLL is in TV mode; value for VCR mode is 80 (81 for SECAM VCR mode) 5. for Y/C mode 6. 4:1:1 format August 1996 36 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B 12 PACKAGE OUTLINE PLCC68: plastic leaded chip carrier; 68 leads SOT188-2 eD eE y X 60 A 44 43 Z E 61 bp b1 w M 68 1 HE E pin 1 index A e A4 A1 (A 3) β 9 k1 27 Lp k detail X 10 26 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT A A1 min. A3 A4 max. bp b1 mm 4.57 4.19 0.51 0.25 3.30 0.53 0.33 0.81 0.66 0.180 inches 0.020 0.01 0.165 D (1) E (1) e eD eE HD HE k 24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07 k1 max. Lp v w y 0.51 1.44 1.02 0.18 0.18 0.10 Z D(1) Z E (1) max. max. 2.16 β 2.16 45 o 0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950 Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT188-2 112E10 MO-047AC August 1996 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-03-11 37 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B 13 SOLDERING 13.3 13.1 Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream corners. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 13.2 During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. August 1996 Wave soldering 38 Philips Semiconductors Product specification Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) SAA7191B 14 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 15 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 16 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 657027/00/01/pp40 Date of release: August 1996 Document order number: 9397 750 02437