PHILIPS SAA4996H

INTEGRATED CIRCUITS
DATA SHEET
SAA4996H
Motion Adaptive Colour Plus And
Control IC (MACPACIC) for
PALplus
Preliminary specification
File under Integrated Circuits, IC02
1996 Oct 28
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And
Control IC (MACPACIC) for PALplus
SAA4996H
CONTENTS
8
TEST
1
FEATURES
8.1
8.1.1
Boundary scan test
Identification codes
2
GENERAL DESCRIPTION
9
DC CHARACTERISTICS
3
QUICK REFERENCE DATA
10
AC CHARACTERISTICS
4
ORDERING INFORMATION
10.1
Clock buffers
5
BLOCK DIAGRAMS
11
LIST OF ABBREVIATIONS
6
PINNING
12
PACKAGE OUTLINE
7
FUNCTIONAL DESCRIPTION
13
SOLDERING
7.1
7.1.1
7.1.2
7.2
7.3
7.3.1
7.3.2
7.4
Introduction
Data processing
Control
General requirements
Hardware configurations and delays
Full PALplus module (see Fig.5)
Stand-alone MACPACIC (see Fig.6)
Analog processing in front of the PALplus
module
Block diagram
Luminance and helper processing
Input range
Luminance processing
Luminance helper processing
Output signals
Measurements
Line 22 offset reference measurement
Line 23 and 623 amplitude reference
measurement
Noise measurement in line 23 and 623
Automatic gain and offset control
SNERT control bits influencing the AGC and
AOC
Gain control
Offset control
Helper amplitude and bandwidth control
Output range
Chrominance
Input range
Chrominance processing
Output signals
Output range
Chrominance motion detection
Intelligent residual cross-luminance reduction
(IRXR)
Control
Input reference signals
Functional description
SNERT interface (see application note
AN95XXX)
13.1
13.2
13.3
13.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
14
DEFINITIONS
15
LIFE SUPPORT APPLICATIONS
7.5
7.6
7.6.1
7.7
7.7.1
7.8
7.9
7.9.1
7.9.2
7.9.3
7.10
7.10.1
7.10.2
7.10.3
7.10.4
7.11
7.12
7.12.1
7.12.2
7.12.3
7.12.4
7.13
7.14
7.15
7.15.1
7.15.2
7.15.3
1996 Oct 28
2
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
1
The integrated circuit is especially designed to be used in
conjunction with the SAA4997H Vertical Reconstruction IC
(VERIC) to decode the transmitted PALplus video signals
in PALplus colour TV receivers.
FEATURES
• Motion adaptive colour plus decoding
• Helper AGC/AOC
• Helper decompanding
In addition, a hardware configuration ‘stand-alone
MACPACIC’ with only two field memories (FM1 and FM4)
is also possible. In this condition no helper lines are
processed and no vertical reconstruction is applied.
This configuration enables the Motion Adaptive Colour
Plus processing to be performed in non PALplus receivers.
• Memory controlling
• VERIC controlling.
2
SAA4996H
GENERAL DESCRIPTION
The SAA4996H (MACPACIC) performs the Motion
Adaptive Colour Plus (MACP) processing which is a
dedicated field comb filter technique exploited for the
PALplus system.
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
digital supply voltage
4.75
5.25
V
Tamb
operating ambient temperature
0
+70
°C
Tdie
die temperature
−
+125
°C
4
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
SAA4996H
QFP100
1996 Oct 28
DESCRIPTION
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14 × 20 × 2.7 mm; high stand-off height
3
VERSION
SOT317-1
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
5
SAA4996H
BLOCK DIAGRAMS
handbook, full pagewidth
SAA4996H
Y_ADC
Y_FM1
17 to 24
1 to 8
8
8
60, 59,
57 to 52
8
37 to 44
LUMINANCE AND
HELPER PROCESSING
8
YL
U_ADC
V_ADC
U_FM1
V_FM1
4
VA_FRONT
CLAMP
WE_FRONT
3
CHROMINANCE
PROCESSING
11, 12,
9, 10
4
85, 86,
87, 88 4
MUX
0
91, 92,
89, 90
4
99
100
94
95
93
79
80
28
76
77
78
CONTROL
81
29
36
82
83
84
CLK_16i
SNERT INTERFACE
25, 49,
67, 73,
96
58
VERIC_AV_N
26, 50,
66, 74,
97
VSS1 to VSS5
CLOCK
BUFFER
27
98, 75, 35
3
51, 31, 65
68
TDI
Fig.1 Block diagram.
TMS
Y_TO_FM1
U_TO_FM1_0
U_MA, V_MA
WE_FM2 / U_TO_FM1_1
WE_FM3 / V_TO_FM1_1
RSTW_FM23 / V_TO_FM1_0
U_TO_FM4
V_TO_FM4
RE_FM1
WE_FM1
RE_FM4
WE_FM4
RST_FM14
VA_AI
HREF_MA
WE_MA
EVEN_FIELD
FILM
INTPOL
CLK_16B1,2,3
CLK_32B1,2,3
TDO_MA
30,
32, 34
70 72 71 69
CLK_32
4
3
TEST
33
CLK_16
VDD1 to VDD5
1996 Oct 28
SEL
IVericN
CS
CLK_32i
SNERT_CL
SNERT_RST
46, 47,
48
3
1
3
CHROMINANCE
MOTION DETECTION
AND IRXR
control
SNERT_DA
61, 62,
63, 64
4
15, 16,
13, 14 4
UV_IFA
U_FM4
V_FM4
45
Y_MA
TEST1,2,3
TCK TRSTN
MHA133
1996 Oct 28
5
SNERT_RST
SNERT_CL
SNERT_DA
WE_FRONT
CLK_32B3
CLK_32B2
CLK_32B1
CLK_16B3
CLK_16B2
CLK_16B1
CLK_32
CLK_16
64
MacpOn
CLK_16I
2
LD = 1
FilmOn
2
InvO/E
PC1
Mpip
Control 3:
22/23/623Valid,
IMacpacicN,
IVericN
Control 5:
BOH0-2,
VAA0,1,
SEL_SD_YL0,1,
NAIRXR
7
EnIRXR
VA_AI
PC2_PRE
Control 6:
Interlace,
EnPreEvFld,
PreEvFld
3
line2_every_field
CLK_16I
CLK_16I
CLK_16I
LD = 2
CLK
11
Mpip
FilmOn
HlpM0,1
TDI
TMS
TCK
TEST1
TEST2
TEST3
VERIC
CONTROL
DECODER
2 CLK_16
DELAY
16/32 MHz
CONVERTER
H/V
LOGIC
line2_every_field
TEST AND BST
22Valid
2
CLAMP
6
H_RE / WE
CLK_32I
CLK_16I
Mpip
IVericN
VA_RES
VA_AI_DIFF
6
V_RE / WE
EVEN_FIELD
IVericN
PIXEL
DECODER
LINE
DECODER
TRSTN
PC2
IVericN
2
HlpM0,1
PIXEL
COUNTER 2
10 BIT
PRE
VA_AI_DIFF
EVEN_FIELD
Fig.2 Block diagram of the control part.
3
VaDel0-2
VA_AI
EVEN_FIELD
WE_MA
0
Mpip
WeShift16_0,1
WeStrtH,V
WeStpH,V
Control 4:
SelSdYl0,1,
NmYl0,1,
Rha/Rhb0-2
7
36
WE_MA
GENERATION
CLK_16I
VA_AI DELAY
(1/2 LINE)
FIELD
DETECTION,
FIELD LENGTH
MEASUREMENT,
SNERT INTERFACE
5
MotVis0,1
LD = 2
CLK
PIXEL
10
COUNTER 1
PC1
10 BIT
PRE
IrxrThr1-4,
FixHlpMain
40
HlpM0,1
CLK_32I
CLK_16I
Mpip
LC_ACQ
InvO/E
IVericN
VA_FR_DEL
VA_RES
CLP_DIFF
CLK_16I
9
DSP
LC_DSP
LINE
9
COUNTER
9 BIT
EN
PRE
LD = 1
EN
ACQ
LINE
COUNTER
9 BIT
PRE
VA_RES
VA_FR_DEL
1
MHA137
TDO_MA
INTPOL
FILM
WE_MA
HREF_MA
RSTW_FM23
WE_FM3
WE_FM2
RST_FM14
WE_FM4
RE_FM4
WE_FM1
RE_FM1
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
HlpRedThr1-5,
MacpYhThr1-3
Preset
CLOCK
BUFFER
IVericN
1
MUX1
0
SEL
CLK_16I
1
MUX2
0
SEL
CLP_DIFF
VaDel0-2
3
VA_FRONT
DELAY
VA_AI_DIFF
CLK_16I
0
1
handbook, full pagewidth
CLAMP
VA_FRONT
Mpip
Philips Semiconductors
Preliminary specification
SAA4996H
1996 Oct 28
6
EVEN_FIELD
Line2_every_field
SNERT_RST
SNERT_CL
SNERT_DA
LINE 2
ODD / EVERY FIELD
ENABLE SIGNAL
GENERATION
Interlace
SEND / RECEIVE
CONTROLLING
4 BIT COUNTER
DATA AND ADDRESS
LATCH ENABLE
GENERATION
SERIAL DATA I/O
REGISTER
8
ADDRESS
DECODER
21
adr_en_50h
to
adr_en_68h
21 ACTUAL
DATA
INPUT
REGISTER
8
8
8
8
MHA138
Control 6
HlpRedThr1,2,3,4,5,
MacpYhThr1,2,3,
IrxrThr1,2,3,4,
FixHlpMain,
Control 5
WeStrtV,
WeStpV
WeStrtH,
WeStpH
Control 2
Control 1
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
Line2_every_field
1 SYNCHRON
DATA
INPUT
REGISTER
SNERT_RST
Control 6/1
WeStrtV*,
WeStpV*
2×9
14 × 8
DATA
INPUT
REGISTER
2 SYNCHRON
Line2_odd_every_field
Control 2/2
Control 1/2
Control 5
Control 4
2×8
4 ACQ DATA
INPUT
REGISTER
2 ACQ DATA
INPUT
REGISTER
8
8
FastTest
(bit D3)
FAST TEST DELAY
FastTest_Del
8
8
WeStrtH*,
WeStpH*
2×9
Control 2/1
Control 1/1
SNERT_RST
2 ACQ DATA
OUTPUT
REGISTER
2×8
8
8
adr_H65/H66
8
Fig.3 Block diagram of the SNERT interface.
Line2_odd_every_field
SNERT_RST
DATA_IN
DLE
ALE
handbook, full pagewidth
DATA_OUT
Philips Semiconductors
Preliminary specification
SAA4996H
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
6
SAA4996H
PINNING
SYMBOL
PIN
DESCRIPTION
Y_FM1_7
1
CVBS/helper/luminance input data bit 7 from FM1
Y_FM1_6
2
CVBS/helper/luminance input data bit 6 from FM1
Y_FM1_5
3
CVBS/helper/luminance input data bit 5 from FM1
Y_FM1_4
4
CVBS/helper/luminance input data bit 4 from FM1
Y_FM1_3
5
CVBS/helper/luminance input data bit 3 from FM1
Y_FM1_2
6
CVBS/helper/luminance input data bit 2 from FM1
Y_FM1_1
7
CVBS/helper/luminance input data bit 1 from FM1
Y_FM1_0
8
CVBS/helper/luminance input data bit 0 from FM1
V_FM1_0
9
chrominance input data bit 0 from FM1
V_FM1_1
10
chrominance input data bit 1 from FM1
U_FM1_0
11
chrominance input data bit 0 from FM1
U_FM1_1
12
chrominance input data bit 1 from FM1
V_ADC_0
13
chrominance input data bit 0 from ADC
V_ADC_1
14
chrominance input data bit 1 from ADC
U_ADC_0
15
chrominance input data bit 0 from ADC
U_ADC_1
16
chrominance input data bit 1 from ADC
Y_ADC_0
17
CVBS/helper/luminance data input bit 0 from ADC
Y_ADC_1
18
CVBS/helper/luminance data input bit 1 from ADC
Y_ADC_2
19
CVBS/helper/luminance data input bit 2 from ADC
Y_ADC_3
20
CVBS/helper/luminance data input bit 3 from ADC
Y_ADC_4
21
CVBS/helper/luminance data input bit 4 from ADC
Y_ADC_5
22
CVBS/helper/luminance data input bit 5 from ADC
Y_ADC_6
23
CVBS/helper/luminance data input bit 6 from ADC
Y_ADC_7
24
CVBS/helper/luminance data input bit 7 from ADC
VDD1
25
positive supply voltage 1
VSS1
26
negative supply voltage 1
CLK_16
27
16 MHz line-locked system clock input pulse
WE_MA
28
write enable output signal; defines active video data
CLAMP
29
horizontal reference input pulse
TEST1
30
test pin 1; must be LOW during normal operation
CLK_32B2
31
32 MHz line-locked clock output pulse
TEST2
32
test pin 2; must be LOW during normal operation
CLK_32
33
32 MHz line-locked system clock input pulse
TEST3
34
test pin 3; must be LOW during normal operation
CLK_16B3
35
16 MHz line-locked clock output pulse
36
write enable input signal used as horizontal reference in the event of active
data
Y_TO_FM1_0
37
CVBS/helper/luminance output data bit 0 to FM1; stand-alone MACPACIC
Y_TO_FM1_1
38
CVBS/helper/luminance output data bit 1 to FM1; stand-alone MACPACIC
Y_TO_FM1_2
39
CVBS/helper/luminance output data bit 2 to FM1; stand-alone MACPACIC
WE_FRONT
1996 Oct 28
7
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SYMBOL
SAA4996H
PIN
DESCRIPTION
Y_TO_FM1_3
40
CVBS/helper/luminance output data bit 3 to FM1; stand-alone MACPACIC
Y_TO_FM1_4
41
CVBS/helper/luminance output data bit 4 to FM1; stand-alone MACPACIC
Y_TO_FM1_5
42
CVBS/helper/luminance output data bit 5 to FM1; stand-alone MACPACIC
Y_TO_FM1_6
43
CVBS/helper/luminance output data bit 6 to FM1; stand-alone MACPACIC
Y_TO_FM1_7
44
CVBS/helper/luminance output data bit 7 to FM1; stand-alone MACPACIC
U_TO_FM1_0
45
chrominance output data to FM1; stand-alone MACPACIC
WE_FM2/U_TO_FM1_1
46
for full PALplus module; write enable for FM2 for stand-alone MACPACIC;
chrominance output to FM1
RSTW_FM23/V_TO_FM1_0
47
for full PALplus module; reset write for FM2/FM3 for stand-alone
MACPACIC; chrominance output to FM1
WE_FM3/V_TO_FM1_1
48
for full PALplus module; write enable for FM3 for stand-alone MACPACIC;
chrominance output to FM1
VDD2
49
positive supply voltage 2
VSS2
50
negative supply voltage 2
CLK_32B1
51
32 MHz line-locked clock output pulse
Y_MA_0
52
luminance output data bit 0 from MACPACIC
Y_MA_1
53
luminance output data bit 1 from MACPACIC
Y_MA_2
54
luminance output data bit 2 from MACPACIC
Y_MA_3
55
luminance output data bit 3 from MACPACIC
Y_MA_4
56
luminance output data bit 4 from MACPACIC
Y_MA_5
57
luminance output data bit 5 from MACPACIC
VERIC_AV_N
58
input configuration signal VERIC available (VERIC_AV_N = 0)
Y_MA_6
59
luminance output data bit 6 from MACPACIC
Y_MA_7
60
luminance output data bit 7 from MACPACIC
U_MA_0
61
chrominance output data bit 0 from MACPACIC
U_MA_1
62
chrominance output data bit 1 from MACPACIC
V_MA_0
63
chrominance output data bit 0 from MACPACIC
V_MA_1
64
chrominance output data bit 1 from MACPACIC
CLK_32B3
65
32 MHz line-locked clock output pulse
VSS3
66
negative supply voltage 3
VDD3
67
positive supply voltage 3
TDO_MA
68
boundary scan test: data output signal
TRSTN
69
boundary scan test: reset input signal
TDI
70
boundary scan test: data input signal
TMS
71
boundary scan test: multiplexer set input
TCK
72
boundary scan test: clock input signal
VDD4
73
positive supply voltage 4
VSS4
74
negative supply voltage 4
CLK_16B2
75
16 MHz line-locked clock output pulse
EVEN_FIELD
76
even field =0 = odd input field; even field =1 = even input field
1996 Oct 28
8
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SYMBOL
SAA4996H
PIN
DESCRIPTION
FILM
77
control output signal to select film or camera mode in VERIC;
FILM = 0: camera mode; FILM = 1: film mode; FILM = 1 and INTPOL = 0;
bypass mode for MultiPIP
INTPOL
78
INTPOL = 0 = vertical interpolation in the VERIC not active;
INTPOL = 1 = vertical interpolation in the VERIC active
VA_AI
79
vertical reference output pulse or vertical reference input pulse in MultiPIP
mode
HREF_MA
80
horizontal reference output pulse
VA_FRONT
81
vertical reference input pulse or vertical reference output pulse in MultiPIP
mode
SNERT_DA
82
Synchronous No parity Eight bit Reception and Transmission (SNERT)-bus
data
SNERT_CL
83
SNERT-bus clock
SNERT_RST
84
SNERT-bus reset
U_FM4_0
85
chrominance input data bit 0 from FM4
U_FM4_1
86
chrominance input data bit 1 from FM4
V_FM4_0
87
chrominance input data bit 0 from FM4
V_FM4_1
88
chrominance input data bit 1 from FM4
V_TO_FM4_1
89
chrominance output data bit 1 to FM4
V_TO_FM4_0
90
chrominance output data bit 0 to FM4
U_TO_FM4_1
91
chrominance output data bit 1 to FM4
U_TO_FM4_0
92
chrominance output data bit 0 to FM4
RST_FM14
93
reset read/write FM1 and FM4 output
RE_FM4
94
read enable FM4 output
WE_FM4
95
write enable FM4 output
VDD5
96
positive supply voltage 5
VSS5
97
negative supply voltage 5
CLK_16B1
98
16 MHz line-locked clock output pulse
RE_FM1
99
read enable FM1 output
WE_FM1
100
write enable FM1 output
1996 Oct 28
9
Philips Semiconductors
Preliminary specification
81 VA_FRONT
82 SNERT_DA
83 SNERT_CL
84 SNERT_RST
85 U_FM4_0
86 U_FM4_1
SAA4996H
87 V_FM4_0
88 V_FM4_1
89 V_TO_FM4_1
90 V_TO_FM4_0
91 U_TO_FM4_1
92 U_TO_FM4_0
93 RST_FM14
94 RE_FM4
95 WE_FM4
97 VSS5
96 VDD5
98 CLK_16B1
handbook, full pagewidth
99 RE_FM1
100 WE_FM1
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
Y_FM1_7
1
80 HREF_MA
Y_FM1_6
2
79 VA_AI
Y_FM1_5
3
78 INTPOL
Y_FM1_4
4
77 FILM
Y_FM1_3
5
76 EVEN_FIELD
Y_FM1_2
6
75 CLK_16B2
Y_FM1_1
7
Y_FM1_0
8
74 VSS4
73 VDD4
V_FM1_0
9
72 TCK
V_FM1_1 10
71 TMS
U_FM1_0 11
70 TDI
U_FM1_1 12
69 TRSTN
V_ADC_0 13
68 TDO_MA
V_ADC_1 14
67 VDD3
66 VSS3
U_ADC_0 15
SAA4996H
U_ADC_1 16
65 CLK_32B3
Y_ADC_0 17
64 V_MA_1
Y_ADC_1 18
63 V_MA_0
Y_ADC_2 19
62 U_MA_1
Y_ADC_3 20
61 U_MA_0
Y_ADC_4 21
60 Y_MA_7
Y_ADC_5 22
59 Y_MA_6
Y_ADC_6 23
58 VERIC_AV_N
Y_ADC_7 24
57 Y_MA_5
VDD1 25
56 Y_MA_4
VSS1 26
55 Y_MA_3
CLK_16 27
54 Y_MA_2
WE_MA 28
53 Y_MA_1
CLAMP 29
52 Y_MA_0
TEST1 30
Fig.4 Pin configuration.
1996 Oct 28
10
VSS2 50
VDD2 49
WE_FM3/V_TO_FM1_1 48
RSTW_FM23/V_TO_FM1_0 47
WE_FM2/U_TO_FM1_1 46
Y_TO_FM1_7 44
U_TO_FM1_0 45
Y_TO_FM1_6 43
Y_TO_FM1_5 42
Y_TO_FM1_4 41
Y_TO_FM1_3 40
Y_TO_FM1_2 39
Y_TO_FM1_1 38
Y_TO_FM1_0 37
WE_FRONT 36
CLK_16B3 35
TEST3 34
CLK_32 33
TEST2 32
CLK_32B2 31
51 CLK_32B1
MHA134
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
7
7.1.2
FUNCTIONAL DESCRIPTION
7.1
The special ICs are as follows;
• Motion Adaptive Colour Plus And Control IC
(MACPACIC) for PALplus (SAA4996H)
• Vertical Reconstruction IC (VERIC) (SAA4997H).
Besides the full PALplus module, a configuration for
stand-alone Motion Adaptive Colour Plus processing
(MACP) is also possible (see Fig.6). In this event only
MACPACIC with FM1 and FM4 are necessary.
This configuration enables the MACP processing in
non-PALplus receivers to be performed.
7.2
General requirements
The PALplus IC set is designed to operate in conjunction
with the PHILIPS 100 Hz feature box. All requirements
with respect to this combination are fulfilled.
The special requirements are as follows;
The PALplus module is designed to operate in conjunction
with a 100 Hz feature box. All special requirements such
as the delay of the PALplus module, bypass modes and
generation of the necessary control and clock signals will
be fulfilled.
• The signal processing is adapted to the analog
preprocessing in the TDA9144 for luminance, helper
and chrominance signals
• Clock rate and clock generation
• Some special control signals are generated in the
PALplus module
DATA PROCESSING
• The field length must be measured and used to set the
delay of the full PALplus module to 1.5 fields
The MACPACIC includes the decompanding functions for
the helper lines and the motion adaptive
luminance/chrominance separation in accordance with the
PALplus system description REV. 3.0 with some
modifications;
• A SNERT interface is used to transfer control data to
and from the PALplus module
• MultiPIP with the help of a PIP module is possible
• The system operates at a clock frequency of 16 MHz
• Results of noise measurements influence the helper
processing
• The Y:U:V format is 4:1:1 instead of 4:2:2
• The filter DEC_MD_UV_LPF is not implemented
• Automatic gain and offset control is implemented
• If noisy helper signals are received, the helper
bandwidth and/or amplitude can be reduced
• Reference signals in line 22 are used for inverse set-up
operation
• Automatic gain control of the helper signal with respect
to the luminance signal.
• Noise measurement implemented
• Boundary scan test implemented
The input signals are the BB(helper)/CVBS and
chrominance signals which are derived from the
analog-to-digital converter (ADC).
• Preset of internal recursive parts for testing.
At its outputs the MACPACIC delivers separate luminance
and chrominance signals, each one free from
cross-artefacts as main signal, as well as decompanded
and filtered helper signals. For standard input signals and,
in the event of MultiPIP mode with the help of a
PIP module, the MACPACIC can be switched to different
bypass modes.
1996 Oct 28
CONTROL
Memory control, PALplus system controlling and clock
generation (from the incoming 16 MHz and 32 MHz
line-locked clocks) are implemented in the MACPACIC.
All clocks and control signals necessary for the PALplus
module (excluding read control of FM2/FM3) are
generated in the controller part. Inputs are reference
signals, clocks and control signals delivered by the
colour/helper decoder IC (TDA9144), and the 100 Hz
memory controller, i.e. ECO4 (SAA4952) or ECOBENDIC
(SAA4970). The MACPACIC also receives control
information via a three-wire serial interface (SNERT-bus)
from the microprocessor in the 100 Hz feature box.
Introduction
The MACPACIC is designed to be used in the PALplus
decoder module of a PALplus colour TV receiver. The full
PALplus decoder module consists of two special
integrated circuits and four field memories, as illustrated in
Fig.5.
7.1.1
SAA4996H
11
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
7.3
7.4
Hardware configurations and delays
Two general hardware configurations are possible.
7.3.1
Because of the requirement that a standard ADC with
clamping on 16 should be used for CVBS and helper
analog-to-digital conversion, a black (letter box lines) and
mid grey (helper lines) shift is applied in the colour/helper
decoder. For reshifting without errors in the digital domain
these shift levels are inserted as a reference in line 22.
In the MultiPIP mode the delay of the full PALplus module
is one line.
In the event of stand-alone MACPACIC and PALplus input
signals the helper demodulation must be switched off.
STAND-ALONE MACPACIC (see Fig.6)
No special actions are taken in the colour/helper decoder
for chrominance processing.
In this situation only the MACPACIC with FM1 and FM4
are necessary. No helper lines are processed and no
vertical reconstruction with the VERIC is applied.
The delay from input to output is one field, one line and
some clocks of processing delay, this also applies in the
bypass mode. In the MultiPIP mode the delay is two clocks
(CLK_16).
1996 Oct 28
Analog processing in front of the PALplus
module
In front of the MACPACIC an analog colour/helper
decoder (TDA9144) performs the colour and helper
demodulation.
FULL PALPLUS MODULE (see Fig.5)
The delay from input to output is 1.5 fields rounded to
complete lines, also in the bypass mode. Therefore, the
number of input lines of the odd and even fields must be
measured. The result of this measurement is then used to
generate the required delay.
7.3.2
SAA4996H
In this document U will refer to −(B − Y) and V will refer to
−(R − Y).
In combination with the full PALplus module with letter box
input signals (16:9), the PAL delay line of the colour/helper
decoder must be switched off. This is because this function
is also implemented in the vertical reconstruction filter of
the VERIC. For all other input signals and for stand-alone
MACPACIC the PAL delay line must be switched on.
12
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
handbook, full pagewidth
SAA4996H
3
SAA4997H
CLK_16B1, 2, 3
3
8
SAA4996H
CLK_32B1, 2, 3
Y_VE_0...7
CLK_32B1
8
Y_VE_[0...7]
Y_ADC_0...7
Y_FRONT[0...7]
8
FIELD MEMORY
8
8
Y_MA_0...7
FM1
SWCK
4
FIELD MEMORY
FM2
4
U_FM1_0,1
V_FM1_0,1
8
SRCK
FIELD MEMORY
CLK_16B1
FM3
CLK_16
4
U_ADC_0,1
V_ADC_0,1
U_FRONT[0,1]
V_FRONT[0,1]
8
4
4
Y_FM23_0...7
U_FM23_0,1
V_FM23_0,1
8
4
U_MA_0,1
V_MA_0,1
4
8
Y_FM1_0...7
U_VE_[0,1]
V_VE_[0,1]
4
4
U_VE_0,1
V_VE_0,1
CLK_32B3
8
VDD1-5
VSS1-5
5
BB-DECOMPANDING
5
CLK_16
CLK_32
MOTION ADAPTIVE
LUMINANCE /
CHROMINANCE
SEPARATION
VA_FRONT
WE_FRONT
CLAMP
MEMORY CONTROL
PALplus CONTROL
SNERT_DA
SNERT_CL
SNERT_RST
VERIC_AV_N (2)
U_TO_FM1_1
RSTW_FM23 (1)
2
V_TO_FM1_1
HREF_MA
WE_FM1, RE_FM1
WE_FM4, RE_FM4
VA_AI
SYNC GENERATION
SNERT INTERFACE
WE_MA
HREF_MA
FILM
EVEN_FIELD
INTPOL
3
U_TO_FM4_0,1 U_FM4_0,1
V_TO_FM4_0,1 V_FM4_0,1
4
VSS1-4
CLK_16B2
RST_FM14
2
VDD1-4
V_TO_FM1_0
WE_FM3 (1)
CLOCK GENERATION
TRSTN
TDI
TMS
TCK
TEST1-3
Y_TO_FM1_0...7
U_TO_FM1_0
WE_FM2 (1)
TDO_MA
4
4
CLK_32B3
VERTICAL
CHROMINANCE
SRC
VA_AI
RE_FM2
FM2 / FM3
READ CONTROL
EVEN_FIELD
INTPOL
TDI
TMS
TCK
TEST1-3
3
11
MHA136
4
CLK_16B1
(1) In case of stand-alone MACPACIC the output signals are U_TO_FM1_1, V_TO_FM1_0 or V_TO_FM1_1.
Otherwise the output signals are WE_FM2, RSTW_FM23 or WE_FM3.
(2) VERIC available: VERIC_AV_N is connected to VSS.
1996 Oct 28
13
RE_FM3
RSTR_FM23
TRSTN
NC
Fig.5 PALplus decoder module.
TDO_VE
OE_FM2
OE_FM3
FILM
FIELD MEMORY
FM4
INVERSE QMF
RECONSTRUCTION
FILTER
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
handbook, full pagewidth
8
Y_TO_FM1_0...7
8
Y_ADC_0...7
Y_FRONT[0...7]
FIELD MEMORY
8
Y_TO_FM1_0
Y_FM1_0...7
8
Y_MA_0...7
Y_MA_0...7
FM1
4
SWCK
SRCK
U_FM1_0,1
V_FM1_0,1
CLK_16
WE_FM2
U_TO_FM1_1 (1)
U_ADC_0,1
V_ADC_0,1
U_FRONT[0,1]
V_FRONT[0,1]
VDD1-5
VSS1-5
VA_FRONT
WE_FRONT
CLAMP
3
MEMORY CONTROL
2
3
CLOCK GENERATION
CLK_16B1, 2, 3
CLK_32B1, 2, 3
WE_FM1, RE_FM1
RST_FM14
2
WE_FM4, RE_FM4
VA_AI
SYNC GENERATION
TRSTN
TDI
TMS
TCK
VERIC_AV_N (2)
MOTION ADAPTIVE
LUMINANCE /
CHROMINANCE
SEPARATION
PALplus CONTROL
SNERT_DA
SNERT_CL
SNERT_RST
TEST1-3
WE_FM3
V_TO_FM1_1 (1)
5
5
CLK_16
CLK_32
U_MA_0,1
V_MA_0,1
RSTW_FM23
V_TO_FM1_0 (1)
SAA4996H
CLK_16B1
4
4
U_MA_0,1
V_MA_0,1
SNERT INTERFACE
WE_MA
HREF_MA
FILM
EVEN_FIELD
INTPOL
3
U_TO_FM4_0,1 U_FM4_0,1
V_TO_FM4_0,1 V_FM4_0,1
4
TDO_MA
4
FIELD MEMORY
FM4
CLK_16B1
MHA135
(1) In case of stand-alone MACPACIC the output signals are U_TO_FM1_1, V_TO_FM1_0 or V_TO_FM1_1.
Otherwise the output signals are WE_FM2, RSTW_FM23 or WE_FM23.
(2) VERIC not available: VERIC_AV_N is connected to VDD.
Fig.6 Stand-alone MACPACIC.
1996 Oct 28
14
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
7.5
7.7
Block diagram
• Luminance and helper processing
• Chrominance processing
• Chrominance motion detection
• Control.
To remove the chrominance part of the incoming
composite video signal, the Motion Adaptive Colour Plus
technique is applied. Colour Plus is a dedicated comb filter
technique, which makes full use of the correlation of two
successive fields.
The clock rate of the input data is 16 MHz. Internally, the
device operates at a 32 MHz clock frequency. The clock
rate of the output data is either 32 MHz (in combination
with FM2, FM3 and VERIC) or 16 MHz for stand-alone
MACP processing.
During processing the data of the odd and even fields are
separated in a high-pass and low-pass part. The high-pass
part consists of the luminance high-pass component and
the modulated chrominance signal. Due to the phase
difference of the colour carrier of 180° from the odd to the
even field, the chrominance signal can be removed by
adding the high-pass signals.
The delay of the full PALplus module is 1.5 fields in the
PALplus and bypass mode. A field length measurement is
implemented. For MultiPIP with the help of a PIP module
the delay of the PALplus module is one line.
For stand-alone MACP the delay is one field, one line and
some clocks of processing delay.
This processing will work successfully in the film mode,
because scanned film material is motionless within the two
fields of one frame. In the camera mode a motion detector
fades down the luminance high-pass component if motion
is detected.
For MultiPIP with the help of a PIP module the delay of
MACPACIC is two clocks (CLK_16).
Luminance and helper processing
7.6.1
INPUT RANGE
The following vertical low-pass filters perform a vertical
interpolation of the high-pass part by the factor of two.
To use a standard ADC with clamping on 16, a black
set-up for the CVBS signal and a black/mid grey set-up for
the helper signal has to be performed in the colour/helper
decoder. The shift values for black set-up and mid grey
set-up are inserted in line 22.
In the event of bad signal conditions, the residual
cross-luminance signal, caused by clock jitter between two
fields, can be reduced by using this filter as a 2D comb
filter. Therefore different sets of coefficients can be
selected via SNERT.
All values are nominal values.
The luminance high-pass part and the luminance low-pass
part are then added.
CVBS:
clamp level: 16
The automatic gain control (AGC) and automatic offset
control (AOC) functions use reference lines 23,
623 and 22 to reduce errors in the vertical reconstruction
in the VERIC. This is to reduce the effects of any errors
that might be caused due to variations in the conventional
PAL references in the signal during the transmission chain
with respect to the levels of the luminance letter box and
helper signals.
black set-up: 51
white: 191
format: 8-bit, straight binary
Helper:
mid grey set-up: 121
range: (121 − 60) to (121 + 60) = 61 to 181
format: 8-bit, offset binary
Y (standard input):
black: 16
peak white: 191
format: 8-bit, straight binary
1996 Oct 28
Luminance processing
The luminance and the helper processing have two input
branches. One input is an 8-bit wide 16 MHz data stream
from the ADC. The other is an 8-bit wide 16 MHz data
stream from the field memory (FM1). The odd field of an
input frame is stored in the field memory FM1. In the even
field of a frame, the even field together with the delayed
odd field is processed by the MACPACIC.
The functional block diagram of the MACPACIC for
PALplus is illustrated in Fig.1. The device consists of
4 main parts:
7.6
SAA4996H
15
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
7.7.1
The content and the timing of the reference lines are
illustrated in Figs 13, 14 and 15.
LUMINANCE HELPER PROCESSING
In the event of incoming helper, the switchable low-pass
filter acts as an inverse shaping and bandwidth reduction
filter for the helper lines. If a distorted helper signal is
transmitted, the bandwidth can be reduced from 2.2 MHz
(0 dB) to 1.0 MHz or to 0.5 MHz (−3 dB).
7.9.1
LINE 22 OFFSET REFERENCE MEASUREMENT
Due to the fact that a standard ADC with a clamping level
of 16 should be inserted for CVBS and helper
analog-to-digital conversion, a black offset for the letter
box lines and a mid grey offset for the helper lines are
carried out in the colour/helper decoder. These offset
values are inserted as references in line 22 to reshift the
CVBS and helper signals in the digital domain without
errors. Therefore, a measurement of the offsets in line 22
is necessary. The average value of the real offset is
calculated from 64 samples and substacted from the
CVBS and helper signal. The CVBS and helper input
signal are illustrated in Fig.16.
The high-pass part of the luminance processing is not
used for the helper processing.
To stabilize the transmitted helper signal against noise
disturbances, the encoder performs a companding of the
signal. In the decoder the decompanding is performed in
the AGOC block (see Fig.7).
7.8
SAA4996H
Output signals
In the event of full PALplus configuration, odd and even
field data are multiplexed to a 32 MHz data stream.
7.9.2
For the stand-alone MACPACIC, the processed even field
data is connected to the field memory FM1 and the odd
field data is switched to the output Y_MA. In the next field
the stored even field data is read out of the field memory
FM1 and then connected to the output of the MACPACIC.
LINE 23 AND 623 AMPLITUDE REFERENCE
MEASUREMENT
The helper and luminance amplitude measurement
consists of averaging 64 samples each of;
Helper zero (MHZ).
If MultiPIP mode is selected, the luminance input data from
the ADC (Y_ADC) is switched directly to the output Y_MA.
Helper maximum (MHM).
In the bypass mode the luminance data processing is
switched off and multiplexed data is connected to the
MACPACIC output.
Luminance white (MLW).
Luminance black (MLB).
Measured helper amplitude = helper maximum minus
helper zero.
The clock frequency of the output data Y_MA is 32 MHz for
the MACPACIC in combination with the VERIC, or 16 MHz
for the stand-alone MACPACIC.
Measured luminance amplitude = luminance white minus
luminance black.
7.9
Frame integration is performed with a feed back factor of
(1 − K) = 1⁄16. The frame integration part can be preset with
the first measured value. Preset is controlled with the
preset bit transmitted via SNERT.
Measurements
The digital data stream at the input of the PALplus decoder
module contains three reference lines;
• Reference line 22 consists of the black and mid grey
set-up, inserted by the colour/helper decoder
7.9.3
For the helper lines the noise measurement is carried out
in reference line 23 and for the letter box lines in reference
line 623. Both measurements are active in the black
reference levels of line 23 and line 623 respectively.
The processing of the noise measurement for the helper
signal and the letter box signal is performed in the same
way.
• The second half of line 23 contains the black level
reference and the maximum negative reference for the
PALplus helper lines
• The first half of line 623 contains reference values for
the black level and the peak white level for the main
lines.
First the average value of 64 samples is calculated.
The single actual sample values are subtracted from this
average value and the sum of these absolute differences
are frame integrated. The integration factor is 1 − K = 1⁄16.
The reference lines 23 and 623 are generated by the
PALplus encoder and are used to reduce the effects of any
errors that might be caused due to variations in the
transmission chain with respect to the levels of the
luminance letter box and helper signals.
1996 Oct 28
NOISE MEASUREMENT IN LINE 23 AND 623
16
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
The frame integration part can be preset with the first
measured value. Preset is controlled via a bit from the
SNERT interface.
7.10
The helper amplitude is reduced when the measured noise
exceeds a certain threshold level. These thresholds are
conveyed via the SNERT-bus. The reduction of the helper
amplitude, before decompanding, ensures that more noise
is cancelled by the coring. The adaptive helper gain control
is switched off when the SNERT bits HlpM1 and HlpM0 are
both at logic 1. In this condition the helper gain is defined
by the values FixHlp and FixMain via the SNERT-bus.
Automatic gain and offset control
The automatic gain and offset control circuit evaluates the
results of the reference data, which are derived from
reference lines 22, 23 and 623 to eliminate any offset and
gain differences between the letter box lines and the
helper lines. This is caused during transmission of the
video signal.
7.10.1
If the measured helper or luminance amplitude is below
the threshold level, or when line 22 is not valid, the helper
is switched off.
7.10.3
SNERT CONTROL BITS INFLUENCING THE AGC AND
AOC
For luminance offset control a hysteresis function,
controlled by SNERT, is applied to the measured
luminance offset.
FilmOn: If line 22 is not detected, the VERIC operates in
Camera mode.
HlpM1, HlpM0: In adaptive and fixed helper processing
modes (HlpM1 = 1, HlpM0 = X) AGC and AOC are
achieve.
HlpM0
0
0
no helper processing
(any aspect ratio, without helper)
0
1
helper set to zero
(up-conversion without helper)
1
0
adaptive helper processing (helper
processing controlled by reference
amplitudes and noise in the helper
channel)
1
7.10.2
7.10.4
1
Five thresholds are therefore transmitted via SNERT.
These thresholds are compared with the measured helper
noise value. The results are used to control a state
machine with five states.
FUNCTION
The state machine is initialized with the preset bit from
SNERT or when line 22 is valid for the first time.
The output states are used to control the helper amplitude
and bandwidth as shown in Fig.8 and Tables 2 and 3.
7.11
fixed helper processing (fixed gain
values loaded via SNERT-bus)
Output range
Luminance lines: straight binary, black = 16, white = 191.
PALplus helper lines: offset binary, 128 ±70.
GAIN CONTROL
If line 22 reference is present in a frame, the luminance
input signal contains black set-up and reduced amplitude.
The luminance gain then is 1.25. If line 22 is not valid the
luminance gain is 1.0.
The helper gain is controlled by the measured helper
amplitude in line 23 to match the helper amplitude to the
decompanding table. After decompanding the helper
amplitude is controlled by the measured luminance
amplitude in line 623, to obtain the correct
luminance/helper ratio for the QMF filter in the VERIC.
1996 Oct 28
HELPER AMPLITUDE AND BANDWIDTH CONTROL
In the event of noisy helper signals the helper amplitude
and bandwidth can be reduced to avoid disturbances in
the inverse QMF processing in VERIC.
Control bits HlpM1 and HlpM0
HlpM1
OFFSET CONTROL
As long as line 22 reference is present, luminance and
helper offset are controlled by line 22. If line 22 is not valid
the offset value is fixed to 16.
MacpOn: If line 22 is not detected this bit will be ignored
and the MACP processing (and thus AGC and AOC) is
switched off.
Table 1
SAA4996H
17
1996 Oct 28
Y_FM1
Y_ADC
18
SWITCHABLE
LOW-PASS
FILTER
HIGH-PASS
FILTER
HIGH-PASS
FILTER
LOW-PASS
FILTER
handbook, full pagewidth SWITCHABLE
Y_LP (odd)
LM
X
VERTICAL
LPF
3 TAB
VERTICAL
LPF
3 TAB
+
+
AGOC
Y_ADC
Y_FM1
measurement
results
MEASUREMENTS
AGOC
MHA300
MUX
Y_MA
Y_TO_FM1
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
Fig.7 Luminance and helper processing.
Y_HP
Y_HP (odd)
+
LM
YL
(fade controlled
from motion
detector)
Y_HP (even)
Y_LP (even)
Philips Semiconductors
Preliminary specification
SAA4996H
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
state machine
output
handbook, halfpage
4
3
2
Measured Helper
Noise (MHN)
HlpRedThr5
HlpRedThr4
HlpRedThr3
HlpRedThr2
0
HlpRedThr1
1
MHA295
Fig.8 Helper bandwidth and amplitude reduction.
Table 2
Measured Helper Noise in Zero (MHNZ)
MHNZ
STATE MACHINE (OLD)
STATE MACHINE (NEW)
MHNZ < HlpRedThr1
X
4
HlpRedThr1 ≤ MHNZ < HlpRedThr2
4
4
<4
3
≥3
3
<3
2
HlpRedThr2 ≤ MHNZ < HlpRedThr3
HlpRedThr3 ≤ MHNZ < HlpRedThr4
HlpRedThr4 ≤ MHNZ < HlpRedThr5
HlpRedThr5 ≤ MHNZ
Table 3
≥2
2
<2
1
≥1
1
0
0
X
0
State machine output
STATE MACHINE OUTPUT
REDUCE HELPER BANDWIDTH (RHB)
REDUCE HELPER AMPLITUDE (RHA)
4
0 (2.2 MHz LPF)
2; note 1
3
1 (1.0 MHz LPF)
2
2
1 (1.0 MHz LPF)
1; note 2
1
2 (0.5 MHz LPF)
1
0
2 (0.5 MHz LPF)
0; note 3
Notes
1. No helper amplitude reduction.
2. Helper amplitude reduction via LUT of about 50%.
3. Helper signal zero.
1996 Oct 28
19
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
7.12
7.12.1
Odd and even field data are multiplexed and connected to
the output of MACPACIC.
Chrominance
INPUT RANGE
The chrominance processing has two input branches (see
Fig.9). One input branch is the direct chrominance input
path from the ADC. The other input branch is the output of
the field memory FM1. The odd field of a frame is stored in
the field memory FM1. In the even field of a frame the
delayed odd field and the incoming even field are
processed with the motion adaptive colour plus algorithm
to the cross-colour free chrominance output data.
The input is a 4:1:1 sequential 4-bit wide UV signal with a
16 MHz clock frequency. Originally the U and V signals
were 8 bits wide with a sampling frequency of 4 MHz each.
The range is 0 ±90 in two’s complement format for
U and V.
7.12.2
SAA4996H
CHROMINANCE PROCESSING
The Motion Adaptive Colour Plus technique is also applied
in the chrominance processing to remove the luminance
part from the incoming demodulated UV signal.
By adding the incoming chrominance signals of the odd
and even fields, the intra frame average chrominance
signal (UVifa) is generated.
In the modulated domain the chrominance signal can be
generated by subtracting the odd and even field data due
to the 180° phase difference of the colour subcarrier.
The colour decoder eliminates the phase difference of the
chrominance signals, but now the luminance signals will
obtain the phase difference of 180°.
For the chrominance motion detector this signal is stored
after formatting in the memory FM4 (UV_TO_FM4).
7.12.3
The output data rate is 32 MHz for MACPACIC in
combination with VERIC and 16 MHz for stand-alone
MACPACIC or in the MultiPIP mode.
By adding the odd and even field data, the cross-colour
free chrominance signal (UVifa) is generated.
In the MultiPIP mode the chrominance data from the ADC
(UV_ADC) is switched directly to the output UV_MA.
This processing will work successfully in the film mode,
because scanned film material is motionless within the two
fields of one frame. In the camera mode, where each field
represents an individual picture, a motion detector fades
down the chrominance high-pass component if motion is
detected.
In the bypass mode the chrominance data processing is
switched off and the multiplexed odd and even field data
are connected to the MACPACIC output.
7.12.4
When chrominance motion occurs, the encoder fades
down the high-pass luminance signal. In that event, the
motion detector in the decoder will switch the chrominance
part from intra frame average processing to the incoming
data.
handbook, full pagewidth
UV_ADC
(even)
OUTPUT SIGNALS
OUTPUT RANGE
The range is 0 ±90 in two’s complement format for
U and V.
0
MUX
LM
UV_TO_FM1
1
+
CS
from motion
detector
UVifa
0
MUX
UV_FM1
(odd)
LM
1
MUX
UV_FM1
MUX
UV_out
UV_ADC
UV_TO_FM4
to motion detector
Fig.9 Chrominance processing.
1996 Oct 28
20
MHA299
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
7.13
When the sampling grid is not optimum (e.g. shifted a little
in one field with respect to the other field), the cancellation
of both modulated colour signals will not be complete and
some residual XL will remain. The amount of residual XL
is proportional to the amplitude of the modulated colour
signal and to the following formula;
Chrominance motion detection
The PALplus system has two modes of operation.
These are called film mode, which is only used with film
sources, and camera mode which is applied for normal
50 Hz interlaced video sources. The motion detector is
only necessary in the camera mode because, in the
film mode, the two fields of a frame are sampled from the
same picture of the film.
sin ( π × f_sc × timing_error )
The timing error is determined by the type of circuitry used
for the sync/clock generation and by the amount of
noise/disturbance in the input signal (more
noise/disturbance generally leads to larger timing errors).
The chrominance motion detector has two input branches
(see Fig.10). One input branch is the intra frame average
of the actual frame, the other input branch is the intra
frame average signal of the previous frame. This signal is
delivered by the field memory FM4.
The intelligent residual cross-luminance reduction (IRXR)
tries to cancel this residual cross-luminance (XL), by
reducing the amount of YH depending of the amplitude of
the modulated colour signal.
Subtraction of the two intra frame average signals
generates the chrominance inter frame difference.
The saturation indication signal (SD) is generated by the
intra frame average signal of the actual frame with the help
of a look-up table (LUT). A horizontal interpolation filter
interpolates a 16 MHz saturation detection signal SD.
PAL averaging eliminates phase errors. This PAL
averaging can be switched off when the PAL delay line in
the colour decoder is active.
A look-up table (LUT) generates the motion signal from the
chrominance signal. A comparator generates a
chrominance control switch signal (CS). A horizontal
interpolation filter interpolates a 16 MHz motion signal.
The motion high-pass luminance control signal M_YL is
provided by another LUT.
7.14
Another LUT transforms the SD signal into the signal
SD_YL, which determines the amount of YH to be
reduced. Different characteristics curves of the LUT can
be selected either via SNERT (SEL_SD_YL) or
automatically depending on the measured noise value
(SelSdYl), see Fig.11 and Table 4.
Intelligent residual cross-luminance reduction
(IRXR)
The IRXR function can be disabled or enabled via SNERT
by the EN_IRXR bit.
The IRXR block diagram is illustrated in Fig.10.
The output signal YL is generated from the three YH
reduction signals SD_YL, M_YL and NM_YL.
This combination is performed with a minimum detection
circuit. The amount of YH that is allowed is the lowest of
the three input signals. Whenever one input signal
indicates a reason to reduce the YH, this should be
performed independently of the other input signals.
The MACP algorithm requires good stability of the
sampling clock between both fields, because samples
from both fields will be combined, in order to suppress
cross-colour and cross-luminance. Investigations with
currently used sync/clock circuitry have shown that the
stability of these clocks is not as good as it should be for
perfect performance of the MACP algorithm.
In the event of film mode the signals NM_YL (Fig.12 and
Table 5) and M_YL are over-written with the value 4.
Motion detector processing is not active for these signals
in the film mode. Such film overriding is not allowed for the
SD_YL signal, because the residual XL can occur in the
film mode as well as in the camera mode.
When a MACP signal is received the colour subcarrier trap
in the TDA9144 is bypassed and the input signal of the
SAA4996H still contains the modulated colour component.
The MACP technique always processes corresponding
lines of two successive fields (having an offset of
312 lines). These lines will have the same high-frequency
luminance information (YH) and inverted colour
information due to the phase/line relationship in PAL.
With an ideal sampling grid, the two inverted colour signals
will be cancelled completely by addition so that no
cross-luminance (XL) remains in the resulting picture.
1996 Oct 28
SAA4996H
21
1996 Oct 28
UV_FM4
UVifa
−
0
MUX
1
22
0
MUX
1
M
INTERPOLATION
FILTER
INTERPOLATION
FILTER
CS
LUT
M_YL
LUT
NAIRXR
0
MUX
1
SD' SD_YL
LUT
CS
SD'
M
FilmOn
0
MUX
1
FilmOn
0
MUX
1
EN_IRXR
0
4
SD_YL MUX
1
4
NM_YL
4
M_YL
Fig.10 Motion detector and intelligent residual cross-luminance reduction (IRXR).
SelSdYl
SEL_SD_YL (from SNERT)
LUT TO GENERATE SD
THE SATURATION
SIGNAL SD
PAL averaging in colour
decoder active
PAL
AVERAGING
IRXR
LUT TO GENERATE M
THE MOTION
SIGNAL M
PAL averaging in colour
decoder active
PAL
AVERAGING
MOTION DETECTOR
MHA298
MIN
YL
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
handbook, full pagewidth
Philips Semiconductors
Preliminary specification
SAA4996H
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
state machine
output
handbook, halfpage
SAA4996H
state machine
output
handbook, halfpage
3
2
2
MHA296
Fig.11 Generation of the signal SelSdYl.
Table 4
Measured Helper
Noise Zero (MHNZ)
MHA297
Fig.12 Generation of the signal NM_YL.
Measured luminance noise in black (MLNB)
MLNB
STATE MACHINE (OLD)
STATE MACHINE (NEW)
X
3
MLNB < SatYhThr1
SatYhThr1 ≤ MLNB < SatYhThr2
SatYhThr2 ≤ MLNB < SatYhThr3
SatYhThr3 ≤ MLNB < SatYhThr4
SatYhThr3 ≤ MLNB
Table 5
MacpYhThr3
0
Measured Luminance
Noise in Black (MLNB)
MacpYhThr1
SatYhThr4
SatYhThr3
SatYhThr2
SatYhThr1
0
MacpYhThr2
1
1
3
3
<3
2
≥2
2
<2
1
≥1
1
0
0
X
0
Generation of the signal NM_YL
MHNZ
MHNZ < MacpYhThr1
MacpYhThr1 ≤ MHNZ < MacpYhThr2
MacpYhThr2 ≤ MHNZ < MacpYhThr3
MacpYhThr3 < MHNZ
1996 Oct 28
STATE MACHINE (OLD)
STATE MACHINE (NEW)
NM_YL
X
2
4
2
2
4
<2
1
2
≥1
1
2
<1
0
0
X
0
0
23
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
handbook,
255 full pagewidth
line time
reference point = half amplitude
of the falling synchronisation slope
191
22 µs
121
31 µs
11 µs
mid grey set-up
black set-up
51
clamp level
16
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
MHA148
Fig.13 Digital representation of the reference signal in line 22 at the input of the PALplus decoder module.
handbook,
255 full pagewidth
line time
reference point = half amplitude
of the falling synchronisation slope
wide screen signalling bits
191
black level
reference
121
maximum negative
reference
61
10.5 µs
51
41 µs
16
0
10.83 µs
51 µs
clamp level
0
5
10
15
20
25
30
35
40
45
50
55
60
65
MHA149
Fig.14 Digital representation of the reference signal in line 23 at the input of the PALplus decoder module.
1996 Oct 28
24
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
handbook,
255 full pagewidth
line time
reference point = half amplitude
of the falling synchronisation slope
191
white level reference
30 µs
20 µs
black level
reference
10.5 µs
51
clamp level
16
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
MHA150
Note: There is no burst in line 623.
Fig.15 Digital representation of the reference signal in line 623 at the input of the PALplus decoder module.
handbook,
255 full pagewidth
white
191
181
121
mid grey set-up
16
0
61
black set-up
51
clamp level
CVBS (EBU colour bar with 100% saturation and
75% amplitude) with black set-up
base band helper with mid grey set-up
Fig.16 PALplus CVBS and helper input signal.
1996 Oct 28
25
MHA151
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
handbook, full pagewidth
SAA4996H
255
WHITE 191
BLACK 16
(clamp level) 0
MHA154
Fig.17 Non PALplus Y input signal.
handbook, full pagewidth
255
WHITE 191
BLACK 16
0
MHA155
Fig.18 Y output signal.
1996 Oct 28
26
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
handbook, full pagewidth
SAA4996H
255
198
128
58
16
0
MHA152
Fig.19 Helper output signal.
typical digital values
handbook, full pagewidth
127
90
60
30
0
–30
–60
–90
52 µs
12 µs
–128
EBU Colour Bar
MHA153
Fig.20 −(B − Y) input and output signal.
1996 Oct 28
27
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
handbook, full pagewidth
SAA4996H
typical digital values
+127
+90
+76
+14
0
−14
−76
−90
52 µs
12 µs
−128
EBU Colour Bar
MHA294
Fig.21 −(R − Y) input and output signal.
CLK_16
handbook,
full pagewidth
WE_FRONT
Y_ADC_0...7 XX
XX
Y0
Y1
Y2
Y3
Y4
Y5
Y838
Y839
XX
U_ADC_1
XX
XX
U70
U50
U30
U010
U74
U54
U3836
U1836
XX
U_ADC_0
XX
XX
U60
U40
U20
U00
U64
U44
U2836
U0836
XX
V_ADC_1
XX
XX
V70
V50
V30
V10
V74
V54
V3836
V1836
XX
V_ADC_0
XX
XX
V60
V40
V20
V00
V64
V44
V2836
V0836
XX
MHA163
Fig.22 Horizontal data input timing.
1996 Oct 28
28
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
handbook, full pagewidth
SAA4996H
CLK_16
CLK_32
Y_MA_0..7
XX
XX
XX
XX
Y0A
Y0B
Y1A
Y1B
Y2A
Y2B
Y3A
Y3B
Y4A
Y4B
U_MA_1
XX
XX
XX
XX
U70A U50A U30A U10A U60B U40B U20B U00B U64A U44A
U_MA_0
XX
XX
XX
XX
U60A U40A U20A U00A U70B U50B U30B U10B U74A U54A
V_MA_1
XX
XX
XX
XX
V70A V50A V30A V10A V60B V40B V20B V00B V64A V44A
V_MA_0
XX
XX
XX
XX
V60A V40A V20A V00A V70B V50B V30B V10B V74A V54A
MHA156
U60A
bit word field
Fig.23 Horizontal output signals, full PALplus module.
CLK_16
handbook,
full pagewidth
Y_MA_0...7
XX
Y0
Y1
Y2
Y3
Y4
Y5
Y838
Y839
XX
U_MA_1
XX
U70
U50
U30
U010
U74
U54
U3836
U1836
XX
U_MA_0
XX
U60
U40
U20
U00
U64
U44
U2836
U0836
XX
V_MA_1
XX
V70
V50
V30
V10
V74
V54
V3836
V1836
XX
V_MA_0
XX
V60
V40
V20
V00
V64
V44
V2836
V0836
XX
MHA157
Fig.24 Horizontal output signals, stand-alone MACPACIC.
1996 Oct 28
29
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
CLK_16
handbook,
full pagewidth
Y_FM1_0...7
XX
Y0
Y1
Y2
Y3
Y4
Y5
Y838
Y839
XX
U_FM1_1
XX
U70
U50
U30
U010
U74
U54
U3836
U1836
XX
U_FM1_0
XX
U60
U40
U20
U00
U64
U44
U2836
U0836
XX
V_FM1_1
XX
V70
V50
V30
V10
V74
V54
V3836
V1836
XX
V_FM1_0
XX
V60
V40
V20
V00
V64
V44
V2836
V0836
XX
MHA160
Fig.25 Horizontal timing, data from FM1.
CLK_16
handbook,
full pagewidth
Y_TO_FM1_0...7
XX
XX
XX
Y0
Y1
Y2
Y3
Y838
Y839
XX
U_TO_FM1_1
XX
XX
XX
U70
U50
U30
U010
U3836
U1836
XX
U_TO_FM1_0
XX
XX
XX
U60
U40
U20
U00
U2836
U0836
XX
V_TO_FM1_1
XX
XX
XX
V70
V50
V30
V10
V3836
V1836
XX
V_TO_FM1_0
XX
XX
V60
V40
V20
V00
V2836
V0836
XX
XX
MHA161
Fig.26 Horizontal timing, data to FM1 for stand-alone MACPACIC.
1996 Oct 28
30
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
CLK_16
handbook,
full pagewidth
U_FM4_1
XX
XX
XX
U70
U50
U30
U010
U3836
U1836
XX
U_FM4_0
XX
XX
XX
U60
U40
U20
U00
U2836
U0836
XX
V_FM4_1
XX
XX
XX
V70
V50
V30
V10
V3836
V1836
XX
V_FM4_0
XX
XX
XX
V60
V40
V20
V00
V2836
V0836
XX
MHA158
Fig.27 Horizontal timing, input signals from FM4.
CLK_16
handbook,
full pagewidth
U_TO_FM4_1
XX
XX
XX
U70
U50
U30
U010
U3836
U1836
XX
U_TO_FM4_0
XX
XX
XX
U60
U40
U20
U00
U2836
U0836
XX
V_TO_FM4_1
XX
XX
XX
V70
V50
V30
V10
V3836
V1836
XX
V_TO_FM4_0
XX
XX
XX
V60
V40
V20
V00
V2836
V0836
XX
MHA159
Fig.28 Horizontal timing, output signals to FM4.
1996 Oct 28
31
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
FIELD A
handbook, full pagewidth
line number
21
22
23
24
black and mid grey set-up reference line
reference signals
wide screen signalling bits
helper (36 lines)
('black band')
59
60
letter box (215 lines)
274
275
helper (36 lines)
('black band')
310
311
FIELD B
335
336
helper (36 lines)
('black band')
371
372
letter box (215 lines)
586
587
helper (36 lines)
('black band')
622
623
624
reference signals
MHA147
Fig.29 PALplus frame.
1996 Oct 28
32
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
7.15
The rising edge of WE_FRONT marks the horizontal
location of the first active input data of MACPACIC.
Control
The control part (see Fig.2) generates all necessary
internal control signals for the MACPACIC, the external
control signals for the field memories FM1 to FM4 and the
control signals for the VERIC. All of these signals are
derived from the mode bits transmitted via the SNERT
interface or from the reference input pins.
7.15.1
The signal WE_MA defines the horizontal and vertical
active area in which the first field memory (FM5) of the
succeeding 100 Hz feature box stores incoming data.
The signal WE_MA is generated by comparing (via the
SNERT interface) the transmitted start and stop values
with the values of the display line counter and the pixel
counter 1.
INPUT REFERENCE SIGNALS
The horizontal reference signal is the rising edge of the
CLAMP input pulse generated by the 100 Hz memory
controller (see Fig.30). The rising edge of WE_FRONT
defines the first active horizontal sample of the incoming
data Y_FRONT. The vertical reference signal is the rising
edge of VA_FRONT (see Fig.32), derived from the
synchronisation IC (e.g. TDA9144).
The pixel counter 2 is preset with the rising edge of
WE_FRONT in such a way that the counter has the value
‘1’ when the first active input data pixel is valid at the
Y, UV_ADC input of MACPACIC. This counter is a 10-bit
modulo 1024 counter clocked with CLK_16I.
7.15.2.1
For PALplus input signals line 24 is the first processed line
related to VA_FRONT. When MACP or standard input
signals are used, line 21 is the first processed line related
to VA_FRONT.
7.15.2
Memory control
The output of pixel counter 2 is used to generate the
horizontal read and write enable signals for FM1 and FM4
and the write enable signals for the field memories FM2
and FM3. The read cycle for FM2 and FM3 is controlled by
the VERIC.
FUNCTIONAL DESCRIPTION
The horizontal read and write signals are different for the
full PALplus module, for stand-alone MACPACIC and for
the odd and even fields. Therefore, the signals IVericN and
EVEN_FIELD are also input to the pixel decoder.
The acquisition line counter (ACQ) is preset with the
delayed rising edge of VA_FRONT (see Fig.2). With the
‘VA_FRONT Delay’ circuit it is possible to shift the rising
edge of VA_FRONT in multiples of CLK_16 clock periods.
This feature is necessary for unambiguous odd/even field
detection. The delay can be set via the SNERT interface.
The output of the acquisition line counter is used to
generate the vertical part of the read and write enable
signals for FM1 and FM4 and the vertical part of the write
enable signals for the field memories FM2 and FM3.
The vertical read cycle for FM2 and FM3 is controlled by
the VERIC.
The ACQ line counter is preset with logic 1 at the
beginning of the odd and even fields. The counter is
enabled with the rising edge of the clamp signal.
The display line counter (DSP) is used in the event of a
stand-alone MACPACIC (IVericN = 1) and is also preset
with the delayed rising edge of VA_FRONT. If VERIC is
available the field length measurement is active.
The display line counter is preset at the beginning of a
displayed odd and even field with the rising edge of VA_AI
set to logic 1.
The horizontal and vertical component of the read and
write enable signals are different for the full PALplus
module and for the stand-alone MACPACIC. The line
values for the memory controlling are shown in Tables 6,
7 and 8.
The pixel counter 1 is preset with the rising edge of the
CLAMP pulse. The counter is clocked with the 16 MHz
clock signal CLK_16I.
1996 Oct 28
SAA4996H
33
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
handbook, full pagewidth
VIDEO
INPUT FROM
TDA9144
CLAMP
tWE_F
WE_FRONT
MHA144
tWE_F: CLAMP phase to WE is programmable via SNERT-bus.
Fig.30 Timing diagram of the horizontal reference input signals.
1996 Oct 28
34
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
Table 6
SAA4996H
Pixel values for horizontal memory control
EVEN_FIELD
IVericN
H_WE_FM1
H_RE_FM1
H_WE_FM2
H_WE_FM3
H_WE_FM4
H_RE_FM4
0
0
0 to 839
−
−
−
−
−
0
1
2 to 841
24 to 863
−
−
−
−
1
0
−
0 to 839
27 to 866
27 to 866
9 to 848
0 to 839
1
1
26 to 865
0 to 839
−
−
9 to 848
0 to 839
V_RE_FM1
V_WE_FM2
V_WE_FM3
V_RE_FM4
V_WE_FM4
Table 7
Line values for vertical memory control, PALplus signals
EVEN_FIELD
IVericN
V_WE_FM1
0
0
21 to 311
−
−
−
−
−
0
1
21 to 311
21 to 311
−
−
−
−
1
0
−
20 to 310
24 to 59
167 to 274
60 to 166
275 to 310
21 to 311
21 to 311
1
1
22 to 312
20 to 310
−
−
21 to 311
21 to 311
Table 8
Line values for vertical memory control, MACP and standard signals
EVEN_FIELD
IVericN
V_WE_FM1
V_RE_FM1
V_WE_FM2
V_WE_FM3
V_RE_FM4
V_WE_FM4
0
0
0
1
21 to 311
−
−
−
−
−
21 to 311
21 to 311
−
−
−
−
1
0
−
20 to 310
21 to 166
167 to 311
21 to 311
21 to 311
1
1
22 to 312
20 to 310
−
−
21 to 311
21 to 311
The horizontal and vertical memory control signals are
combined in the H/V logic to generate the memory read
and write signals.
7.15.2.2
The signal HREF_MA is generated by delaying the
CLAMP input signal two clocks CLK_16. The HREF_MA
signal is used in the VERIC as a clock pulse for the internal
line counter. The timing is illustrated in Fig.34.
In all modes, except the MultiPIP mode, the signal
VA_RES is used as a reset signal for the field memories
FM1 to FM4 (RSTW_FM23 and RST_FM14). If the
MultiPIP mode is selected, the signal VA_AI is an input
signal generated by an external memory controller. In this
event the signal VA_AI_DIFF is used as RSTW_FM23.
The signal WE_FM2 is set to logic 1 and all other read and
write enable signals are set to logic 0. If the stand-alone
MACPACIC and MultiPIP mode is selected, all memory
control signals are set to logic 0.
7.15.2.3
VERIC control output signals
In the VERIC control decoder of MACPACIC the output
signals FILM and INTPOL are generated as shown in
Table 9.
The output pins 46 to 48 have different output signals
depending on the environment in which MACPACIC is
used. If it is part of a full PALplus module these pins deliver
bits of chrominance data, in the stand-alone MACPACIC
mode they output memory control signals
(see Chapter “Pinning”). Selection of either mode is
performed by the control signal IVericN.
1996 Oct 28
The output signal HREF_MA
35
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
Table 9
SAA4996H
Generation of the signals FILM and INTPOL
22Valid
FilmOn
Mpip
HlpM0
HlpM1
FILM
INTPOL
1
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
1
0
0
0
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
X
X
1
X
X
1
0
7.15.2.4
The odd/even field detection can be inverted by the
SNERT control bit InvO/E.
Field length measurement
On the full PALplus module the field length is measured in
the MACPACIC.
It is also possible to define the EVEN_FIELD signal by
software via a SNERT transmission.
The ACQ line counter counts the lines between two
succeeding vertical pulses. The one-line-long vertical
output signal VA_AI has a delay of 1.5 fields with respect
to the delayed VA_FRONT input signal and has the same
phase relationship to the CLAMP input signal for various
video input signals (VCR, NTSC).
7.15.2.6
The signals VA_FRONT and VA_AI have bidirectional
functions. In all modes, except the MultiPIP mode, the pin
VA_FRONT is an input pin and the pin VA_AI is an output
pin. If the MultiPIP mode is selected the pin VA_AI is an
input pin and the signal is connected to the VA_FRONT pin
which now becomes an output pin (see Fig.2 and Fig.35).
For the stand-alone MACPACIC the 2.5 H signal
VA_FR_DEL is selected by the control signal IVericN as
the vertical reference output signal VA_AI.
7.15.2.5
7.15.3
Field detection
To detect the current odd or even field, the location of the
delayed VA_FRONT (VA_RES) input signal inside a line
has to be located.
SNERT INTERFACE (SEE APPLICATION NOTE
AN95XXX)
In the SNERT interface the external signals SNERT_CL
and SNERT_DA are processed to address and data.
A synchronisation to the bus performed with the reset
signal SNERT_RST. The transmitted data is valid with the
next rising edge of SNERT_RST.
For a PALplus video input signal the output signal
EVEN_FIELD is generated by enabling a register with the
VA_RES signal, which has the MSB of the pixel counter 2
at the D input.
The block diagram and the data, clock and reset timing of
the SNERT interface are shown in Fig.3 and Fig.36.
In the bypass or MultiPIP mode the toggle function of the
register is active.
1996 Oct 28
Pins VA_FRONT and VA_AI
36
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
7.15.3.1
Serial interface protocol
7.15.3.2
Power-on state: After power-on the serial interface is in
an unknown state. The information in the actual data
registers is random. When signals are applied to
SNERT_CL and SNERT_DA in this state, the behaviour is
unpredictable.
Special SNERT transmission requirements
EVEN_FIELD definition:
After switching on the MACPACIC, the EVEN_FIELD
output signal toggles.
When the EVEN_FIELD signal accidentally toggles in the
right way (EVEN_FIELD = 0, odd field) and when a
PALplus input signal is present, the line 22 is detected.
Then the internal field detection is active and the normal
data processing starts up.
Initialization state: After power-on, or in any other state,
the initialization state is entered after the rising edge of the
signal SNERT_RST. The SNERT clock counter C1 is
reset with the rising edge of SNERT_RST. The data
registers remain loaded with the last transmitted values.
When the EVEN_FIELD signal toggles in the wrong way
(EVEN_FIELD = 0, even field), line 22 will never be
detected and the field detection remains in this wrong
behaviour.
Address reception state: After reset the address
reception state is entered. On each negative edge of
SNERT_CL the next data bit from SNERT_DA is shifted
into the input shift register. The counter is incremented
with each rising edge of SNERT_CL. After the 8th negative
edge of SNERT_CL the Address Latch Enable (ALE)
pulse is generated. With this enable pulse the contents of
the shift register is loaded into the address register. If an
address in the range 50H to 64H, 67H or 68H is decoded,
one of the 8-bit wide input data registers is selected.
Solution: After switching on the MACPACIC or after
switching into PALplus or MACP mode, the EVEN_FIELD
output signal has to be defined by the control bits
‘EnPreEvFld’ and ‘PreEvFld’ of the control 6 SNERT
register.
Luminance offset hysteresis control:
For luminance offset control a hysteresis function is
applied to the measured luminance offset. The hysteresis
function is controlled by the three black offset hysteresis
control bits BOH0, BOH1 and BOH2 transmitted via
SNERT (control 5 data register).
Data reception state: If a valid address is received, the
next eight bits on SNERT_DA are considered as data bits.
When the 8 data bits have been shifted into the shift
register the counter enables the loading of the data word
in one of the 23 data registers in combination with the
decoded address.
To guarantee the correct hysteresis function, the following
software actions are necessary:
There are three data register banks;
First the hysteresis has to be set to zero via SNERT
(BOH = 0). After a PALplus input signal is detected (line 22
is valid), the actual black offset is measured in the next
frame. During this time (40 ms) the software remains in the
stand-by position. One of the possible hysteresis values
can then be transmitted via SNERT.
• The actual data register bank
• The acquisition data register bank
• The synchronizing register bank.
After a SNERT transmission is completed another
SNRST pulse must follow in order to enable the
acquisition registers and make the data valid.
The synchronizing registers are enabled with the signals
‘line2_odd_every_field’ respectively ‘line2_every_field’,
which are related to the vertical reference input signal
VA_FRONT.
Data send state: If the transmitted address is 65H or 66H,
the ‘send_rcv’ signal defines the SNERT_DA pin as an
output and, with the positive edge of the next
8 SNERT_CL pulses generated by the microcontroller, the
data output register is read out.
1996 Oct 28
SAA4996H
37
1996 Oct 28
38
Control3
Control4
Control5
Control6
65
66
67
68
Interlace
EnPreEvFld
2. Don’t care (bits can be logic 0 or logic 1).
1. Bits not valid.
SelSdYl1
X(1)
BOH1
X(1)
X(1)
BOH2
FixHlp2
IrxrThr46
IrxrThr36
IrxrThr26
IrxrThr16
MaThr36
MaThr26
MaThr16
HlpThr56
HlpThr46
HlpThr36
HlpThr26
HlpThr16
StpV16
StpV06
StrtV16
FixHlp3
IrxrThr47
IrxrThr37
IrxrThr27
IrxrThr17
MaThr37
MaThr27
MaThr17
HlpThr57
HlpThr47
HlpThr37
StpV17
StpV07
StrtV17
StrtV06
StpH6
StrtH6
VaDel2
MacpOn
D6
PreEvFld
BOH0
SelSdYl0
X(1)
FixHlp1
IrxrThr45
IrxrThr35
IrxrThr25
IrxrThr15
MaThr35
MaThr25
MaThr15
HlpThr55
HlpThr45
HlpThr35
HlpThr25
HlpThr15
StpV15
StpV05
StrtV15
StrtV05
StpH5
StrtH5
VaDel1
HlpM1
D5
VAA0
X(2)
X(2)
NmYl0
623Valid
FixMain3
IrxrThr43
IrxrThr33
IrxrThr23
IrxrThr13
MaThr33
MaThr23
MaThr13
HlpThr53
HlpThr43
HlpThr33
HlpThr23
HlpThr13
StpV13
StpV03
StrtV13
StrtV03
StpH3
StrtH3
FastTest
FilmOn
D3
VAA1
NmYl1
22Valid
FixHlp0
IrxrThr44
IrxrThr34
IrxrThr24
IrxrThr14
MaThr34
MaThr24
MaThr14
HlpThr54
HlpThr44
HlpThr34
HlpThr24
HlpThr14
StpV14
StpV04
StrtV14
StrtV04
StpH4
StrtH4
VaDel0
HlpM0
D4
DATA BYTE
X(2)
SEL_SD_YL1
Rha/Rhb2
23Valid
FixMain2
IrxrThr42
IrxrThr32
IrxrThr22
IrxrThr12
MaThr32
MaThr22
MaThr12
HlpThr52
HlpThr42
HlpThr32
HlpThr22
HlpThr12
StpV12
StpV02
StrtV12
StrtV02
StpH2
StrtH2
WeShift16_1
MotVis1
D2
X(2)
SEL_SD_YL0
Rha/Rhb1
IVericN
FixMain1
IrxrThr41
IrxrThr31
IrxrThr21
IrxrThr11
MaThr31
MaThr21
MaThr11
HlpThr51
HlpThr41
HlpThr31
HlpThr21
HlpThr11
StpV11
StpV01
StrtV11
StrtV01
StpH1
StrtH1
WeShift16_0
MotVis0
D1
X(2)
NAIRXR
Rha/Rhb0
IMacpacicN
FixMain0
IrxrThr40
IrxrThr30
IrxrThr20
IrxrThr10
MaThr30
MaThr20
MaThr10
HlpThr50
HlpThr40
HlpThr30
HlpThr20
HlpThr10
StpV10
StpV00
StrtV10
StrtV00
StpH0
StrtH0
EnIRXR
InvO/E
D0
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
Notes
IrxrThr4
FixHlpMain
IrxrThr3
62
64
IrxrThr2
63
IrxrThr1
61
HlpRedThr5
5C
60
HlpRedThr4
5B
MacpYhThr3
HlpRedThr3
5F
HlpRedThr2
59
5A
MacpYhThr1
HlpRedThr1
58
MacpYhThr2
WeStpV1
57
5E
HlpThr27
WeStpV0
56
5D
HlpThr17
WeStrtV1
55
StrtV07
StpH7
StrtH7
WeStpH
WeStrtH
52
Mpip
Preset
WeStrtV0
Control2
51
54
Control1
50
D7
53
FUNCTION
ADDRESS
(HEX)
7.15.3.3 Address and data overview
Table 10 Address and data overview
Address 50H to 64H, 67H and 68H contains write data (data from microprocessor); address 65H and 66H contains read data (data to microcontroller).
Philips Semiconductors
Preliminary specification
SAA4996H
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
7.15.3.4 Command explanation
Table 11 Control1
ADDRESS
(HEX)
R/W
BIT
NAME
50
W
7
Preset
FUNCTION
0: normal processing
1: abandon the recursive measurement loops and load the circuits
with actual video data
6
MacpOn
5, 4
HlpM1 and HlpM0
0: Motion Adaptive Colour Plus decoding not activated
1: Motion Adaptive Colour Plus decoding activated
00: bypass mode VERIC
01: vertical up-conversion without use of helper
10: vertical enhancement with adaptive helper processing
11: vertical enhancement with helper amplitude and main
reference via SNERT interface
3
FilmOn
0: camera mode activated
1: film mode activated
2, 1
MotVis1 and MotVis0 00: don’t show motion decisions
01: show Y motion decisions
10: show C motion decisions
11: show M motion decisions
0
InvO/E
0: don’t invert EVEN_FIELD definition
1: invert EVEN_FIELD definition
Table 12 Control2
ADDRESS
(HEX)
R/W
BIT
NAME
51
W
7
Mpip
FUNCTION
0: MultiPIP mode not active
1: MultiPIP with the help of PIP module is activated; VA_AI is set
to input and VA_FRONT to output; the signal at the WE_FRONT
pin is used
6 to 4
VaDel2, VaDel1 and
VaDel0
internal delay of VA_FRONT in multiples of CLK_16 clock periods;
range: [0, 64, 128 to 448] CLK_16 periods; this feature is required
for unambiguous Odd/Even field detection
3
FastTest
0: normal mode: activating new SNERT commands at frame
boundaries related to VA_FRONT (address 50H to 57H and 68H)
1: activating new SNERT commands immediately
2, 1
WeShift16_1 and
WeShift16_0
0
EnIRXR
shift of WE_MA of 0 to 3 16 MHz samples related to the positive
edge of CLAMP
0: disable Intelligent Residual cross-luminance Reduction
1: enable Intelligent Residual cross-luminance Reduction
1996 Oct 28
39
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
Table 13 Programming of WE_MA
ADDRESS
(HEX)
R/W
BIT
NAME
52
W
7 to 0
WeStrtH
distance between rising edge of CLAMP and rising edge of WE_MA in
multiples of 4 CLK_16 periods
53
W
7 to 0
WeStpH
distance between rising edge of CLAMP and falling edge of WE_MA in
multiples of 4 CLK_16 periods
54
W
55
W
7 to 0 WeStrtV0 number of lines between rising edge of VA_AI (VA_FRONT) and first active
7 to 0 WeStrtV1 WE_MA line
56
W
57
W
FUNCTION
7 to 0 WeStpV0 number of lines between rising edge of VA_AI (VA_FRONT) and first
7 to 0 WeStpV1 non-active WE_MA line
WeStrtH, WeStpH, WeStrtV and WeStpV:
signals WeShift16_0 and WeShift16_1 shifts the active
horizontal area over 0 to 3 clock periods of 16 MHz. In this
case the positive as well as the negative edge will shift
over the same amount of samples.
The horizontal reference is the rising edge of the CLAMP
signal. The vertical reference is the rising edge of the
VA_FRONT signal. This signal is set via software. Signals
WeStrtH and WeStpH define the horizontal active area.
Signals (WeStrtV0 and WeStrtV1) and
(WeStpV0 and WeStpV1) mark the vertical active area.
The least significant bit of the start and stop address is also
the most significant bit of the data.
WeStrtV0 indicates the vertical start addresses 1 to 256
and WeStrtV1 indicates the addresses 257 to 512.
The vertical start at line 1 is not allowed. WeStpV0
indicates the vertical stop addresses 1 to 256 and
WeStpV1 indicates the addresses 257 to 512.
Because the number of 16 MHz samples in a line is 1024,
and one data byte can only define 256 positions, the
horizontal start and stop positions are defined with a
4 MHz resolution. To reach the full 16 MHz resolution the
If WeStrtH = WeStpH and WeStrtV0 = WeStpV0 or
WeStrtV1 = WeStpV1 the output control signal WE_MA is
switched to a LOW level and no data will be written into the
succeeding module (still picture).
WeStrtH
handbook, full pagewidth
WeStpH
WeStrtV
WeStpV
MHA145
Fig.31 Boundaries of the WE_MA signal.
1996 Oct 28
40
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
Table 14 Helper Reduction Thresholds
ADDRESS
(HEX)
R/W
58
W
59
W
5A
W
7 to 0 HlpRedThr1 5 thresholds defining the ranges in which the 5 modes for adaptive helper
7 to 0 HlpRedThr2 reduction will be applied (inclusive hysteresis); this adaptivity prevents
from artefacts of helper noise break through
7 to 0 HlpRedThr3
5B
W
7 to 0 HlpRedThr4
5C
W
7 to 0 HlpRedThr5
BIT
NAME
FUNCTION
Table 15 Definition of Y_HP Reduction Thresholds related to MACP
ADDRESS
(HEX)
R/W
5D
W
5E
W
7 to 0 MacpYhThr1 3 thresholds defining the ranges in which the 3 modes for adaptive Yhp
7 to 0 MacpYhThr2 reduction will be applied (inclusive hysteresis)
5F
W
7 to 0 MacpYhThr3
BIT
NAME
FUNCTION
Table 16 Definition of Y_HP Reduction Thresholds related to PLL disturbances
ADDRESS
(HEX)
R/W
BIT
NAME
FUNCTION
60
W
7 to 0
IrxrThr1
61
W
7 to 0
IrxrThr2
62
W
7 to 0
IrxrThr3
4 thresholds defining the ranges in which the 4 modes for the intelligent
residual cross-luminance reduction will be applied; this adaptivity prevents
from artefacts caused by the PLL disturbance
63
W
7 to 0
IrxrThr4
Table 17 Definition of fixed helper gain and relative main amplitude (FixHlpMain)
ADDRESS
(HEX)
R/W
BIT
NAME
64
W
7 to 4
FixHlp3,
FixHlp2,
FixHlp1,
FixHlp0
3 to 0
FixMain3,
FixMain2,
FixMain1,
FixMain0
1996 Oct 28
FUNCTION
definition of helper gain
definition of relative main amplitude (letter box)
41
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
Table 18 Control3
ADDRESS
(HEX)
R/W
BIT
NAME
65
R
7 to 5
X
4
22Valid
FUNCTION
no function
0: correct MACP and/or helper processing is not possible and is
automatically switched off; helpers are blanked and MACPACIC is forced
into camera mode; reference levels of line 22 are not valid
1: correct MACP and/or helper processing could be possible; reference
levels of line 22 are valid
3
623Valid
0: correct helper processing is not possible and is automatically switched
off; reference values of line 623 are not valid
1: correct helper processing could be possible; reference values of line 623
are valid
2
23Valid
0: correct helper processing is not possible and is automatically switched
off; reference values of line 23 are not valid
1: correct helper processing could be possible; reference values of line 23
are valid
1
IVericN
0: VERIC available
1: VERIC not available
0
IMacpacicN 0: MACPACIC available
1: MACPACIC not available
Table 19 Control4
ADDRESS
(HEX)
R/W
BIT
NAME
66
R
7
X
6, 5
SelSdYl1,
SelSdYl0
4, 3
NmYl1,
NmYl0
2 to 0
1996 Oct 28
FUNCTION
no function
indication of the Y_HP reduction factor, which is further saturation
dependent; these are deduced from the noise within full band (line 623)
indication of the Y_HP reduction factor deduced from the noise within the
helper (line 23)
Rha/Rhb2, indication of the amount of helper bandwidth reduction and helper amplitude
Rha/Rhb1, reduction; these are deduced from the noise within the helper (line 23)
Rha/Rhb0
42
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
Table 20 Control5
ADDRESS
(HEX)
R/W
BIT
NAME
67
W
7 to 5
BOH2, BOH1,
BOH0
FUNCTION
selection of black offset hysteresis:
000: 0
001: ±1
010: ±2
011: ±3
100: ±4
101: ±5
110: ±6
111: fixed black offset (51)
4, 3
VAA1 and
VAA0
2, 1
selection of the coefficients of the luminance vertical anti-alias filter
(DEC_Y_VAA): see Table 21
SEL_SD_YL1, selection of IRXR characteristics (NAIRXR = 0): see Table 22
SEL_SD_YL0
0
NAIRXR
0: IRXR table selection dependent of SEL_SD_YL
1: noise adaptive IRXR table selection
Table 21 DEC_Y_VAA
SELECTION OF THE LUMINANCE VERTICAL ANTI-ALIAS FILTER (DEC_Y_VAA)
VAA1
VAA0
FIELD
COEFF1
COEFF2
COEFF3
0
0
odd
2
7
−1
0
0
even
−1
7
2
0
1
X
2
4
2
1
0
X
3
2
3
1
1
X
4
0
4
Table 22 IRXR
SELECTION OF IRXR CHARACTERISTICS (NAIRXR = 0)
SEL_SD_YL
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
4
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
1
4
4
4
3
2
1
0
0
0
0
0
0
0
0
0
0
2
4
4
4
4
4
3
3
2
2
1
1
0
0
0
0
0
3
4
4
4
4
4
4
4
3
3
2
2
1
0
0
0
0
1996 Oct 28
43
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
Table 23 Control6
ADDRESS
(HEX)
R/W
BIT
NAME
68
W
7
Interlace
FUNCTION
0: incoming video signal is defined as ‘non interlaced’
1: incoming video signal is defined as ‘interlaced’
6
EnPreEvFld 0: EVEN_FIELD signal defined internally
1: EVEN_FIELD signal defined by SNERT transmission: PreEvFld
5
PreEvFld
0: incoming field is defined as ‘Odd’
1: incoming field is defined as ‘Even’
4 to 0
8
X
no function
TEST
8.1
Boundary scan test
Boundary Scan Test (BST) is supported. See boundary scan specification: “IEEE Standard 1149.1 - 1990, IEEE standard
test access port and boundary scan architecture”.
8.1.1
IDENTIFICATION CODES
The PALplus ICs MACPACIC and VERIC are equipped with BST identification registers. The identification codes and
their meaning are shown in Tables 24 and 25.
Table 24 Identification codes
VERSION
COMPONENT
MANUFACTURER
FIXED
IDENTIFICATION
3322
22222 22211 11111 1
11000000000
0
−
1098
76543 21098 76543 2
10987654321
0
−
MACPACIC
0001
01101 00001 00011 0
00000010101
1
1684602B
VERIC
0001
10110 00101 10010 0
00000010101
1
1B16402B
IC
Table 25 Code parts
BITS
NAME
DESCRIPTION
31 to 28
version number
start with 1 and increment every redesign
27 to 12
component
first 3 characters of name
11 to 1
manufacturer
JEDEC code for PHILIPS
0
fixed
1
1996 Oct 28
44
1996 Oct 28
45
VA_RES
VA_FRONT
CVBS
VA_RES
VA_FRONT
Z312
1/2
H
Z313
Z625
Z1
H
Z314
Z315
2.5 H
Z2
Z3
Z316
Z4
Z317
Z318
even field
Z5
odd field
Z6
Z319
Z22
Z23
Z24
Z337
MHA139
Z25
helper
reference burst
Z336
signalling
bits
Z335
mid grey
black set-up set-up
Fig.32 Timing of the vertical synchronisation pulse (VA_FRONT) and the delayed vertical signal (VA_RES).
Z310
Z624
Z311
Z623
odd field
Z622
Z309
Z621
Z308
Z620
main white
reference
handbook, full pagewidth
video input signal
of TDA9144
CVBS
helper signal
even field
main black
reference
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
1996 Oct 28
46
943
1023
944
0
945
1
60
1003 1004
tWE_F
59
1023
79
Y0
1
81
handbook, full pagewidth
Y1
2
82
838
918
839
919
840
920
Y836 Y837 Y838 Y839
837
917
Fig.33 Pixel timing of the input signals CLAMP and WE_FRONT.
0
80
841
921
952
953
1022 1023
954
0
MHA143
955
1
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
tWE_F: CLAMP phase to WE_RES (WE_FRONT) is programmable via SNERT-bus
YUV_ADC
PC2
WE_FRONT
PC1
CLAMP
CLK_16
Philips Semiconductors
Preliminary specification
SAA4996H
1996 Oct 28
47
tCLP_HRMA
60 x CLK_16
tPD
handbook, full pagewidth
tWE_D
Y0a
Y0b
Y1a
Y1b
Y838a Y838b Y839a Y839b
Fig.34 Pixel timing of the output signals HREF_MA and WE_MA (full PALplus module and stand-alone MACPACIC).
60 x CLK_16
MHA142
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
tCLP_HRMA: delay CLAMP to HREF_MA, 2 × CLK_16B2
tPD: processing delay
tWE_D: data write enable delay
YUV_MA
WE_MA
WE_FRONT
HREF_MA
CLAMP
CLK_32B3
CLK_16B2
Philips Semiconductors
Preliminary specification
SAA4996H
1996 Oct 28
48
2
3
157
158
1.5 fields
314
313
2
even field
1
3
155
156
157
odd field
312 313 1
2
3
MHA141
4
Fig.35 Horizontal timing of the input signal VA_FRONT and the output signal VA_AI (full PALplus module, all input signals except MultiPIP).
156
even field
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
td_VA_FRONT: this delay is defined via SNERT-bus
VA_AI
312 313 1
td_VA_FRONT
odd field
handbook, full pagewidth
LC_ACQ
CLAMP
EVEN_FIELD
VA_FR_DEL
VA_FRONT
Philips Semiconductors
Preliminary specification
SAA4996H
1996 Oct 28
49
COUNTER_OUT
NEDGE_SNERT_CL
PEDGE_SNERT_CL
DLE
ALE
xx
0
≥3 µs
1
3
4
5
A5
6
A6
7
A7
MSB
8
≥4 µs
D0
LSB
9
D1
10
D2
11
D3
12
D4
data
13
D5
14
D6
15
D7
0
MHA140
MSB
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
Fig.36 SNERT interface; data, clock and reset timing.
2
A4
A3
A2
A0
A1
address
LSB
handbook, full pagewidth
SNERT_DA
SNERT_CL
SNERT_RST
Philips Semiconductors
Preliminary specification
SAA4996H
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
9 DC CHARACTERISTICS
Tj = 0 to 125 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
4.75
5.00
5.25
V
IDD
supply current
−
80
−
mA
IDD(PD)
quiescent supply current
−
−
100
µA
all inputs to VDD or VSS
Inputs
VIL
LOW level input voltage
0
−
0.8
V
VIH
HIGH level input voltage
2.0
−
VDD
V
II
input current
−
−
1.0
µA
−
−
0.1
V
VDD − 0.1
−
−
V
Outputs and 3-state
IO = 20 µA
VOL
LOW level output voltage
VOH
HIGH level output voltage IO = 20 µA
Outputs Y_TO_FM1, UV_TO_FM1, Y_MA, UV_MA, WE_MA, HREF_MA, UV_TO_FM4, EVEN_FIELD, INTPOL,
FILM, RST_FM14, WE_FM1, RE_FM1, WE_FM4, RE_FM4 and CLK_16B1
IOL
LOW level output current
IOH
HIGH level output current VO = VDD − 0.5 V
VO = 0.5 V
4
−
−
mA
4
−
−
mA
Outputs CLK_32B1, CLK_32B2 and CLK_16B2
IOL
LOW level output current
IOH
HIGH level output current VO = VDD − 0.5 V
VO = 0.5 V
8
−
−
mA
8
−
−
mA
Outputs CLK_32B3 and CLK_16B3
IOL
LOW level output current
IOH
HIGH level output current VO = VDD − 0.5 V
VO = 0.5 V
12
−
−
mA
12
−
−
mA
−
−
10
µA
3-state TDO_MA, SNERT_DA, VA_FRONT and VA_AI
IZ
1996 Oct 28
input current
50
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
tr
handbook, full pagewidth
SAA4996H
tf
90 %
CLK
50 %
10 %
th
DATA
tl
Dn
XX
Dn + 1
toh
tih
tod
tsu
MHA146
Data input: CLK = CLK_16.
Data output: CLK = CLK_16 for stand-alone MACPACIC and CLK = CLK_32 for full PALplus module.
Fig.37 Clock to data timing.
10 AC CHARACTERISTICS
Tj = 0 to 125 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock CLK_32
Tcy
cycle time
28.1
−
−
ns
tr
rise time
2
−
4
ns
tf
fall time
2
−
4
ns
th
HIGH time
9.2
−
−
ns
tl
LOW time
9.2
−
−
ns
Clock CLK_16
TCY
cycle time
56.2
−
−
ns
tr
rise time
2
−
4
ns
tf
fall time
2
−
4
ns
th
HIGH time
20.5
−
−
ns
tl
LOW time
20.5
−
−
ns
all data inputs
6
−
−
ns
CLK_16 w.r.t. CLK_32
4.5
−
−
ns
Input set-up time
tsu
1996 Oct 28
set-up time
51
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SYMBOL
PARAMETER
SAA4996H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input hold time
input hold time
tih
all data inputs
3
−
−
ns
CLK_16 w.r.t. CLK_32
3.5
−
−
ns
Outputs (CL = 15 pF)
CLK_16B1, CLK_16B2 AND CLK_16B3 (RISING)
toh
hold time
6
−
−
ns
tod
delay time
−
−
17
ns
CLK_16B1, CLK_16B2 AND CLK_16B3 (FALLING)
toh
hold time
9
−
−
ns
tod
delay time
−
−
24
ns
CLK_32B1, CLK_32B2 AND CLK_32B3 (RISING)
toh
hold time
6
−
−
ns
tod
delay time
−
−
17
ns
CLK_32B1, CLK_32B2 AND CLK_32B3 (FALLING)
toh
hold time
6
−
−
ns
tod
delay time
−
−
17
ns
Outputs YUV_TO_FM1, RST_FM14, WE_FM1, RE_FM1, WE_FM4, RE_FM4, HREF_MA, WE_MA, VA_AI,
VA_FRONT and YUV_MA (CLK_16; CL = 15 pF)
toh
hold time
12
−
−
ns
tod
delay time
−
−
38
ns
Outputs (CLK_32; CL = 15 pF; note 1)
YUV_MA
toh
hold time
13
−
−
ns
tod
delay time
−
−
39
ns
RSTW_FM23, WE_FM2 AND WE_FM3
toh
hold time
12
−
−
ns
tod
delay time
−
−
38
ns
Note
1. 32 MHz output signals are related to the output clock signals CLK_32B1 and CLK_32B3.
10.1
Clock buffers
MACPACIC supplies the clocks for VERIC and the field memories on the PALplus module. Therefore the input clocks
CLK_16 and CLK_32 are buffered and output as CLK_16B1 to CLK_16B3 and CLK_32B1 to CLK_32B3. The clock
distribution is shown in Fig.5.
1996 Oct 28
52
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
11 LIST OF ABBREVIATIONS
Table 26 Abbreviations used in document
SYMBOL
DESCRIPTION
ALE
Address Latch Enable
BB
Black Bands (above and below letter box picture)
BOH
Black Offset Hysteresis (see Table 20)
CLP_DIFF
Positive Edge of CLAMP Signal
DLE
Data Latch Enable
EnlRXR
Enable IRXR (see Table 12)
EnPreEvFld
Enable Preset Even Field (see Table 23)
FixHlpMain
Fix gain of Helper and Main Amplitude (see Table 17)
HlpM
Helper mode (see Table 11)
HlpRedThr
Helper Reduction Threshold (see Table 14)
H_RE/WE
Horizontal part of Read Enable/Write Enable signal
InvO/E
Invert Odd/Even
IRXR
Intelligent Residual Cross-Luminance Reduction
IrxrThr
IRXR Threshold (see Table 16)
IVericN
VERIC Identification (active LOW) (see Table 18)
LC_ACQ
Acquisition Line Counter
LC_DSP
Display Line Counter
MACP
Motion Adaptive Colour Plus
MacpOn
MACP on (see Table 11)
MacpYhThr
MACP Luminance Threshold (see Table 15)
MotVis
Motion Visibility (see Table 11)
Mpip
MultiPIP (see Table 12)
NmYl
Noise Dependent Luminance High-Pass Reduction (see Table 19)
PreEvFld
Preset Even Field (see Table 23)
Rha/Rhb
Helper Bandwidth and Amplitude Reduction (see Table 19)
SEL_SD_YL
Select Saturation Dependent Cross-Luminance Reduction (see Table 22)
VAA
Vertical Anti-Alias Filter (see Table 21)
VA_AI_DIFF
Positive Edge of VA_AI
VaDel
Delay of VA_FRONT
VA_FR_DEL
VA_FRONT Delayed
V_RE/WE
Vertical part of Read Enable/Write Enable signal
WeStrtH
Horizontal Start and Stop values for WE_MA (see Table 13 and Fig.31)
WeStpH
WeStrtV
Vertical Start and Stop values for WE_MA (see Table 13 and Fig.31)
WeStpV
XL
Cross-Luminance
Y_HP
Luminance High-Pass Component
Y_LP
Luminance Low-Pass Component
1996 Oct 28
53
SAA4996H
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
12 PACKAGE OUTLINE
QFP100: plastic quad flat package;
100 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT317-1
c
y
X
80
A
51
81
50
ZE
Q
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
31
100
detail X
30
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
3.3
0.36
0.10
2.87
2.57
0.25
0.40
0.25
0.25
0.13
20.1
19.9
14.1
13.9
0.65
24.2
23.6
18.2
17.6
1.95
1.0
0.6
1.43
1.23
0.2
0.15
0.1
Z D (1) Z E (1)
0.8
0.4
1.0
0.6
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT317-1
1996 Oct 28
EUROPEAN
PROJECTION
54
o
7
0o
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
If wave soldering cannot be avoided, the following
conditions must be observed:
13 SOLDERING
13.1
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
13.2
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9398 510 63011).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
13.4
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1996 Oct 28
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
13.3
SAA4996H
55
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
SAA4996H
14 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
15 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Oct 28
56
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
NOTES
1996 Oct 28
57
SAA4996H
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
NOTES
1996 Oct 28
58
SAA4996H
Philips Semiconductors
Preliminary specification
Motion Adaptive Colour Plus And Control
IC (MACPACIC) for PALplus
NOTES
1996 Oct 28
59
SAA4996H
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/01/pp60
Date of release: 1996 Oct 28
Document order number:
9397 750 01434