PHILIPS SAA7151

INTEGRATED CIRCUITS
DATA SHEET
SAA7151B
Digital multistandard colour
decoder with SCART interface
(DMSD2-SCART)
Product specification
File under Integrated Circuits, IC02
April 1993
Philips Semiconductors
Product specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA7151B
FEATURES
• 8-bit performance on chip for luminance and
chrominance signal processing for PAL, NTSC and
SECAM standards
• Separate 8-bit luminance and 8-bit chrominance input
signals from Y/C, CVBS, S-Video (S-VHS or Hi8)
sources
• The YUV bus supports a data rate of 13.5 MHz
(CCIR 601).
• SCART signal insertion by means of RGB/YUV
convertion; fast switch handling
– (864 × fH) for 50 Hz
• Horizontal and vertical sync detection for all standards
– (858 × fH) for 60 Hz
• Real time control output RTCO
• Compatible with memory-based features (line-locked
clock)
• Fast sync recovery of vertical blanking for VCR signals
(bottom flutter compensation)
• One 24.576 MHz crystal oscillator for all standards
• Controls via the I2C-bus
• User programmable aperture correction (horizontal
peaking)
GENERAL DESCRIPTION
• Cross-colour reduction by chrominance comb-filtering
(NTSC) or by special cross-colour cancellation
(SECAM)
The SAA7151B is a digital multistandard colour-decoder
having two 8-bit input channels, one for CVBS or Y, the
other for chrominance or time-multiplexed
colour-difference signals.
• 8-bit quantization of output signals in 4:1:1 or 4:2:2
formats
• 720 active samples per line
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
VDD
supply voltage (pins 5, 18, 28, 37 and 52)
4.5
5
IDD
total supply current (pins 5, 18, 28, 37 and 52)
−
100
VI
input levels
TTL-compatible
VO
output levels
TTL-compatible
Tamb
operating ambient temperature
0
−
UNIT
5.5
V
250
mA
70
°C
ORDERING INFORMATION
PACKAGE
EXTENDED TYPE
NUMBER
PINS
PIN POSITION
MATERIAL
CODE
SAA7151B
68
mini-pack PLCC
plastic
SOT188(1)
Note
1. SOT188-2; 1996 December 16.
April 1993
2
April 1993
3
41
SCL
IICSA
40
6 to 13
CUV0 to
CUV7
SDA
14 to 17
20 to 23
3
CVBS0 to
CVBS7
RESN
43
63
status
clock
44
65
32
HCL HSY
29
24
VS
30
HS
31
SYNCHRONIZATION
ODD
39
25
GPSW2
GPSW1
CHROMINANCE PROCESSOR
LUMINANCE
PROCESSOR
26
66
SYIS
MUXC
COMPONENT PROCESSING;
SCART INTERFACE CONTROL;
FAST SWITCH INSERTION
68
CPI
CREF
4
34
33
35
36
XTALI
XTAL
VSSA
LFCO
VDDA
FEIN
HREF
UV output
(UV7 to UV0)
Y output
(Y7 to Y0)
MEH292
37 +5 V
64
42
55 to 62
45 to 50,
53, 54
27
LL27
CLOCK
OUTPUT
INTERFACE
1, 2
test pins
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
Fig.1 Block diagram (application circuits see Figs 17, 18 and 19).
GPSW0
CONTROL
I2C-BUS
STATUS
REGISTER
INPUT
INTERFACE
SAA7151A
19, 38, 51, 67
POWER-ON
RESET
VSS1 to VSS4
5, 18, 28, 52
SCART
FSI FSO
ull pagewidth
VDD1 to VDD4
+5 V
Philips Semiconductors
Product specification
SAA7151B
BLOCK DIAGRAM
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
PINNING
SYMBOL
PIN
DESCRIPTION
SP
1
connected to ground (shift pin for testing)
AP
2
connected to ground (action pin for testing)
RESN
3
reset, active-LOW
CREF
4
clock reference, sync from external to ensure in-phase signals on the Y-, CUV- and YUV-bus
VDD1
5
+5 V supply input 1
CUV0
6
CUV1
7
CUV2
8
CUV3
9
CUV4
10
CUV5
11
CUV6
12
CUV7
13
CVBS0
14
CVBS1
15
CVBS2
16
chrominance input data bits CUV7 to CUV0 (digitized chrominance signals in two’s complement
format from a S-Video source (S-VHS, Hi8) or time-multiplexed colour-difference signals from a
YUV(RGB) source or both in combination)
CVBS lower input data bits CVBS3 to CVBS0
(CVBS with luminance, chrominance and all sync information in two’s complement format)
CVBS3
17
VDD2
18
+5 V supply input 2
VSS1
19
ground 1 (0 V)
CVBS4
20
CVBS5
21
CVBS6
22
CVBS7
23
GPSW1
24
status bit output FSST0 or port 1 output for general purpose (programmable by subaddress 0C)
GPSW2
25
status bit output FSST1 or port 2 output for general purpose (programmable by subaddress 0C)
HCL
26
black level clamp pulse output (begin and stop programmable), e.g. for TDA8708A (ADC)
LL27
27
line-locked system clock input signal (27 MHz)
VDD3
28
+5 V supply input 3
HSY
29
hor. sync pulse reference output (begin and stop programmable), e.g. for gain adj.TDA8708A
(ADC)
VS
30
vertical sync output signal (Fig.11)
HS
31
horizontal sync output signal (Fig.16; start point programmable)
RTCO
32
real time control output; serial increments of HPLL and FSCPLL and status PAL or SECAM
sequence (Fig.10)
XTAL
33
24.576 MHz clock output (open-circuit for use with external oscillator)
XTALI
34
24.576 MHz connection for crystal or external oscillator (TTL compatible squarewave)
VSSA
35
analog ground
LFCO
36
line frequency control output signal, multiple of horizontal frequency (nominal 6.75 MHz)
VDDA
37
+5 V supply input for analog part
VSS2
38
ground 2 (0 V)
April 1993
CVBS upper input data bits CVBS7 to CVBS4
(CVBS with luminance, chrominance and all sync information in two’s complement format)
4
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SYMBOL
PIN
DESCRIPTION
ODD
39
odd/even field identification output (odd = HIGH)
SDA
40
I2C-bus data line
SCL
41
I2C-bus clock line
HREF
42
horizontal reference for YUV data outputs (for active line 720Y samples long)
IICSA
43
set module address input of I2C-bus (LOW = 1000 101X; HIGH = 1000 111X)
CPI
44
clamping pulse input (digital clamping of external UV signals)
Y7
45
Y6
46
Y5
47
Y4
48
Y3
49
SAA7151B
Y signal output bits Y7 to Y2 (luminance), part of the digital YUV-bus
Y2
50
VSS3
51
ground 3 (0 V)
VDD4
52
+5 V supply input 4
Y1
53
Y0
54
UV7
55
UV6
56
UV5
57
UV4
58
UV3
59
UV2
60
UV1
61
UV0
62
Y signal output bits Y1 to Y0 (luminance), part of the digital YUV-bus
UV signal output bits UV7 to UV0, part of the digital YUV-bus
GPSW0
63
port output for general purpose (programmable by subaddress 0D)
FEIN
64
fast enable input (active-LOW to control fast switching due to YUV data; HIGH = YUV high-Z
MUXC
65
multiplexer control output; source select signal for external ADC (UV signal multiplexing)
FSO
66
fast switch and sync insertion output; gated FS signal from FSI or sync insertion pulse in full screen
RGB mode
VSS4
67
ground 4 (0 V)
FSI
68
fast switch input signal fed from SCART/peri-TV connector (indicates fast insertion of RGB signals)
April 1993
5
Philips Semiconductors
Product specification
SP
1
61 UV1
AP
2
62 UV0
RESN
3
63 GPSW0
CREF
4
64 FEIN
VDD1
5
65 MUXC
CUV0
6
66 FSO
CUV1
7
SAA7151B
67 VSS4
CUV2
8
68 FSI
CUV3
handbook, full pagewidth
9
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
CUV4 10
60 UV2
CUV5 11
59 UV3
CUV6 12
58 UV4
CUV7 13
57 UV5
CVBS0 14
56 UV6
CVBS1 15
55 UV7
CVBS2 16
54 Y0
CVBS3 17
53 Y1
SAA7151A
SAA7151B
VDD2 18
52 VDD4
VSS1 19
51 VSS3
CVBS4 20
50 Y2
CVBS5 21
49 Y3
CVBS6 22
48 Y4
CVBS7 23
47 Y5
GPSW1 24
46 Y6
GPSW2 25
45 Y7
IICSA 43
HREF 42
SCL 41
SDA 40
ODD 39
VSS2 38
VDDA 37
LFCO 36
VSSA 35
XTALI 34
XTAL 33
SYIS 32
HS 31
VS 30
HSY 29
VDD3 28
44 CPI
LL27 27
HCL 26
MEH293
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Chrominance processing
System configuration
The 8-bit chrominance input signal (signal “C” out of CVBS
or Y/C in Fig.4) is fed via the input interface to a bandpass
filter for eliminating the DC component, then to the
quadrature demodulator. Subcarrier signals from the local
oscillator (DTO1) with 90 degree phase shift are applied to
its multiplier inputs. The frequency depends on set TV
standard.
The SAA7151B system processes digital TV signals with
line-locked clock in PAL, SECAM and NTSC standards
(CVBS or S-Video) as well as RGB signals coming from a
SCART/peri-TV connector. The different source signals
are switched, if necessary matrixed and converted (Fig.3
and Table 1).
8-bit CVBS data (digitized composite video) and 8-bit UV
data (digitized chrominance and /or time-multiplexed
colour-difference signals) are fed to the SAA7151B. The
data rate is 27 MHz.
April 1993
6
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
AO
+
TDA8709A
ADI
8-bit ADC
and multiplexer
V2
(CHROMINANCE)
U/V
S0 S1
FE
CLS CLP
HCT4053
MULTIPLEXER
C
R
G
B
MUXC
LP
TDA8446
B
LP
U
VIDEO
SWITCH AND
MATRIX
sync
FS
V
CSO
SW1
FS*
CPI
SW2
CPI
clamping
CPO
GPSW1
I 2C-bus
(select)
CVBS/Y
from SCART interface SAA7151B
FSO
HCL
FSI
sync
CVBS
TDA8540
AO
LP
chroma
Y
C
CLK
VIDEO
SWITCH
to and from SAA7151B
R
G
sync
+5 V
C
TDA8708A
8-bit ADC
V0
CVBS/Y/sync
ADI
(LUMINANCE)
DO(7-0)
SCART
(PERI-TV)
BP
CUV(7-0)
DO(7-0)
handbook, full pagewidth
CVBS(7-0)
Y/C
Y
GA GB
CLK
GPSW2
* fast switching of Y signal for insertion
(UV are switched inside SAA7151B)
GPSW1
MEH305-3
Fig.3 System configuration, RGB fast switch interface included (SCART).
The multipliers operate as a quadrature demodulator for all
PAL and NTSC signals; it operates as a frequency
down-mixer for SECAM signals.
The two multiplier output signals are converted to a serial
UV data stream and applied to two low-pass filter stages,
then to a gain controlled amplifier. A final multiplexed
low-pass filter achieves, together with the preceding
stages, the required bandwidth performance. The from
PAL and NTSC originated signals are applied to a
comb-filter. The signals, originated from SECAM, are fed
through a cloche filter (0 Hz centre frequency), a phase
demodulator and a differentiator to obtain
frequency-demodulated colour-difference signals.
the fast switch to the output formatter stages and to the
output interface.
Chrominance signals are output in parallel (4:2:2) on the
YUV-bus. The data rate of Y signal (pixel rate) is
13.5 MHz. UV signals have a data rate of 13.5 MHz/2 for
the 4:2.2 format (Table 2) respectively 13.5 MHz/4 for the
4:1.1 format (Table 3).
Component processing and SCART interface control
The 8-bit multiplexed colour-difference input signal (signal
CUV, Fig.1, out of matrixed RGB in Fig.3) is fed via the
input interface to a chrominance stop filter (UV signal only
can pass through; Figures 22 to 24). Here it is clamped
and fed to the offset compensation which can be enabled
or disabled via the I2C-bus.
The SECAM signals are fed after de-emphasis to a
cross-over switch, to provide the both serial-transmitted
colour-difference signals. These signals are finally fed via
April 1993
7
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
For matrixed RGB signals - the full screen SCART mode
and the fast insertion mode (blanking/switching) are
selectable. The chrominance stop filter is automatically
bypassed in full screen SCART mode.
errors. An internal timing correction compensates for slight
differences in timing during sampling. The U and V signals
are delay-compensated and fed to the output formatter.
The format 4:2:2 or 4:1:1 is generated by a switchable
filter.
The control signals for the front end (Figures 3 and 20)
MUXC, status bits FSST1, FSST0 (outputs GPSW2,
GPSW1) and FSO are generated by the SAA7151B.
Full screen RGB mode (SCART):
The CUV digital input signal (7-0) consists of
time-multiplexed samples for U and V. An offset correction
for both signals is applied to correct external clamping
Table 1
MODE
SAA7151B
SCART interface control (Fig.3)
CONNECTION
chroma
TDA8709A
output of
selected CUV
FSO GPSW 2 GPSW 1 MUXC TDA8446
input
(7-0)
to TDA8709A
luminance
fast switch
TDA8446
input
selector (via
I2C-bus)
TDA8540
RGB
only
0
0
0
0
0
0
0
1
high-Z
VIN2
U/V
sync (RGB)
sync (RGB)
Y/C or
CVBS
only
0
0
0
0
1
1
0
1
C
VIN1
C
Y (Y/C) or CVBS
Y (Y/C) or
CVBS
Fast
switch
0
0
1
1
0
0
0
1
C
VIN2
0.5(C+U)/
Y (Y/C) or
Y (Y/C) or CVBS
0.5(C+V)
CVBS
0
0
1
1
1
1
0
1
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
RGB
only
Fast
switch
not used
high-Z
VIN2
Y (RGB)
sync (RGB)
not used
C
VIN2
0.5(C+U)/
Y (RGB)
0.5(C+V)
Y (Y/C) or
CVBS
not used
Fast insertion mode:
inserted UV data (Figures 6 and 7)
The control signals for the front end (Table 1) MUXC, FSO,
status bits FSST1 and FSST0 (outputs GPSW2 and
GPSW1) are generated by the SAA7151B.
Fast insertion is applied by FSI pulse to ensure correct
timing. The RGB source signal is matrixed into UV and
inserted into the CVBS or Y/C source signal after two field
periods if FSI pulses are received. The output FSO is set
to HIGH during a determined insertion window (screen
plain minus 6 % of horizontal and vertical deflection).
Switch over depends on the phase of FSI in relation to the
valid pixel sequence depending on the phase-different
weighting factors. They are applied to the original and the
April 1993
U/V
The amplitude of chrominance and colour-difference
signals are scaled down by factor 2 to avoid overloading of
the chrominance analog-to-digital converter. The
amplitudes are reduced in the TDA8446 by signals on lines
GPSW2 and GPSW1.
8
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
delays of some internal stages to achieve a changed
timing due to the timing groups b and c.
The HREF signal only controls the data multiplexer phase
and the data output signals.
All timings of the following diagrams are measured with
nominal input signals, for example coming from a pattern
generator. Processing delay times are taken between
input and data output, respectively between internal sync
reference (main counter = 0) and the rising edge of HREF.
Luminance processing
The luminance input signal, a digital CVBS format or an
8-bit luminance format (S-Video), is fed through a sample
rate converter to reduce the data rate to 13.5 MHz (Fig.5).
Sample rate is converted by means of a switchable
pre-filter. High frequency components are emphasized to
compensate for loss in the following chrominance trap
filter. This chrominance trap filter (fo = 4.43 MHz or
fo = 3.58 MHz centre frequency selectable) eliminates the
most of the colour carrier signal, therefore, it must be
bypassed for S-Video signals.
Line locked clock frequency
LFCO is required in an external PLL (SAA7157) to
generate the line-locked clock frequency LL27 and CREF.
The high frequency components of the luminance signal
can be “peaked” in two bandpass filters with selectable
transfer characteristic. A coring circuit (±1 LSB) can
improve the signal, this signal is then added to the original
signal. A switchable amplifier achieves a common DC
amplification, because the DC gains are different in both
chrominance trap modes. Additionally, a cut-off sync pulse
is generated for the original signal in both modes.
YUV-bus, digital outputs
The 16-bit YUV-bus transfers digital data from the output
interfaces to a feature box, or to the digital-to-analog
converter (DAC). Outputs are controlled via the I2C-bus in
normal selections, or they are controlled by output enable
chain (FEIN, pin 64). The YUV-bus data rate 13.5 MHz.
Timing is achieved by marking each second positive rising
edge of the clock LL27 synchronized by CREF.
Synchronization
The luminance output signal is fed to the synchronization
stage. Its bandwidth is reduced to 1 MHz in a low-pass
filter (sync pre-filter). The sync pulses are sliced and fed to
the phase detectors to be compared with the sub-divided
clock frequency. The resulting output signal is applied to
the loop filter to accumulate all phase deviations. There
are three groups of output timing signals:
YUV-bus formats
4 : 2 : 2 and 4 : 1 : 1
The output signals Y7 to Y0 are the bits of the digital
luminance signal. The output signals UV7 to UV0 are the
bits of the digital colour-difference signal. The frames in
the Tables 2 and 3 are the time to transfer a full set of
samples. In case of 4 : 2 : 2 format two luminance samples
are transmitted in comparison to one U and one V sample
within one frame. The time frames are controlled by the
HREF signal, which determines the correct UV data
phase. The YUV data outputs can be enabled or set to
3-state position by means of the FEIN signal. FEIN = LOW
enables the output; HIGH on this pin forces the Y and U/V
outputs to a high-impedance state (Fig.6).
a. signals related to data output signals (HREF)
b. signals related to the input signals (HSY, and HCL)
c. signals related to the internal sync phase
All horizontal timings are derived from the main counter,
which represents the internal sync phase. The HREF
signal only with its critical timing is phase-compensated in
relationship to the data output signal. Future circuit
improvements could slightly influence the processing
April 1993
SAA7151B
9
April 1993
RTCO 32
10
SAA7151B
HUEC(7-0)
CHROMINANCE
BANDPASS
CHROMINANCE
CHRS
UVSS
CDPO
to luminance
BYPS
YDEL0
CDMO
INPUT
INTERFACE
CHROMINANCE
STOP FILTER,
OFFSET
COMPENSATION
C
UV
CDET
CSTD(2-0)
ASTD
LOOP
FILTER
PI2
GAIN
CONTROLLED
AMPLIFIER
STANDARD
DETECTION
UV
UV
FAST SWITCH
AND
WEIGHTING
CCIR
SUVI
DE-EMPHASIS
SXCR
DIFFERENTIATOR
UV
FSST
UV
(7-0)
OFTS
COLO
OEDY
OEDC
OEHS
CHSB
MEH294
from luminance
FSAU
FSDL(2-0)
GPSI(2-1)
OFTS
FSIV
68 FSI
66 FSO
65 MUXC
25 GPSW1
24 GPSW2
42 HREF
OUTPUT
FORMATTER
AND OUTPUT 64 FEIN
INTERFACE
Y
(7-0)
SCART
INTERFACE
CONTROL
COMB FILTER
AND
SECAM
RECOMBINATION
PHASE
DEMODULATOR
AND
AMPLITUDE
DETECTOR
CLOCHE
FILTER
(SECAM)
COFF
LOWPASS
FILTER
CGFX, AMPF(3-0)
BURST GATE
ACCUMULATOR
CKTS (4-0)
CHCV (7-0)
CKTO (4-0)
LFIS (2-1)
FISE
LOWPASS
FILTER
TIME
INTERPOLATION
OFTS, IPBP
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
Fig.4 Detailed block diagram; continued in Fig.5.
PLSE(7-0) SEQA
SESE(7-0)
CDVI
SEQUENCE
PROCESSOR
LOOP
FILTER
PI1
DISCRETE TIME
OSCILLATOR (DTO1)
AND DIVIDER
QUADRATURE
DEMODULATOR
DELAY
COMPENSATION
handbook, full pagewidth
CUV
(7-0)
CVBS
(7-0)
OSCE
44
CPI
clamping
Philips Semiconductors
Product specification
SAA7151B
April 1993
11
41
40
43
SCL
SDA
IICSA
SYNC SLICER
SAA7151B
BYPS
29
PREF
BYPS
HS
31
HLCK
SYNC
LFCO
ODD
DAC
DISCRETE TIME
OSCILLATOR
(DTO2)
PROGRAMMABLE
DELAY
APER
(1-0)
WEIGHTING
AND
ADDING STAGE
36
FIDT
VNOI (1-0)
WIND
BOFL
BFON
FSEL
AUFD
HLCK
HPLL
LOOP
FILTER
MATCHING
AMPLIFIER
CORI
CORING
39
VERTICAL
PROCESSOR
VTRC
HLCK
PHASE DETECTOR
COARSE
BPSS
(1-0)
VARIABLE
BANDPASS
FILTER
Fig.5 Detailed block diagram; continued from Fig.4.
VS
30
COUNTER
HCL HSY
26
SCEN
OEVS
OEHS
HCLB (7-0)
HCLS (7-0)
HSYB (7-0)
HSYS (7-0)
HPHI (7-0)
IDEL (7-0)
PHASE DETECTOR
FINE
LUMINANCE
PREF
CHROMINANCE
TRAP
CRYSTAL
CLOCK
GENERATOR
LINE-LOCKED
CLOCK
GENERATOR
YDEL
(3-1)
VARIABLE DELAY
COMPENSATION
to output interface
MEH295
34 XTALI
33 XTAL
27 LL27
4 CREF
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
GPSW0
63
I2C-BUS
CONTROL
PRE-FILTER
SYNC
OFFSET
COMPENSATION
PRE-FILTER
handbook, full pagewidth
SAMPLE RATE
CONVERTER
from input interface
Philips Semiconductors
Product specification
SAA7151B
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
Table 2
SAA7151B
for the 4 : 2 : 2 format (720 pixels per line). The quoted frequencies are valid on the YUV-bus. The time
frames are controlled by the HREF signal.
OUTPUT
PIXEL BYTE SEQUENCE
Y0 (LSB)
Y0
Y0
Y0
Y0
Y0
Y0
Y1
Y1
Y1
Y1
Y1
Y1
Y1
Y2
Y2
Y2
Y2
Y2
Y2
Y2
Y3
Y3
Y3
Y3
Y3
Y3
Y3
Y4
Y4
Y4
Y4
Y4
Y4
Y4
Y5
Y5
Y5
Y5
Y5
Y5
Y5
Y6
Y6
Y6
Y6
Y6
Y6
Y6
Y7 (MSB)
Y7
Y7
Y7
Y7
Y7
Y7
UV0 (LSB)
U0
V0
U0
V0
U0
V0
UV1
U1
V1
U1
V1
U1
V1
UV2
U2
V2
U2
V2
U2
V2
UV3
U3
V3
U3
V3
U3
V3
UV4
U4
V4
U4
V4
U4
V4
UV5
U5
V5
U5
V5
U5
V5
UV6
U6
V6
U6
V6
U6
V6
UV7 (MSB)
U7
V7
U7
V7
U7
V7
Y frame
0
1
2
3
4
5
UV frame
0
Table 3
2
4
for the 4 : 1 : 1 format (720 pixels per line). The quoted frequencies are valid on the YUV-bus. The time
frames are controlled by the HREF signal.
OUTPUT
PIXEL BYTE SEQUENCE
Y0 (LSB)
Y0
Y0
Y0
Y0
Y0
Y0
Y0
Y0
Y1
Y1
Y1
Y1
Y1
Y1
Y1
Y1
Y1
Y2
Y2
Y2
Y2
Y2
Y2
Y2
Y2
Y2
Y3
Y3
Y3
Y3
Y3
Y3
Y3
Y3
Y3
Y4
Y4
Y4
Y4
Y4
Y4
Y4
Y4
Y4
Y5
Y5
Y5
Y5
Y5
Y5
Y5
Y5
Y5
Y6
Y6
Y6
Y6
Y6
Y6
Y6
Y6
Y6
Y7 (MSB)
Y7
Y7
Y7
Y7
Y7
Y7
Y7
Y7
UV0 (LSB)
0
0
0
0
0
0
0
0
UV1
0
0
0
0
0
0
0
0
UV2
0
0
0
0
0
0
0
0
UV3
0
0
0
0
0
0
0
0
UV4
V6
V4
V2
V0
V6
V4
V2
V0
UV5
V7
V5
V3
V1
V7
V5
V3
V1
UV6
U6
U4
U2
U0
U6
U4
U2
U0
UV7 (MSB)
U7
U5
U3
U1
U7
U5
U3
U1
Y frame
0
1
2
3
4
5
6
7
UV frame
0
April 1993
12
4
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
Signal levels (Figures 12, 13 and 14)
The nominal input and output signal levels are defined by a colour bar signal with 75 % colour, 100 % saturation and
100 % luminance amplitude (EBU colour bar).
CUV-bus input format
The CUV-bus transfers the digital chrominance/colour-difference signals from the ADC to the SAA7151B (Fig.6; Table 1):
• normal mode for digital chrominance transmission.
• UV colour-difference mode for colour-difference signals UV (out of matrixed RGB signals)
• FS mode (fast switch mode; UV inserted into chrominance signal C with addition of the two signal spectra).
RTCO output
The RTCO output signal (Fig.10) contains serialized information about actual clock frequency, subcarrier frequency and
PAL/SECAM sequence. This signal may preferably be used with the frequency-locked digital video encoder SAA7199B.
handbook,LL27
full pagewidth
from 3-state
to 3-state
CREF
HREF
tHD
tSU
FEIN
tOS
tOH
YUV
MEH548
Fig.6 Timing example of fast enable input (FEIN).
April 1993
13
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
handbook, full
pagewidth
LL27
clock
0
LL13.5 clock
1
2
0
SAA7151B
3
4
1
5
2
MUXC
Normal mode (chrominance pixel byte sequence)
chrominance
C0
C1
C2
C3
C4
C5
U2
U3
V4
V5
UV colour-difference mode (UV pixel byte sequence)
colourdifference
V0
V1
(1)
valid colourdifference
U0
(1)
(1)
V1
V5
U3
Fast switch mode (data insertion)
CUV
(V0 + C0)/2
(V1 + C1)/2
(U2 + C2)/2
(1)
valid CUV
(U3 + C3)/2
(V4 + C0)/2
(1)
(V1 + C1)/2
(V5 + C5)/2
(1)
(U3 + C3)/2
(V5 + C5)/2
MEH332
Fig.7
April 1993
CUV input formats.
(1) each second sample only after a MUXC change is taken for down-sampling to 13.5 MHz to reduce
cross-talk components between U and V signals.
14
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
handbook, full pagewidth
0 old + 1 new
new
1/8 old + 7/8 new
1/4 old + 3/4 new
3/8 old + 5/8 new
1/2 old + 1/2 new
5/8 old + 3/8 new
3/4 old + 1/4 new
7/8 old + 1/8 new
Note: in 4:2:2 format weighting
in 1/4 steps only.
old
T(n−2)
T(n−1)
T(n)
T(n+1)
T(n+2)
MEH307
Fig.8 Addition of weighted components.
handbook, full pagewidth
1 3/4 1/2 1/4
FS
U0, V0
UV
LL6.75
0
LL27
0
FS
fast switch weighting for 4:2:2 format
U1, V1
U2, V2
1
1
1
2
3
4
2
5
6
7
8
7/8 3/4 5/8 1/2 3/8 1/4 1/8
3
9
LL3.375
0
LL27
0
2
3
4
10 11 12 13 14 15 16
U1, V1
1
1
4
fast switch weighting for 4:1:1 format
U0, V0
UV
U3, V3
5
6
7
8
3
9
10 11 12 13 14 15 16
MEH308
Fig.9 Weighting factors of fast switching for 4:2:2 and 4:1:1 formats.
April 1993
15
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
handbook, full pagewidth
LL27
CREF
HREF
start of
active line
Byte number for pixels:
Y signal
0
1
2
3
4
5
6
7
U0
V0
U2
V2
U4
V4
U6
V6
50/60 Hz
U and V signal
MEH297
handbook, full pagewidth
LL27
CREF
HREF
end of
active line
Byte number for pixels:
714
715
716
717
718
719
U714
V714
U716
V716
U718
V718
Y signal
50/60 Hz
U and V signal
MEH298
Fig.10 Line control by HREF in 4:2:2 format for 50 Hz and 60 Hz systems.
handbook, full pagewidth
H/L transition
(counter start)
4 bits
reserve
HPLL
increment
bits 13 to 0
128 clocks
13
0
bit
21 20
14
19
5 bits
reserve sequence bit(1)
FSCPLL
increment
bits 21 to 0
15
10
reserved(2)
5
1 0
RTCO
0
4
8
61
time slot
(LL27/4)
(1) Sequence bit:
SECAM: 0 equals DB-line
1 equals DR-line
PAL:
0 equals (R-Y) line normal
1 equals (R-Y) line inverted
NTSC:
0 (no change)
(2) Reserve bits: 236 for 50 Hz systems; 233 for 60 Hz systems
Fig.11 RTCO timing.
April 1993
16
valid
not valid
67
MEH341
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
Condition: Nominal input signal, 50 Hz
handbook, full pagewidth
(a) 1st field
625
1
2
3
4
5
7
6
8
9
input CVBS
HREF
503 × 2/LL27
VS
2 × 2/LL27
ODD
(b) 2nd field
313
314
315
316
317
318
319
320
321
input CVBS
HREF
71 × 2/LL27
VS
2 × 2/LL27
ODD
MEH335
Fig.12 Vertical timing diagram at 50 Hz.
April 1993
17
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
Condition: Nominal input signal, 60 Hz
handbook, full pagewidth
(a) 1st field
525
1
2
3
4
5
7
6
8
9
input CVBS
HREF
491 × 2/LL27
VS
2 × 2/LL27
ODD
(b) 2nd field
263
264
265
266
267
268
269
270
271
input CVBS
HREF
59 × 2/LL27
VS
2 × 2/LL27
ODD
MEH336
Fig.13 Vertical timing diagram at 60 Hz.
April 1993
18
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
handbook, +127
full pagewidth
+106
+95
+127
reserved
+105
+100
+76
luminance
60 Hz mode
luminance
50 Hz mode
chrominance
60 Hz mode
C
chrominance
chrominance
50 Hz mode
0
0
V
U
component of
colour-difference
signal
−52
−64
blanking level
−76
−91
−103
−91
−103
sync
−128
−132
−128
clipped
(b) CUV input signal range
(U and V out of RGB;
in FS mode ranges × 0.5).
(a) CVBS input signal range.
+255
+127
+127
+235
white 100%
+100
blue 75%
+105
red 75%
luminance signal
output range
+128
0
0
U-component
output signal range
−101
+16
V-component
output signal range
yellow 75%
−106
cyan 75%
black
−128
−128
0
(c) Y output signal range.
(d) U output signal range (B-Y).
(e) V output signal range (R-Y).
Notes: 1. All levels related to EBU colour bar.
2. Values in decimal at 100% luminance and 75% chrominance amplitude
Fig.14 Input and output signal ranges in DTV mode (digital TV).
April 1993
19
MEH299
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
handbook, +127
full pagewidth
+106
+95
+127
reserved
100% white
+84
+76
luminance
60 Hz mode
luminance
50 Hz mode
chrominance
60 Hz mode
chrominance
50 Hz mode
0
−52
−64
−91
−103
C
chrominance
0
V
U
component of
colour-difference
signal
blanking level
−76
−84
sync
−128
−132
−128
clipped
(b) CUV input signal range
(U and V out of RGB;
in FS mode ranges × 0.5).
(a) CVBS input signal range.
+255
+255
+235
+255
white 100%
+212
blue 75%
+212
red 75%
luminance signal
output range
+128
+128
+128
U-component
output signal range
+44
+16
V-component
output signal range
yellow 75%
+44
cyan 75%
black
0
0
(c) Y output signal range.
0
(d) U output signal range (B-Y).
(e) V output signal range (R-Y).
MEH300
Notes: 1. All levels are related to EBU colour bar.
2. Values in decimal at 100 % luminance and 75 % chrominance amplitude.
3. For SECAM input signals the CCIR levels will be exceeded.
Fig.15 Input and output signal ranges in CCIR mode.
April 1993
20
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
63 × 2/LL27
handbook, full pagewidth
burst
CVBS
HSY
step size 2/LL27
HSY
+191
programming
range
(step size: 2/LLC)
−64
0
HCL
HCL
+127
programming
range
(step size: 2/LL27)
−128
0
83.5 × 2/LL27(1)
4 × 2/LL27 (50 HZ)
10 × 2/LL27 (60 HZ) HREF position
+235
Y-output
+16
Yout
0
HREF
...719
0...
144 × 2/LL27 (50 HZ)
138 × 2/LL27 (60 HZ)
HREF length fix
16 × 2/LL27 (50 HZ)
12 × 2/LL27 (60 HZ)
720 × 2/LL27
HS
HS
programming range
(step size: 8/LL27)
64 × 2/LL27
+431
−432
0
MEH549
(1) the processing delay will be influenced in future enhancements.
(1) the processing delay will be ifluenced in future enhancements
Fig.16 Horizontal sync and clamping timing for 50/60 Hz (signals HSY, HCL, HREF and HS).
April 1993
21
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); ground pins 19, 35, 38, 51 and 67 as well as
supply pins 5, 18, 28, 37 and 52 connected together.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage (pins 5, 18, 28, 37, 52)
−0.5
7.0
V
Vdiff GND
difference voltage VSS A − VSS(1 to 4)
−
±100
mV
VI
voltage on all inputs
−0.5
VDD+0.5
V
VO
voltage on all outputs (IO max = 20 mA)
−0.5
VDD+0.5
V
Ptot
total power dissipation
−
2.5
W
Tstg
storage temperature range
−65
150
°C
Tamb
operating ambient temperature range
0
70
°C
VESD
handling(1)
−
±2000
V
electrostatic
for all pins
Note
1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor; inputs and outputs are protected
against electrostatic discharge in normal handling. Normal precautions appropriate to handle MOS devices is
recommended (“Handling MOS Devices”).
April 1993
22
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
CHARACTERISTICS
VDD = 4.5 to 5.5 V; Tamb = 0 to 70 °C unless otherwise specified.
SYMBOL
PARAMETER
VDD
supply voltage range (pins 5, 18, 28, 37, 52)
IDD
total supply current (pins 5, 18, 28, 37, 52)
I2C-bus,
CONDITIONS
MIN.
4.5
VDD = 5 V; inputs LOW;
outputs not connected −
TYP.
MAX.
UNIT
5
5.5
V
100
250
mA
SDA and SCL (pins 40 and 41)
VI L
input voltage LOW
−0.5
−
1.5
V
VI H
input voltage HIGH
3
−
VDD+0.5
V
I40, 41
input current
−
−
±10
µA
IACK
output current on pin 40
acknowledge
3
−
−
mA
VO L
output voltage at acknowledge
I40 = 3 mA
−
−
0.4
V
Data, clock and control inputs (pins 3, 4, 6 to 17, 20 to 23, 27, 34, 64 and 68); Figures 14 and 15
VI L
LL27 input voltage (pin 27)
VI H
VI L
other input voltages
VI H
Ileak
input leakage current
CI
input capacitance
tSU.DAT
input data set-up time
tHD.DAT
input data hold time
LOW
−0.5
−
0.6
V
HIGH
2.4
−
VDD+0.5
V
LOW
−0.5
−
0.8
V
HIGH
2.0
−
VDD+0.5
V
−
−
10
µA
data inputs; note 1
−
−
8
pF
I/O high-impedance
−
−
8
pF
clock inputs
−
−
10
pF
11
−
−
ns
3
−
−
ns
Fig.17
YUV-bus, HREF and VS outputs (pins 30, 42, 45 to 50 and pins 53 to 62), Figures 10, 14 and 15
VO L
output voltage LOW
0
−
0.6
V
VO H
output voltage HIGH
2.4
−
VDD
V
CL
load capacitor
15
−
50
pF
1.4
−
2.6
V
1
−
VDD
V
0
−
0.6
V
notes 1 and 2
LFCO output (pin 36)
Vo
output signal (peak-to-peak value)
V36
output voltage range
note 2
Control outputs (pins 24 to 26, 29, 31, 32, 33, 39, 63, 65 and 66); Figures 12, 16 and 17
VO L
output voltage LOW
VO H
output voltage HIGH
2.4
−
VDD
V
CL
load capacitor
7.5
−
25
pF
April 1993
notes 1 and 2
23
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SYMBOL
PARAMETER
CONDITIONS
SAA7151B
MIN.
TYP.
MAX.
UNIT
Timing of YUV-bus and control outputs
Figures 10, 12 and 13
tOH
YUV, HREF, VS
at CL = 15 pF;
13
−
−
ns
controls at CL = 7.5 pF
13
−
−
ns
YUV, HREF, VS
at CL = 50 pF;
20
−
−
ns
tOS
output signal hold time
output set-up time
controls at CL = 25 pF
20
−
−
ns
tSZ
data output disable transition time
to 3-state condition
22
−
−
ns
tZS
data output enable transition time
from 3-state condition
20
−
−
ns
±400
−
−
Hz
Chrominance PLL
fC
catching range
Crystal oscillator
Figures 19 and 20; note 3
fn
nominal frequency
3rd harmonic
−
24.576
−
MHz
∆f / fn
permissible deviation fn
−
−
±50
10−6
temperature deviation from fn
−
−
±20
10−6
temperature range Tamb
0
−
70
°C
load capacitance CL
8
−
−
pF
series resonance resistance RS
−
40
80
Ω
motional capacitance C1
−
1.5±20%
−
fF
parallel capacitance C0
−
3.5±20%
−
pF
X1
crystal specification:
Line locked clock input LL27 (pin 27)
Fig.9 and 17
tLL27
cycle time
note 4
35
−
39
ns
tp
duty factor
tLL27H /t LL27
40
50
60
%
tr
rise time
−
−
5
ns
tf
fall time
−
−
6
ns
Notes
1. Data output signals are Y7 to Y0 and UV7 to UV0. All other are control signals.
2. Levels are measured with load circuit. YUV-bus, HREF and VS outputs with 1.2 kΩ in parallel to 50 pF at 3 V
(TTL load);
LFCO output with 10 kΩ in parallel to 15 pF and other outputs with 1.2 kΩ in parallel to 25 pF at 3 V (TTL load).
3. Recommended crystal: Philips 4322 143 05291.
4. tSU, tHD, tOH and tOD include tr and tf.
April 1993
24
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
Table 4
SAA7151B
High-impedance control for YUV-bus (Fig.17)
OEDY
OEDC
FEIN
Y(7:0)
UV(7:0)
0
0
0
Z
Z
0
1
0
Z
active
1
0
0
active
Z
1
1
0
Z
Z
X
X
1
Z
Z
tLL27
handbook, full pagewidth
tLL27H
2.4 V
clock input LL27
1.5 V
0.6 V
tr
tf
tSU
tHD
not valid
2.0 V
input data
0.8 V
2.0 V
input CREF
0.8 V
tZS
tSU
tOH
tOS
tHD
not valid
2.4 V
output data
0.6 V
tSZ
tSU
tHD
2.4 V
input FEIN
0.6 V
MEH550
Fig.17 Data input and output timing diagram.
April 1993
25
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
handbook, full pagewidth
24.576 MHz
(3rd harmonic)
XTAL
SAA7151B
XTAL
33
33
10 pF
X1
SAA7151B
XTALI
1 nF
10 µH
(±20%)
SAA7151B
XTALI
34
34
10 pF
MEH302
(a)
(b)
Fig.18 Oscillator application (a) and optional clock from external (b).
April 1993
26
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
CPI
handbook, full pagewidth
VSS
5
0.1 µF
UV2
UV3
59
UV4
58
52
UV6
56
UV7
55
chrominance
CUV7 to CUV0
CUV0
CUV1
CUV2
CUV3
CUV4
CUV5
CUV6
CUV7
luminance
CVBS7 to CVBS0
L0
L1
L2
L3
L4
L5
L6
X1 :
Philips 4322 143 05291
L7
YUV-bus
UV5
57
VDD
UV7 to UV0
UV1
61
60
0.1 µF
6
Y0
54
7
8
53
9
50
10
49
11
48
12
47
13
46
SAA7151B
15
Y2
Y3
Y4
Y5
Y6
Y7
RTCO
32
16
31
17
30
20
29
21
26
Y7 to Y0
Y1
45
14
HS
VS
HSY
HCL
22
23
HREF
42
SCL
41
33
X1
UV0
62
28
0.1 µF
+5 V
44
18
0.1 µF
digital
67 51 38 19
SDA
40
24.576 MHz
39
34
GPSW0
63
FEIN
64
12
pF
10
µH
12
pF
I2C-bus
ODD
IICSA
43
2
1 nF
RESN
27
24 25
MUXC
36
65
66
37
68
2.2 µH
CREF
LL27B
LL13A
LL13B
analog
8
12
7
SAA7157
VDD digital
17
1
15
6
10
9
14
13
20
18
0.1
µF
0.1
µF
MEH328
digital
Fig.19 Application of SAA7151B.
April 1993
+5 V
0.1 µF
4
GPSW2
VDD analog
10 µF
3
16
f > 13 MHz
0.1 µF
5
19
75
Ω
0.1 µF
2
LL27A
150
BAT45 pF
680
Ω
+5 V
11
RESN
680 Ω
FSI
LFCO
FSO
GPSW1
digital
VSSA
VDDA
35
4
digital
(from SCART)
FS
1
3
27
+5 V
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
2.2 µH
+12 V
sync
22
µF
4.7 kΩ
1
20
2
19
3
18
4
17
0.15 µF
sync
from SCART connector
75
Ω
75 Ω
B
VP
U signal
16
Y signal
6
15
V signal
7
14
GPSW2
8
13
5
TDA8446
0.1 µF
75 Ω
0.1 µF
R
FS
+12 V
0.1 µF
75 Ω
G
0.1 µF
4.7 µF
1 nF
to SAA7151B
0.1 µF
from / to TDA8708/09
handbook, full pagewidth
SAA7151B
FSO
CVBS/Y 0.1 µF
C
9
12
10
11
C signal
chrominance
bandpass filter
HCL
GPSW1
CLO
47
kΩ
SCL
1 kΩ
SCL
I2C-bus
SDA
SDA
(to SAA7151B)
75 Ω
10 kΩ
1
20
2
19
3
18
4
17
+5 V
10 kΩ
unused signal
outputs
22 µF
75 Ω
C
(chrominance)
75 Ω
CVBS
75 Ω
Y
16
5
0.1 µF
audio
source
control
150 Ω
22 µF
TDA8540
6
15
7
14
8
13
9
12
10
11
0.1 µF
0.1 µF
150
Ω
7808
stabilizer
C
22 Ω
VP
0.1
µF
+8 V
10 µF
1.6 kΩ
22 Ω
220 pF
0.1 µF
330 Ω
MEH330
Fig.20 Application of input signal selecting (SCART interface).
April 1993
28
to pin 8
29
(+5 V)
1 kΩ
5.6 Ω
UV gain level for CCIR
1 µF
VDDA
VIN2
VIN1
analog
10 Ω
10 µF
3
2
26
27
CVBS7
CVBS2
CVBS3
CVBS4
CLK
VDDD
VDDO
CVBS3
CVBS2
CVBS1
CVBS0
0.1
µF
0.1
µF
68 pF
120
Ω
5
22
Ω
5.6 Ω
0.1
µF
100
kΩ
4
14
11
6, 8,
10 7
HCT4053
digital
1.5 kΩ
1 nF
3
12
13
9
handbook, full pagewidth
5.6 Ω
3.3 kΩ
3 kΩ
analog
6.2 kΩ
0.1 µF
VIN2
VIN1
VIN0
28
27
26
25
24
23
22
21
20
19
18
17
16
15
5.6 Ω
1 kΩ
VDDA
1 µF
1.2 kΩ
1 µF
1 µF
0.22 µF
0.1 µF
1 mH
1.5 kΩ
10 µF
4.7 µF
33 pF
NOR
Fig.21 Application circuit analog-to-digital conversions.
1
4
25
28
5
24
7
8
9
10
11
12
13
14
6
TDA8708A
1
nF
220 Ω
BC547
10 µF
220
Ω
BC547
23
22
21
20
19
18
17
16
15
2 4.7
kΩ µF
6.8 kΩ
VIN0
0.22 µF
0.1 µF
2.2 kΩ
1 µF
1 µF
4.7 µF
2
kΩ
2
kΩ
16
TDA8709A
1 kΩ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CUV7
CUV6
CUV5
CUV4
CLK
VDDD
VDDO
CUV3
CUV2
CUV1
CUV0
68
pF
MEH329
22
Ω
CPI
HSY
HCL
CVBS(7-0)
120
Ω
0.1 µF
0.1 µF
digital
CUV(7-0)
MUXC
GPSW2
GPSW1
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
+5 V (digital supply)
+5 V (analog supply)
LL27A
CLO from pin 4
of TDA8446
HCL to pin 9
of TDA8446
5 MHz low-pass
filter
680 Ω
Y or CVBS
from pin 16
C signal
from pin 11
U signal
from pin 17
2 MHz
low-pass
filters
1 kΩ
VDDA
from/to SAA7151B
April 1993
V signal
from pin 15
Philips Semiconductors
Product specification
SAA7151B
from/to TDA8446
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
I2C-BUS FORMAT
S
SLAVE ADDRESS
A
SUBADDRESS
A
DATA0
A
S
=
start condition
SLAVE
ADDRESS
=
1000 101X (IICSA = LOW) or 1000 111X (IICSA = HIGH)
A
=
acknowledge, generated by the slave
SUBADDRESS(1)
=
subaddress byte (Table 5)
DATA
=
data byte (Table 5)
P
=
stop condition
X
=
read/write control bit
X = 0, order to write (the circuit is slave receiver)
X = 1, order to read (the circuit is slave transmitter)
DATAn
Note
1. If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed.
Remarks: - Prior to reset of the IC all outputs are undefined.
- After power-on reset, the control register 12 (hex) is set to 00 (hex).
April 1993
30
A
P
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
Table 5
SAA7151B
I2C-bus; DATA for status byte (X in address byte = 1; slave address 8B (hex) at IICSA = LOW or 8F (hex) at
IICSA = HIGH)
FUNCTION
DATA
D7
status byte
D6
D5
STTC HLCK FIDT
D4
D3
D2
FSST1
FSST0 CDET2
D1
D0
CDET1
CDET0
Function of the bits:
STTC
Status time constant (to be used for gogical combfilter SAA7152)
0 = TV mode; 1 = VCR mode
HLCK
Horizontal PLL information:
0 = HPLL locked; 1 = HPLL unlocked
FIDT
Field information
0 = 50 Hz system detected; 1 = 60 Hz system detected
−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
FSST1 to FSST0
Fast switching output mode:
FSST1
FSST0
mode
0
0
1
1
0
1
0
1
RGB; FSI = HIGH (pin 68)
Y/C; FSI = LOW (pin 68)
fast switching (toggle)
not used
−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
CDET2 to CDET0
April 1993
Identified colour standard
CDET2
CDET2
CDET2 standard
0
0
0
0
0
0
1
1
0
1
0
1
PAL-B/G, -H, -I; 50 Hz
PAL-N; 50 Hz
SECAM; 50 Hz
PAL-M; 60 Hz
1
1
1
1
0
0
1
1
0
1
0
1
PAL 4.43; 60 Hz
NTSC-M; 60 Hz
NTSC 4.43; 60 Hz
black/white
31
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
Table 6
SAA7151B
I2C-bus; subaddress and data bytes for writing (X in address byte = 0; slave address 8A (hex) at
IICSA = LOW or 8E at IICSA = HIGH)
data byte
function
subaddress byte
D7
D6
D5
D4
D3
D2
D1
D0
increment delay
H-sync HSY begin
H-sync HSY stop
00
01
02
IDEL7
HSYB7
HSYS7
IDEL6
HSYB6
HSYS6
IDEL5
HSYB5
HSYS5
IDEL4
HSYB4
HSYS4
IDEL3
HSYB3
HSYS3
IDEL2
HSYB2
HSYS2
IDEL1
HSYB1
HSYS1
IDEL0
HSYB0
HSYS0
H-clamp HCL begin
H-clamp HCL stop
H-sync after PHI1
03
04
05
HCLB7
HCLS7
HPHI7
HCLB6
HCLS6
HPHI6
HCLB5
HCLS5
HPHI5
HCLB4
HCLS4
HPHI4
HCLB3
HCLS3
HPHI3
HCLB2
HCLS2
HPHI2
HCLB1
HCLS1
HPHI1
HCLB0
HCLS0
HPHI0
luminance control
hue control
miscellaneous controls #1
06
07
08
BYPS
HUEC7
CSTD2
PREF
HUEC6
CSTD1
BPSS1
HUEC5
CSTD0
BPSS0
HUEC4
CKTQ4
BFBY
CORI
HUEC3 HUEC2
CKTQ3 CKTQ2
APER1 APER0
HUEC1 HUEC0
CKTQ1 CKTQ0
miscellaneous controls #2
PAL switch sensitivity
SECAM switch sensitivity
09
0A
0B
OSCE
PLSE7
SESE7
LFIS1
PLSE6
SESE6
LFIS0
PLSE5
SESE5
CKTS4
PLSE4
SESE4
CKTS3
PLSE3
SESE3
CKTS1
PLSE1
SESE1
miscellaneous controls #3
miscellaneous controls #4
miscellaneous controls #5
0C
0D
0E
FSAU
COLO
CCIR
GPSI2
CHSB
COFF
GPSI1
CGFX
GPSW0 SUVI
OEHS
OEVS
AMPF3 AMPF2
SXCR
FSDL2
UVSS
CHRS
AMPF1 AMPF0
FSDL1 FSDL0
CDMO CDPO
miscellaneous controls #6
miscellaneous controls #7
0F
10
AUFD
ASTD
FSEL
OFTS
HPLL
IPBP
SCEN
CDVI
VTRC
YDEL3
FSIV
YDEL1
chroma gain reference
miscellaneous controls #8
11
12
CHCV7
OEDY
CHCV6
OEDC
CHCV5
VNOI1
CHCV4
VNOI0
CHCV3 CHCV2
BFON
BOFL2
April 1993
32
CKTS2
PLSE2
SESE2
MUIV
YDEL2
CKTS0
PLSE0
SESE0
WIND
YDEL0
CHCV1 CHCV0
BOFL1 BOFL0
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
Function of the bits of Table 6
IDEL7 to IDEL0
“00”
Increment delay time, step size = 4/LL27 = 148 ns(1)
D7 D6 D5 D4
D3
D2 D1 D0 decimal number
note
1
1
1
1
1
1
1
1
minimum −148 ns
1
0
0
1
0
0
1
0
1
0
0
1
0
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
0
1
−215
−31.85 µs (outside central counter range
at FSEL = 1 (2))
0
0
1
0
1
0
0
0
−216
−32.0 µs (maximum value at FSEL = 0 (2))
0
0
1
0
0
1
1
1
−217 to −256
−32.148 µs (outside central counter range
at FSEL = 0 (2))
0
0
0
0
0
0
0
−1 to −110
−111 to −214
−16.3 µs (outside available range)
−16.44 µs
−31.7 µs (maximum value at FSEL = 1)
−37.9 µs (outside central counter (2))
0
HSYB7 to HSYB0
Horizontal sync begin, step size = 2/LL27 = 74 ns
HSYS7 to HSYS0
Horizontal sync stop, step size = 2/LL27 = 74 ns
“01” and “02”
D7
D6 D5 D4
D3
D2 D1
D0 decimal multiplier
note
1
0
1
1
1
1
1
1
−14.2 µs (maximum negative value)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
191 to 1
0
−1 to −64
−74 ns
0 equals reference value
+74 ns
+4.7 µs
HCLB7 to HCLB0
Horizontal clamp begin, step size = 2/LL27 = 74 ns
HCLS7 to HCLS0
Horizontal clamp stop, step size = 2/LL27 = 74 ns
“03” and “04”
D7
D6 D5 D4
D3
D2 D1
D0 decimal multiplier
note
0
1
1
1
1
1
1
1
−9.4 µs (maximum negative value)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
−1 to −128
127 to 1
−74 ns
0 equals reference value
+74 ns
+9.5 µs (maximum positive value)
HPHI7 to HPHI0
Horizontal sync start, step size = 8/LL27 = 296 ns
“05”
D7
D6 D5 D4
D3
D2 D1
D0 decimal multiplier
note
0
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
) forbidden (outside available central
)
counter range)
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0 equals reference value
1
1
1
0
1
0
1
1
1
0
1
1
1
0
1
1
−1 to −107
+0.296 µs
+31.7 µs (maximum positive value)
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
−108 to −128
) forbidden (outside available central
)
counter range)
April 1993
+127 to +109
+108 to +1
33
−32 µs (maximum negative value)
−0.296 ns
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
BYPS
“06”
Input mode select bit:
0 = CVBS mode (chroma trap active)
1 = S-Video mode (chroma trap by-passed)
PREF
Use of pre-emphasis (to be used if chrominance trap is active):
0 = pre-filter bypassed; 1 = pre-filter on
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
BPSS1 to BPSS0
Aperture bandpass to select different centre frequencies (Figures 25 to 40):
BPSS1
BPSS0
centre frequency
0
0
1
1
0
1
0
1
4.1 MHz
3.8 MHz
2.6 MHz
2.9 MHz
BFBY
Bandfilter bypass switching:
0 = bandfilter active; 1 = bandfilter bypassed
CORI
Coring function:
0 = coring off; 1 = ±1 LSB coring
APER1 to APER0
Aperture factor (Figures 25 to 40):
APER1
APER0
factor
0
0
1
1
0
1
0
1
0
0.25
0.5
1
HUE7 to HUE0
“07”
Hue control from +178.6° to −180.0°, equals data bytes 7F to 80 (hex); 0° equals 00.
CSTD2 to CSTD0
Forced colour standard of input signal;
“08”
CSTD2
CSTD1
CSTD0
standard
0
0
0
0
0
0
1
1
0
1
0
1
PAL-B/G, -H, -I; 50 Hz
PAL-N; 50 Hz
SECAM; 50 Hz
PAL-M; 60 Hz
1
1
1
1
0
0
1
1
0
1
0
1
PAL 4.43; 60 Hz
NTSC-M; 60 Hz
NTSC 4.43; 60 Hz
black/white
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
CKTQ4 to CKTQ0
April 1993
Colour killer threshold QAM (PAL/NTSC):
CKTQ4
CKTQ3
CKTQ2
CKTQ1
CKTQ0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
34
approximately −30 to −24 dB
−24 dB to −18 dB
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
OSCE
“09”
SAA7151B
External UV offset compensation: 0 = disabled; 1 = enabled
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
LFIS1 to LFIS0
Chrominance gain control (AGC filter):
LFIS1
LFIS0
control of loop filter time constant
0
0
1
1
0
1
0
1
slow
medium
fast
actual gain, stored (for test purposes only)
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
CKTS4 to CKTS0
Colour killer threshold SECAM as previously described under CKTQ subaddress “08”
PLSE7 to PLSE0
“0A”
PAL switch sensitivity from LOW to HIGH (HIGH means immediate sequence correction), equals FF to
00 (hex), MEDIUM equals 80.
SESE7 to SESE0
“0B”
SECAM switch sensitivity from LOW to HIGH (HIGH means immediate sequence correction), equals FF
to 00 (hex), MEDIUM equals 80.
FSAU; GPSI2,
Set port outputs (general purpose switching, internal)
and GPSI1
FSAU
GPSI2
GPSI1
output GPSW2 (pin 25)
output GPSW1 (pin 24)
“0C”
0
0
0
0
0
0
1
1
0
1
0
1
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
1
X
X
status bit FSST1 set
status bit FSST0 set
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
CGFX
Chrominance gain pre-determination: 0 = gain controlled via loop; 1 = gain set by AMPF-bits
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
AMPF3 to AMPF0
April 1993
Chrominance amplification factor
AMPF3
AMPF2
AMPF1
AMPF0
gain
0
0
0
⋅
1
0
1
1
⋅
1
0
0
0
⋅
1
0
0
1
⋅
1
−6 dB
0 dB
+1.5 dB
+3 to +16.5 dB (approximately 1.5 dB steps)
+17 dB
35
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
COLO
“0D”
Colour-on bit:
0 = colour-killer automatically enabled;
1 = forced colour-on.
CHSB
Chrominance (UV) output code:
0 = two’s complement; 1 = straightly binary
GPSW0
General purpose port output (pin 63):
0 = LOW; 1 = HIGH
SUVI
SECAM UV output signal polarity:
0 = U and V positive; 1 = U and V negative
SXCR
SECAM cross-colour reduction:
0 = off; 1 = on
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
FDSL2 to FDSL0
Fast switching delay adjustment in 37 ns steps:
FDSL2
FDSL1
FDSL0
delay
0
0
0
0
0
0
1
1
0
1
0
1
0
37 ns
74 ns
111 ns
1
1
1
1
0
0
1
1
0
1
0
1
−148 ns (negative delay)
−111 ns
−74 ns
−37 ns
CCIR
“0E”
Set CCIR mode: 0 = digital TV mode (DTV); 1 = CCIR mode
COFF
Set colour off: 0 = colour on; 1 = colour off
OEHS
Enable horizontal sync outputs HS and HREF:
OEVS
Enable vertical sync output VS:
0 = output high-impedance; 1 = VS enabled
UVSS
Select UV pixel sample:
1 = first pixel after U/V signal has changed;
0 = second pixel (free of crosstalk signals)
CHRS
S-Video input mode:
0 = chrominance signal from CVBS or CUV input
and controlled by BYPS (subaddress 06);
1 = S-Video mode; chrominance signal from CUV input
0 = output high-impedance;
1 = HS and HREF enabled
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
CDMO, CDPO
Chrominance delay:
CDMO
CDPO
0
1
0
0
X
1
no delay
−37 ns (negative delay)
+37 ns
AUFD
“0F”
Automatic field detection:
0 = field selection by FSEL-bit;
1 = automatic field detection
FSEL
Field select (AUFD-bit = 0):
0 = 50 Hz (625 lines);
1 = 60 Hz (525 lines)
HPLL
Horizontal PLL:
0 = PLL closed; 1 = PLL open, horizontal frequency fixed
SCEN
Sync and clamping pulse enable:
0 = HCL and HSY outputs HIGH (pins 26 and
29);
1 = HCL and HSY outputs active.
VTRC
VTR/TV mode select:
0 = TV mode (slow time constant);
1 = VTR mode (fast time constant).
MUIV
MUXC signal invertion:
0 = inverted; 1 = not inverted
FSIV
Fast switch input signal inversion:
0 = not inverted; 1 = inverted
WIND
Narrow fast switch window:
0 = off; 1 = on
April 1993
36
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
ASTD
“10”
Automatic standard switching:
SAA7151B
0 = off; 1 = on
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
OFTS
Select output format:
0 = 4 : 1 : 1 format; 1 = 4 : 2 : 2 format.
IPBP
External UV signal interpolation filter:
0 = active; 1 = bypassed
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
CDVI
Chrominance PLL filter selection for:
0 = VTR or TV source; 1 = fast time constant
for FSC-PLL (only for special applications)
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
YDEL3 to YDEL0
Luminance delay compensation in 37 ns steps:
YDEL3
YDEL2
YDEL1
YDEL0
0
0
0
1
0
1
0
1
)
)
1
1
0
1
0
1
0
1
)
)
delay
0 to 259 ns (step 0 to 7)
−296 to −37 ns (negative delay; step -8 to
-1)
CHCV7 to CHCV0 Chroma gain reference value
“11”
D7
D6 D5 D4
D3
D2 D1
D0
1
1
:
0
:
0
:
0
1
:
0
:
1
:
0
1
1
1
1
0
1
0
0
1
0
0
April 1993
1
1
1
1
1
0
1
1
1
0
0
0
gain
maximum gain
to
DTV level
to
CCIR level
to
minimum gain
37
)
)
) default programmed values
) dependent on application
)
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
OEDY
“12”
OEDC
Enable Y signals on YUV-bus:
SAA7151B
0 = output high-impedance; 1 = output active
(dependent on FEIN)
0 = output high-impedance; 1 = output active
(dependent on FEIN)
Enable UV signals on YUV-bus:
−-−-−-−-−-−-−-−-− -−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−-−
VNOI1, VNOI0
Vertical noise reduction mode:
VNOI1
VNOI0
mode
0
0
1
1
0
1
0
1
normal
searching
free-running
bypassed
BFON
Bottom flutter compensation switching: 0 = off; 1 = on (controlled by BOFL-bit)
BOFL2 to BOFL0
Bottom flutter compensation
BOFL2
BOFL1
BOFL0
start at line number
0
0
⋅
1
1
0
0
⋅
1
1
0
1
⋅
0
1
297 for PAL (247 for NTSC; active to end of field)
298 for PAL (248 for NTSC; active to end of field)
.
.
303 for PAL (253 for NTSC; active to end of field)
304 for PAL (254 for NTSC; active to end of field)
The bottom flutter circuit is able to compensate for horizontal phase jump of up to ±16 µs.
Note: The bottom flutter gate is active at
- HPLL is locked
- HPLL in VTR mode
- the vertical noise limiter (VNL)
is in the VTR mode
- gating is switched by
BFON-bit = 1 (subaddress 12)
vertical
pulse
programmable by BOFL(2-0)
gate 2
Gate 2
Gate 1
HPLL function
0
1
0
1
0
0
1
1
normal
disabled
double speed
unused
000
111
gate 1
Notes
1. an internal sign-bit D8 set to HIGH indicates that all values are always negative
2. H-PLL does not operate in this condition; the system clock frequency is set to a value fixed by the last update and is
within ±7.1 % of the nominal frequency.
April 1993
38
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
MEH326
0
VY −6
(dB)
−12
VY −6
(dB)
−12
−18
−18
−24
−24
−30
−30
NTSC
PAL
−36
−36
−42
−42
−48
MEH325
0
handbook, halfpage
handbook, halfpage
−48
0
2
4
6
8
0
2
4
6
8
fY (MHz)
fY (MHz)
Fig.22 Frequency response of chroma stop filter in
colour-difference mode for 50 Hz PAL. Filter
is only active in fast switching mode, but
bypassed in RGB mode. The selected filter
is dependent on actual detected colour
standard.
Fig.23 Frequency response of chroma stop filter in
colour-difference mode for 60 Hz NTSC.
Filter is only active in fast switching mode,
but bypassed in RGB mode. The selected
filter is dependent on actual detected colour
standard.
MEH327
0
handbook, halfpage
VY −6
(dB)
−12
−18
−24
−30
SECAM
−36
−42
−48
0
2
4
6
8
fY (MHz)
Fig.24 Frequency response of chroma stop filter colour-difference mode for 50 Hz SECAM. Filter is only active
in fast switching mode, but bypassed in RGB mode. The selected filter is dependent on actual detected
colour standard.
April 1993
39
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
MEH309
18
handbook, full pagewidth
63h
12
73h
VY
(dB)
53h
6
43h
43h
53h
0
63h
−6
73h
−12
−18
−24
−30
50 Hz PAL/SECAM;
pre-filter on
0
1
2
3
4
5
6
7
fY (MHz)
Fig.25 Maximum luminance peaking control as a function of four different aperture centre frequencies
controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter on; and
bandfilter on.
MEH310
18
handbook, full pagewidth
12
VY
(dB)
43h
6
42h
43h
41h
0
42h
−6
40h
41h
40h
−12
−18
−24
50 Hz PAL/SECAM;
pre-filter on
−30
0
1
2
3
4
5
6
7
fY (MHz)
Fig.26 3.8 MHz luminance peaking control as a function of four different aperture factors controllable by
subaddress byte 06; coring off; chroma trap on; pre-filter on and bandfilter on.
April 1993
40
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
MEH311
18
handbook, full pagewidth
23h
12
33h
VY
(dB)
6
03h
13h
0
23h
33h
−6
13h
03h
−12
−18
−24
−30
50 Hz PAL/SECAM;
pre-filter off
0
1
2
3
4
5
6
7
fY (MHz)
Fig.27 Maximum luminance peaking control as a function of four different aperture centre frequencies controllable
by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter off; and bandfilter on.
MEH312
18
handbook, full pagewidth
12
VY
(dB)
02h
6
03h
0
01h
02h
03h
00h
−6
01h
−12
00h
−18
−24
50 Hz PAL/SECAM;
pre-filter off
−30
0
1
2
3
4
5
6
7
fY (MHz)
Fig.28 4.1 MHz luminance peaking control as a function of four different aperture factors controllable by
subaddress byte 06; coring off; chroma trap on; pre-filter off and bandfilter on.
April 1993
41
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
MEH313
18
handbook, full pagewidth
73h
12
63h
VY
(dB)
43h
53h
53h
6
43h
63h
73h
0
−6
−12
−18
−24
−30
60 Hz NTSC;
pre-filter on
0
1
2
3
4
5
6
7
fY (MHz)
Fig.29 Maximum luminance peaking control as a function of four different aperture centre frequencies
controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter on; and
bandfilter on.
MEH314
18
handbook, full pagewidth
12
40h
42h
43h
VY
(dB)
41h
6
41h
0
40h
42h
43h
−6
−12
−18
−24
60 Hz NTSC;
pre-filter on
−30
0
1
2
3
4
5
6
7
fY (MHz)
Fig.30 3.8 MHz luminance peaking control as a function of four different aperture factors controllable by
subaddress byte 06; coring off; chroma trap on; pre-filter on and bandfilter on.
April 1993
42
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
MEH315
18
handbook, full pagewidth
12
VY
(dB)
33h
23h
6
03h
13h
13h
03h
0
23h
33h
−6
−12
−18
−24
−30
60 Hz NTSC;
pre-filter off
0
1
2
3
4
5
6
7
fY (MHz)
Fig.31 Maximum luminance peaking control as a function of four different aperture centre frequencies
controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter off; and
bandfilter on.
MEH316
18
handbook, full pagewidth
12
VY
(dB)
03h
6
03h
02h
02h
0
01h
00h
−6
00h
01h
−12
−18
−24
60 Hz NTSC;
pre-filter off
−30
0
1
2
3
4
5
6
7
fY (MHz)
Fig.32 4.1 MHz luminance peaking control as a function of four different aperture factors controllable by
subaddress byte 06; coring off; chroma trap on; pre-filter off and bandfilter on.
April 1993
43
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
MEH317
MEH318
24
24
handbook, halfpage
handbook, halfpage
83h
VY
18
VY
82h
(dB)
A3h
18
(dB)
12
A2h
12
A1h
81h
6
6
80h
A0h
0
0
−6
−6
50 Hz S-Video;
chroma trap off
−12
0
2
4
6
50 Hz S-Video;
chroma trap off
−12
8
0
2
4
6
fY (MHz)
Fig.33 4.1 MHz luminance peaking control as a
function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass
filter on.
Fig.34 2.6 MHz luminance peaking control as a
function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass
filter on.
MEH319
MEH320
24
24
handbook, halfpage
handbook, halfpage
VY
8
fY (MHz)
18
83h
(dB)
VY
A3h
(dB)
82h
12
18
12
A2h
6
A1h
81h
6
80h
A0h
0
0
−6
−6
60 Hz S-Video;
chroma trap off
60 Hz S-Video;
chroma trap off
−12
0
2
4
6
−12
8
Fig.35 4.1 MHz luminance peaking control as a
function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass
filter on.
April 1993
0
2
4
6
8
fY (MHz)
fY (MHz)
Fig.36 2.6 MHz luminance peaking control as a
function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass
filter on.
44
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
MEH322
MEH321
18
18
handbook, halfpage
handbook, halfpage
83h
8Bh
12
12
VY
82h
VY
(dB)
81h
(dB)
8Ah
6
6
89h
80h
88h
0
0
−6
−6
−12
−12
60 Hz Y/C;
all filters off
50 Hz Y/C;
all filters off
−18
0
2
4
6
−18
8
0
2
4
6
8
fY (MHz)
fY (MHz)
Fig.37 4.1 MHz luminance peaking control in
50 Hz / S-VHS mode as a function of four
different aperture factors controllable by
subaddress byte 06.
Fig.38 4.1 MHz luminance peaking control in
60 Hz / S-VHS mode as a function of four
different aperture factors controllable by
subaddress byte 06.
MEH323
MEH324
24
24
handbook, halfpage
handbook, halfpage
B3h
VY
18
A3h
83h
VY
93h
(dB)
B3h
18
A3h
83h
(dB)
12
12
83h
93h
83h
B3h
6
B3h
6
A3h
93h
A3h
93h
0
0
−6
−6
50 Hz Y/C;
bandfilter on
−12
0
2
4
6
60 Hz Y/C;
bandfilter on
−12
8
fY (MHz)
2
4
6
8
fY (MHz)
Fig.39 Maximum luminance peaking control in
50 Hz / S-VHS mode as a function of four
aperture centre frequencies controllable by
subaddress byte 06.
April 1993
0
Fig.40 Maximum luminance peaking control in
60 Hz / S-VHS mode as a function of four
aperture centre frequencies controllable by
subaddress byte 06.
45
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
PROGRAMMING EXAMPLE
Coefficients to set operation for application circuits Figures 19, 20 and 21. Values recommended for PAL CVBS input
signal and 4:2:2 CCIR output signal (all numbers of the Table 6 are hex values).
Table 7
Recommended default values (note 1)
SUBADDRESS BIT NAME
FUNCTION
VALUE (HEX)
00
01
02
IDEL(7-0)
HSYB(7-0)
HSYS(7-0)
increment delay
horizontal sync HSY begin
horizontal sync HSY stop
4D
3D
0D
03
04
05
HCLB(7-0)
HCLS(7-0)
HPHI(7-0)
horizontal clamping HCL begin
horizontal clamping HCL stop
horizontal sync after PHI1
F3
C6
FB
06
BYPS, PREF, BPSS(1-0)
BFBY, CORI, APER(1-0)
luminance bandwidth control:
02 (note 2)
07
HUEC(7-0)
hue control (0 degree)
00
08
CSTD(2-0), CKTQ(4-0)
miscellaneous controls #1
09
09
OSCE, LFIS(1-0), CKTS(4-0)
miscellaneous controls #2
C0
0A
PLSE(7-0)
PAL switch sensitivity
4D
0B
SESE(7-0)
SECAM switch sensitivity
40
0C
FSAU, GPSI(2-1), CGFX,
AMPF(3-0)
miscellaneous controls #3
80
0D
COLO, CHSB, GPSW0,
SUVI, SXCR, FSDL(2-0)
miscellaneous controls #4
60
CCIR, COEF, OEHS, OEVS
UVSS, CHRS, CDMO, CDPO
miscellaneous controls #5
B4
AUFD, FSEL, HPLL, SCEN,
VTRC, MUIV, FSIV, WIND
miscellaneous controls #6
9F
ASTD, OFTS, IPBP, CDVI,
YDEL(3-0)
miscellaneous controls #7
C0
11
CHCV(7-0)
nominal chrominance gain
4F
12
OEDY, OEDC, VNOI(1-0),
BFON, BOFL(2-0)
miscellaneous controls #8
C2
0E
0F
10
Notes
1. Slave address is 8A (hex) at IICSA = LOW or 8E (hex) at IICSA = HIGH.
2. Dependent on applications (Figures 25 to 40).
April 1993
46
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
PACKAGE OUTLINE
PLCC68: plastic leaded chip carrier; 68 leads
SOT188-2
eD
eE
y
X
60
A
44
43 Z E
61
bp
b1
w M
68
1
HE
E
pin 1 index
A
e
A4 A1
(A 3)
β
9
k1
27
Lp
k
detail X
10
26
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT
A
A1
min.
A3
A4
max.
bp
b1
mm
4.57
4.19
0.51
0.25
3.30
0.53
0.33
0.81
0.66
0.180
inches
0.020 0.01
0.165
D (1)
E (1)
e
eD
eE
HD
HE
k
24.33 24.33
23.62 23.62 25.27 25.27 1.22
1.27
24.13 24.13
22.61 22.61 25.02 25.02 1.07
k1
max.
Lp
v
w
y
0.51
1.44
1.02
0.18
0.18
0.10
Z D(1) Z E (1)
max. max.
2.16
β
2.16
45 o
0.930 0.930 0.995 0.995 0.048
0.057
0.021 0.032 0.958 0.958
0.020
0.05
0.007 0.007 0.004 0.085 0.085
0.13
0.890 0.890 0.985 0.985 0.042
0.040
0.013 0.026 0.950 0.950
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT188-2
112E10
MO-047AC
April 1993
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-03-11
47
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
SOLDERING
Wave soldering
Introduction
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream corners.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all PLCC
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
April 1993
48
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
April 1993
49