PHILIPS PHD10N10E

Philips Semiconductors
Product Specification
PowerMOS transistor
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suuitable for
surface mounting. The device is
intended for use in Switched Mode
Power Supplies (SMPS), motor
control, welding, DC/DC and AC/DC
converters, and in general purpose
switching applications.
PINNING - SOT428
PIN
PHD10N10E
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state resistance
100
11
60
175
0.25
V
A
W
˚C
Ω
PIN CONFIGURATION
DESCRIPTION
1
gate
2
drain
3
source
SYMBOL
d
tab
g
2
tab
s
drain
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg
Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction Temperature
RGS = 20 kΩ
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
- 55
-
100
100
30
11
7.7
44
60
175
175
V
V
V
A
A
A
W
˚C
˚C
THERMAL RESISTANCES
SYMBOL
PARAMETER
Rth j-mb
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
Rth j-a
September 1997
CONDITIONS
pcb mounted, minimum
footprint
1
TYP.
MAX.
UNIT
-
2.5
K/W
50
-
K/W
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Zero gate voltage drain current
Gate source leakage current
Drain-source on-state
resistance
VGS = 0 V; ID = 0.25 mA
100
-
-
V
VDS = VGS; ID = 1 mA
VDS = 100 V; VGS = 0 V; Tj = 25 ˚C
VDS = 100 V; VGS = 0 V; Tj = 125 ˚C
VGS = ±30 V; VDS = 0 V
VGS = 10 V; ID = 5.5 A
2.1
-
3.0
1
0.1
10
0.22
4.0
10
1.0
100
0.25
V
µA
mA
nA
Ω
MIN.
TYP.
MAX.
UNIT
VGS(TO)
IDSS
IDSS
IGSS
RDS(ON)
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
gfs
Forward transconductance
VDS = 25 V; ID = 5.5 A
3
4.2
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
400
90
35
500
120
50
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 3 A;
VGS = 10 V; RGS = 50 Ω;
Rgen = 50 Ω
-
9
25
30
20
14
40
45
40
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from tab to centre of die
Measured from source lead solder
point to source bond pad
-
4.5
7.5
-
nH
nH
MIN.
TYP.
MAX.
UNIT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
IDR
-
-
-
11
A
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
IF = 11 A ; VGS = 0 V
-
1.2
44
1.5
A
V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 11 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
90
0.35
-
ns
µC
MIN.
TYP.
MAX.
UNIT
-
-
35
mJ
AVALANCHE LIMITING VALUE
Tmb = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 11 A ; VDD ≤ 50 V ;
VGS = 10 V ; RGS = 50 Ω
September 1997
2
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
120
PHD10N10E
Normalised Power Derating
PD%
1E+01
110
Zth j-mb / (K/W)
BUKX52
100
90
80
1E+00
70
0.5
0.2
0.1
0.05
1E-01 0.02
60
50
40
30
tp
PD
10
0
20
40
60
80 100
Tmb / C
120
140
160
180
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
1E-05
1E-03
t/s
1E-01
1E+01
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
t
T
1E-02
1E-07
0
120
tp
T
D=
0
20
20
BUK452-100A
ID / A
20
15
10
110
VGS / V =
100
90
8
15
80
7
70
60
10
50
6
40
30
5
20
5
4
10
0
0
20
40
60
80 100
Tmb / C
120
140
160
0
180
2
4
6
8
10
VDS / V
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
100
0
ID / A
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
BUK452-100
1.0
BUK452-100A
RDS(ON) / Ohm
A
ID
S/
)=
VD
B
N
O
S(
5.5
6
VGS / V =
6.5
7
tp = 10 us
RD
10
4.5 5
0.8
7.5
8
0.6
100 us
DC
1 ms
10
0.4
20
10 ms
100 ms
1
0.2
0
0.1
1
10
100
VDS / V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
September 1997
0
2
4
6
8
10 12
ID / A
14
16
18
20
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
3
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
ID / A
VGS(TO) / V
BUK452-100A
max.
4
20
25
Tj / C =
16
typ.
3
150
12
min.
2
8
1
4
0
0
0
2
4
6
8
10
-60
-20
20
60
Tj / C
VGS / V
gfs / S
BUK452-100A
180
1E-02
3
1E-03
2
1E-04
1
1E-05
SUB-THRESHOLD CONDUCTION
ID / A
1E-01
4
2%
typ
98 %
1E-06
0
0
2
4
6
8
10
ID / A
12
14
16
18
0
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
2.4
140
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
5
100
2
VGS / V
3
4
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised RDS(ON) = f(Tj)
a
1
10000
BUK4y2-100
C / pF
2.2
2.0
1.8
1.6
1000
1.4
Ciss
1.2
1.0
0.8
100
Coss
0.6
0.4
Crss
0.2
0
-60
-20
20
60
Tj / C
100
140
10
180
0
40
VDS / V
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5.5 A; VGS = 10 V
September 1997
20
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
4
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
BUK452-100
VGS / V
12
120
WDSS%
110
VDS / V =20
10
100
90
80
8
80
70
60
6
50
40
4
30
20
2
10
0
0
0
2
4
6
8
20
10
40
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 11 A; parameter VDS
IF / A
60
80
100
120
Tmb / C
140
160
180
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 11 A
BUK452-100A
VDD
+
L
20
VDS
-
VGS
-ID/100
10
T.U.T.
0
Tj / C =
25
150
RGS
R 01
shunt
0
0
1
VSDS / V
2
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
September 1997
5
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
MECHANICAL DATA
Dimensions in mm : Net Mass: 1.4 g
seating plane
6.73 max
1.1
tab
2.38 max
0.93 max
5.4
4 min
6.22 max
10.4 max
4.6
2
1
0.5
0.5 min
3
0.3
0.5
0.8 max
(x2)
2.285 (x2)
Fig.17. SOT428 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15
1.5
2.5
4.57
Fig.18. SOT428 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
September 1997
6
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD10N10E
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
September 1997
7
Rev 1.000