INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4006B MSI 18-stage static shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4006B MSI 18-stage static shift register 5-stage shift registers each have a data input (DC, DD) and data outputs from the fourth and fifth stages (O3C, O4C, O3D, O4D). DESCRIPTION The HEF4006B is an 18-stage shift register arranged as two 4-stage and two 5-stage shift registers with a common clock input (CP). The two 4-stage shift registers each have a data input (DA, DB) and a data output (O3A, O3B); the two The registers can be operated in parallel or interconnected to form a single shift register of up to 18 bits. Data are shifted into the first register position of each register from the data inputs (DA to DD) and all the data in each register are shifted one position to the right on the HIGH to LOW transition of CP. Fig.2 Pinning diagram. HEF4006BP(N): 14-lead DIL; plastic (SOT27-1) HEF4006BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4006BT(D): 14-lead SO; plastic (SOT108-1) Fig.1 Functional diagram. ( ): Package Designator North America FUNCTION TABLE Dn CP PINNING On(5) D1 D1 X no change DA to DD data inputs CP clock input (HIGH to LOW; edge-triggered) O3A to O3D; O4C; O4D data outputs Notes FAMILY DATA, IDD LIMITS category MSI 1. X = state is immaterial See Family Specifications 2. = positive-going transition 3. = negative-going transition 4. D1 = either HIGH or LOW 5. The moment D1 appears at O depends on the register length. January 1995 2 Philips Semiconductors Product specification HEF4006B MSI 18-stage static shift register Fig.3 Logic diagram. January 1995 3 Philips Semiconductors Product specification HEF4006B MSI 18-stage static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN TYPICAL EXTRAPOLATION FORMULA TYP MAX 90 180 ns 63 ns + (0,55 ns/pF) CL 40 80 ns 29 ns + (0,23 ns/pF) CL 30 60 ns 22 ns + (0,16 ns/pF) CL 90 180 ns 63 ns + (0,55 ns/pF) CL 40 85 ns 29 ns + (0,23 ns/pF) CL 35 70 ns 27 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL Propagation delays CP → On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 Output transition times HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 tTLH 15 Minimum clock pulse width; HIGH Set-up time Dn → CP Hold time Dn → CP Maximum clock pulse frequency 5 package (P) ns 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 60 30 ns 20 ns 15 30 15 ns 5 20 10 ns 10 tWCPH 10 5 ns 15 5 0 ns 5 5 −5 ns 10 tsu 5 0 ns 15 5 0 ns 5 9 18 MHz 15 30 MHz 18 36 MHz 10 VDD V dissipation per 120 40 10 15 Dynamic power 60 30 5 10 15 thold fmax 10 ns + (1,0 ns/pF) CL see also waveforms Fig.4 TYPICAL FORMULA FOR P (µW) 600 fi + ∑ (foCL) × VDD2 3200 fi + ∑ (foCL) × VDD 11 600 fi + ∑ (foCL) × 2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification HEF4006B MSI 18-stage static shift register Fig.4 Waveforms showing minimum clock pulse width, and set-up and hold-times for Dn to CP. Set-up and hold times are shown as positive values but may be specified as negative values. January 1995 5