INTEGRATED CIRCUITS DATA SHEET 74LVC162373A; 74LVCH162373A 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state Product specification Supersedes data of 1999 Aug 05 2004 Feb 05 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination 74LVC162373A; resistors; 5 V tolerant inputs/outputs; 3-state 74LVCH162373A FEATURES DESCRIPTION • 5 V tolerant inputs/outputs for interfacing with 5 V logic The 74LVC(H)162373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One latch enable (pin nLE) input and one output enable (pin nOE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment. • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption • MULTIBYTE flow-through standard pin-out architecture • Low inductance multiple power and ground pins for minimum noise and ground bounce • Direct interface with TTL levels The 74LVC(H)162373A consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When pin nLE is HIGH, data at the corresponding data inputs (pins nDn) enter the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding data inputs changes. • All data inputs have bushold (74LVCH162373A only) • High-impedance when VCC = 0 V • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. When pin nLE is LOW the latches store the information that was present at the data inputs a set-up time preceding the HIGH-to-LOW transition of pin nLE. When pin nOE is LOW, the contents of the eight latches are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. • Specified from −40 to +85 °C and −40 to +125 °C. The 74LVCH162373A bushold data inputs eliminates the need for external pull-up resistors to hold unused inputs. The 74LVC(H)162373A is designed with 30 Ω series termination resistors in both high and low output stages to reduce line noise. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay nDn to nQn CL = 50 pF; VCC = 3.3 V 3.3 ns propagation delay nLE to nQn CL = 50 pF; VCC = 3.3 V 3.5 ns tPZH/tPZL 3-state output enable time nOE to nQn CL = 50 pF; VCC = 3.3 V 4.0 ns tPHZ/tPLZ 3-state output disable time nOE to nQn CL = 50 pF; VCC = 3.3 V 3.4 ns CI input capacitance 5.0 pF CPD power dissipation per latch outputs enabled 26 pF outputs disabled 19 pF VCC = 3.3 V; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; 2004 Feb 05 2 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION TYPE NUMBER 74LVC162373ADGG PACKAGE TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +125 °C 48 TSSOP48 plastic SOT362-1 74LVCH162373ADGG −40 to +125 °C 48 TSSOP48 plastic SOT362-1 74LVC162373ADL −40 to +125 °C 48 SSOP48 plastic SOT370-1 74LVCH162373ADL −40 to +125 °C 48 SSOP48 plastic SOT370-1 INTERNAL LATCH OUTPUT nQn FUNCTION TABLE Per section of eight bits; note 1 INPUT OPERATING MODES nLE nOE Enable and read register (transparent mode) nDn L H L L L L H H H H Latch and read register L L l L L L L h H H Latch register and disable outputs H L l L Z H L h H Z Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. 2004 Feb 05 3 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state PINNING SYMBOL 1OE SYMBOL 74LVC162373A; 74LVCH162373A PIN DESCRIPTION PIN DESCRIPTION 1D1 46 data input 1 output enable input (active LOW) 1D0 47 data input 1LE 48 latch enable input (active HIGH) 1Q0 2 data output 1Q1 3 data output GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) 1Q2 5 data output 1Q3 6 data output VCC 7, 18, 31, 42 1Q4 8 data output 1Q5 9 data output 1OE 1 48 1LE 1Q6 11 data output 1Q0 2 47 1D0 1Q7 12 data output 1Q1 3 46 1D1 data output GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 2Q0 13 supply voltage 2Q1 14 data output 2Q2 16 data output VCC 7 42 VCC 2Q3 17 data output 1Q4 8 41 1D4 data output 1Q5 9 40 1D5 2Q4 19 GND 10 39 GND 1Q6 11 38 1D6 2Q5 20 data output 2Q6 22 data output 2Q7 23 data output 2Q0 13 2OE 24 output enable input (active LOW) 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2LE 25 1Q7 12 latch enable input (active HIGH) 162373A 37 1D7 36 2D0 2D7 26 data input 2D6 27 data input 2Q5 20 29 2D5 2D5 29 data input GND 21 28 GND data input 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2LE 2D4 30 2D3 32 data input 2D2 33 data input 2D1 35 data input 2D0 36 data input 1D7 37 data input 1D6 38 data input 1D5 40 data input 1D4 41 data input 1D3 43 data input 1D2 44 data input 2004 Feb 05 001aaa336 Fig.1 Pin configuration SSOP48 and TSSOP48. 4 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A handbook, full pagewidth 1D0 1Q0 Q D 2D0 LE 2Q0 Q D LATCH 1 LATCH 9 LE LE 1LE 2LE 1OE 2OE to 7 other channels LE to 7 other channels MGU769 Fig.2 Logic diagram. 1 24 1OE 1LE 1OE 2OE 2OE 47 1D0 1Q0 2 46 1D1 1Q1 3 44 1D2 1Q2 5 43 41 1Q3 1D3 1Q4 1D4 2LE 1D0 6 1D1 8 1D2 40 1D5 1Q5 9 1D3 38 1D6 1Q6 11 1D4 12 1D5 37 1Q7 1D7 36 2D0 2Q0 13 1D6 35 2D1 2Q1 14 1D7 33 2D2 2Q2 16 2D0 32 2D3 2Q3 17 2D1 30 2D4 2Q4 19 2D2 29 2D5 2Q5 20 2D3 22 2D4 27 26 2Q6 2D6 2Q7 2D7 1LE 2D5 23 2D6 2LE 2D7 48 25 mgu768 24 25 47 1EN C3 2EN C4 3D 1 2 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 4D 2 13 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 mgu770 Fig.3 Logic symbol. 2004 Feb 05 1 48 Fig.4 Logic symbol (IEEE/IEC). 5 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state handbook, halfpage 74LVC162373A; 74LVCH162373A VCC input to internal circuit MNA428 Fig.5 Bushold circuit. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage VI input voltage VO output voltage Tamb operating ambient temperature tr, tf input rise and fall times CONDITIONS MIN. MAX. UNIT for maximum speed performance 2.7 3.6 V for low-voltage applications 1.2 3.6 V 0 5.5 V output HIGH or LOW state 0 VCC V output 3-state 0 5.5 V in free-air −40 +125 °C VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage −0.5 +6.5 V IIK input diode current VI < 0 − −50 mA VI input voltage note 1 −0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 − ±50 mA VO output voltage output HIGH or LOW state; note 1 −0.5 VCC + 0.5 V output 3-state; note 1 −0.5 +6.5 V VO = 0 to VCC IO output source or sink current − ±50 mA ICC, IGND VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 500 mW Tamb = −40 to +125 °C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. 2004 Feb 05 6 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = −40 to +85 °C; note 1 VIH 1.2 VCC − − V 2.7 to 3.6 2.0 − − V 1.2 − − GND V 2.7 to 3.6 − − 0.8 V IO = −100 µA 2.7 to 3.6 VCC − 0.2 VCC(2) − V IO = −6 mA 2.7 VCC − 0.5 − − V IO = −12 mA 3.0 VCC − 0.8 − − V IO = 100 µA 2.7 to 3.6 − GND(2) 0.20 V IO = 6 mA 2.7 − − 0.40 V IO = 12 mA 3.0 − − 0.55 V HIGH-level input voltage VIL LOW-level input voltage VOH HIGH-level output voltage VI = VIH or VIL VOL LOW-level output voltage VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND; note 3 3.6 − ±0.1 ±5 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND; note 3 3.6 − ±0.1 ±5 µA Ioff power-off leakage current VI or VO = 5.5 V 0 − ±0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 − 0.1 20 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 0.6 V; IO = 0 2.7 to 3.6 − 5(2) 500 µA IBHL bushold LOW sustaining current VI = 0.8 V; notes 4 and 5 3.0 75 − − µA IBHH bushold HIGH sustaining current VI = 2.0 V; notes 4 and 5 3.0 −75 − − µA IBHLO bushold LOW overdrive current notes 4 and 6 3.6 500 − − µA IBHHO bushold HIGH overdrive current notes 4 and 6 3.6 −500 − − µA 2004 Feb 05 7 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage 1.2 VCC − − V 2.7 to 3.6 2.0 − − V 1.2 − − GND V 2.7 to 3.6 − − 0.8 V HIGH-level output voltage VI = VIH or VIL LOW-level output voltage IO = −100 µA 2.7 to 3.6 VCC − 0.3 − − V IO = −6 mA 2.7 VCC − 0.65 − − V IO = −12 mA 3.0 VCC − 1 − − V IO = 100 µA 2.7 to 3.6 − − 0.3 V IO = 6 mA 2.7 − − 0.6 V IO = 12 mA VI = VIH or VIL 3.0 − − 0.8 V ILI input leakage current VI = 5.5 V or GND; note 3 3.6 − − ±20 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND; note 3 3.6 − − ±20 µA Ioff power off leakage current VI or VO = 5.5 V 0 − − ±20 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 − − 80 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 0.6 V; IO = 0 2.7 to 3.6 − − 5000 µA IBHL bushold LOW sustaining current VI = 0.8 V; notes 4 and 5 3.0 60 − − µA IBHH bushold HIGH sustaining current VI = 2.0 V; notes 4 and 5 3.0 −60 − − µA IBHLO bushold LOW overdrive current notes 4 and 6 3.6 500 − − µA IBHHO bushold HIGH overdrive current notes 4 and 6 3.6 −500 − − µA Notes 1. All typical values are measured at Tamb = 25 °C. 2. Measured at VCC = 3.3 V. 3. For bushold parts, the bushold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. 4. Valid for data inputs of bushold parts (LVCH162373A) only. For data inputs only; control inputs do not have a bushold circuit. 5. The specified sustaining current at the data inputs holds the input below the specified VI level. 6. The specified overdrive current at the data input forces the data input to the opposite logic input state. 2004 Feb 05 8 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω. CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note1 tPHL/tPLH propagation delay nDn to nQn propagation delay nLE to nQn tPZH/tPZL tPHZ/tPLZ tW tsu th tsk(0) 2004 Feb 05 see Fig 6 and 10 see Fig 7 and 10 3-state output enable time nOE to nQn see Fig 8 and 10 3-state output disable time nOE to nQn see Fig 8 and 10 nLE pulse width HIGH set-up time nDn to nLE hold time nDn to nLE skew see Fig 7 see Fig 9 see Fig 9 note 3 9 1.2 − 12 − ns 2.7 1.5 − 6.7 ns 3.0 to 3.6 1.0 3.3(2) 5.9 ns 1.2 − 14 − ns 2.7 1.5 − 7.0 ns 3.0 to 3.6 1.5 3.5(2) 6.1 ns 1.2 − 18 − ns 2.7 1.5 − 7.5 ns 3.0 to 3.6 1.0 4.0(2) 6.1 ns 1.2 − 11 − ns 2.7 1.5 − 4.8 ns 3.0 to 3.6 1.5 3.4(2) 4.6 ns 1.2 − − − ns 2.7 3.0 − − ns 3.0 to 3.6 3.0 2.0(2) − ns 1.2 − − − ns 2.7 2.0 − − ns 3.0 to 3.6 2.0 1.0(2) − ns 1.2 − − − ns 2.7 0.9 − − ns 3.0 to 3.6 0.9 −1.0(2) − ns 3.0 to 3.6 − − 1.0 ns Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C tPHL/tPLH propagation delay nDn to nQn propagation delay nLE to nQn tPZH/tPZL tPHZ/tPLZ tW tsu th tsk(0) see Fig 6 and 10 see Fig 7 and 10 3-state output enable time nOE to nQn see Fig 8 and 10 3-state output disable time nOE to nQn see Fig 8 and 10 nLE pulse width HIGH set-up time nDn to nLE hold time nDn to nLE skew see Fig 7 see Fig 9 see Fig 9 note 3 1.2 − − − ns 2.7 1.5 − 8.5 ns 3.0 to 3.6 1.0 − 7.5 ns 1.2 − − − ns 2.7 1.5 − 9.0 ns 3.0 to 3.6 1.5 − 8.0 ns 1.2 − − − ns 2.7 1.5 − 9.5 ns 3.0 to 3.6 1.0 − 8.0 ns 1.2 − − − ns 2.7 1.5 − 6.0 ns 3.0 to 3.6 1.5 − 6.0 ns 1.2 − − − ns 2.7 3.0 − − ns 3.0 to 3.6 3.0 − − ns 1.2 − − − ns 2.7 2.0 − − ns 3.0 to 3.6 2.0 − − ns 1.2 − − − ns 2.7 0.9 − − ns 3.0 to 3.6 0.9 − − ns 3.0 to 3.6 − − 1.5 ns Notes 1. All typical values are measured at Tamb = 25 °C. 2. Measured at VCC = 3.3 V. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2004 Feb 05 10 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A AC WAVEFORMS VI VM nDn input GND t PLH t PHL VOH VM nQn output VOL mna429 INPUT VCC VM VI tr = tf 1.2 V 0.5 × VCC VCC ≤ 2.5 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns VOL and VOH are the typical output voltage drop that occur with the output load. Fig.6 Input (nDn) to output (nQn) propagation delays. VI VM nLE input GND tW t PHL t PLH VOH VM nQn output VOL mna430 INPUT VCC VM VI tr = tf 1.2 V 0.5 × VCC VCC ≤ 2.5 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns VOL and VOH are the typical output voltage drop that occur with the output load. Fig.7 Latch enable input (nLE) pulse width, and the latch enable input to output (nQn) propagation delays. 2004 Feb 05 11 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A VI nOE input VM GND t PLZ t PZL VCC nQn output LOW-to-OFF OFF-to-LOW VM VX VOL t PHZ t PZH VOH VY nQn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled mna432 INPUT VCC VM VI VX = VOL + 0.3 V at VCC ≥ 2.7 V. VX = VOL + 0.1VCC at VCC < 2.7 V. VY = VOH − 0.3 V at VCC ≥ 2.7 V. VY = VOH − 0.1VCC at VCC < 2.7 V. tr = tf 1.2 V 0.5 × VCC VCC ≤ 2.5 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns VOL and VOH are the typical output voltage drop that occur with the output load. Fig.8 3-state enable and disable times. VI VM nDn input GND th th t su t su VI VM nLE input GND mna431 INPUT VCC VM VI tr = tf 1.2 V 0.5 × VCC VCC ≤ 2.5 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns The shaded areas indicate when the input is permitted to change for predictable performance. Fig.9 Data set-up and hold times for the nDn input to the nLE input. 2004 Feb 05 12 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state VEXT handbook, full pagewidth VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL MNA616 VCC VI CL RL VEXT tPLH/tPHL tPZH/tPHZ tPZL/tPLZ 1.2 V VCC 50 pF 500 Ω(1) open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 2 × VCC 3.0 to 3.6 V 2.7 V 50 pF 500 Ω open GND 2 × VCC Note 1. The circuit performs better when RL = 1000 Ω. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.10 Load circuitry for switching times. 2004 Feb 05 13 74LVC162373A; 74LVCH162373A Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A PACKAGE OUTLINES SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3) θ pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 2004 Feb 05 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 14 o Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 2004 Feb 05 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 15 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Feb 05 16 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/02/pp17 Date of release: 2004 Feb 05 Document order number: 9397 750 12674