INTEGRATED CIRCUITS 74F533*,74F534 Latch/flip-flop * Discontinued part. Please see the Discontinued Product List. Product specification Supersedes data of 1989 May 11 IC15 Data Handbook 1999 Jan 08 Philips Semiconductors Product specification Latch/flip-flop 74F533,* 74F534 74F533 Octal Transparent Latch, Inverting (3-State) 74F534 Octal D Flip-Flop, Inverting (3-State) The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus. FEATURES • 8-bit positive edge-triggered register – 74F534 • 3-State inverting output buffers • Common 3-State Output register • Independent register and 3-State buffer operation DESCRIPTION The 74F533 is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the Enable (E) input is High. The latch remains transparent to the data input while E is High and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F533 5.5ns 41mA TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F534 165MHz 51mA ORDERING INFORMATION DESCRIPTION The 74F534 is an 8-bit edge-triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the Clock (CP) and Output Enable (OE) control gates. COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 20-Pin Plastic DIP N74F534N SOT146-1 20-Pin Plastic SOL N74F534D SOT163-1 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION D0 - D7 Data inputs 1.0/1.0 20µA/0.6mA E (74F533) Enable input (active High) 1.0/1.0 20µA/0.6mA OE Output Enable input (active Low) 1.0/1.0 20µA/0.6mA CP (74F534) Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA Q0 - Q7 Data outputs 150/40 3.0mA/24mA * Discontinued part. Please see the Discontinued Products List. 1999 Jan 08 2 853-0374 20616 Philips Semiconductors Product specification Latch/flip-flop 74F533,* 74F534 NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state. PIN CONFIGURATION – 74F533 LOGIC SYMBOL (IEEE/IEC) – 74F533 OE 1 20 VCC 1 Q0 2 19 Q7 11 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 11 E GND 10 EN1 EN2 3 2D 2 1 4 5 7 6 8 9 13 12 14 15 17 16 18 19 SF00981 SF00985 PIN CONFIGURATION – 74F534 LOGIC SYMBOL – 74F534 OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 11 CP GND 10 SF00982 11 CP 1 OE 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 VCC=Pin 20 GND=Pin 10 SF00984 LOGIC SYMBOL – 74F533 LOGIC SYMBOL (IEEE/IEC) – 74F534 3 4 7 8 13 14 17 1 18 11 D0 11 1 D2 D3 D4 D5 D6 3 OE 2 Q1 5 Q2 6 Q3 9 Q4 12 Q5 15 Q6 16 C1 D7 E Q0 VCC=Pin 20 GND=Pin 10 D1 EN1 Q7 19 SF00983 2D 1 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 SF00986 * Discontinued part. Please see the Discontinued Products List. 1999 Jan 08 3 Philips Semiconductors Product specification Latch/flip-flop 74F533,* 74F534 LOGIC DIAGRAM – 74F533 D0 D1 3 D2 4 D E E OE D Q D3 7 E D4 8 D Q E D5 13 D Q E D6 14 D Q E D Q D7 17 E 18 D Q E D Q E Q 11 1 2 VCC=Pin 20 GND=Pin 10 5 Q0 6 Q1 9 Q2 12 Q3 15 Q4 16 Q5 19 Q6 Q7 SF00987 LOGIC DIAGRAM – 74F534 D0 D1 3 D2 4 D CP CP OE D Q D3 7 CP D Q D4 8 CP D Q D5 13 CP D Q D6 14 CP D Q D7 17 CP 18 D Q CP D Q CP Q 11 1 2 VCC=Pin 20 GND=Pin 10 5 6 Q1 Q0 9 Q2 12 Q3 15 Q4 16 Q5 Q6 19 Q7 SF00988 FUNCTION TABLE – 74F533 INPUTS OUTPUTS OE E Dn INTERNAL REGISTER L L H H L H L H H L Load and read register L L ↓ ↓ l h L H H L Enable and read register L L X NC NC H H L H X Dn NC Dn Z Z H = High voltage level h = High voltage level one setup time prior to the High-to-Low E transition L = Low voltage level l = Low voltage level one setup time prior to the High-to-Low E transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low E transition * Discontinued part. Please see the Discontinued Products List. 1999 Jan 08 OPERATING MODES Q0 – Q7 4 Hold Disable outputs Philips Semiconductors Product specification Latch/flip-flop 74F533,* 74F534 FUNCTION TABLE – 74F534 CP Dn INTERNAL REGISTER OUTPUTS OE INPUTS L L ↑ ↑ l h L H H L L ↑ X NC NC H H ↑ ↑ X Dn NC Dn Z Z H = h = L = l = NC= X = Z = ↑ = ↑ = OPERATING MODES Q0 – Q7 Load and read register Hold Disable outputs High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition No change Don’t care High impedance “off” state Low-to-High clock transition Not a Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL RATING UNIT VCC Supply voltage PARAMETER –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5.0 mA VOUT Voltage applied to output in High output state –0.5 to +VCC V IOUT Current applied to output in Low output state Tamb Operating free-air temperature range Tstg Storage temperature 48 mA 0 to +70 °C –65 to +125 °C RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –3 mA IOL Low-level output current 24 mA Tamb Operating free-air temperature range 70 °C 0 * Discontinued part. Please see the Discontinued Products List. 1999 Jan 08 5 V V Philips Semiconductors Product specification Latch/flip-flop 74F533,* 74F534 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH O LIMITS TEST CONDITIONS1 PARAMETER VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX High level output voltage High-level VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX MIN ±10%VCC 2.4 ±5%VCC 2.7 ±10%VCC TYP2 MAX UNIT V 3.3 V 0.35 0.50 V 0.35 0.50 V –0.73 –1.2 V 100 µA VOL O Low level output voltage Low-level VIK Input clamp voltage II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA IOZH Off-state output current, High-level voltage applied VCC = MAX, VO = 2.7V 50 µA IOZL Off-state output current, Low-level voltage applied VCC = MAX, VO = 0.5V –50 µA IOS Short-circuit output current3 –150 mA ICC Supply current (total) mA ±5%VCC VCC = MIN, II = IIK VCC = MAX 74F533 74F534 VCC = MAX –60 OE=4.5V, Dn=E=GND 41 61 OE=4.5V, Dn=GND 51 86 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL TEST CONDITIONS PARAMETER Tamb= +25°C VCC = +5V CL = 50pF, RL = 500Ω Tamb = 0°C to +70°C VCC = +5V ± 10% CL = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX Waveform 2 4.0 3.0 6.0 4.5 8.5 7.0 4.0 3.0 9.5 8.0 ns Waveform 3 5.0 3.0 6.5 4.5 9.5 7.0 5.0 3.0 10.0 8.0 ns Output Enable time to High or Low level Waveform 6 Waveform 7 2.0 2.0 4.5 5.0 7.0 7.0 2.0 2.0 8.0 8.0 ns tPHZ tPLZ Output Disable time from High or Low level Waveform 6 Waveform 7 2.0 2.0 3.5 3.0 6.0 5.5 2.0 2.0 7.0 6.5 ns fMAX Maximum Clock frequency Waveform 1 150 165 tPLH tPHL Propagation delay CP to Qn Waveform 1 3.0 3.0 4.5 4.5 7.0 7.0 2.5 2.5 7.5 7.5 ns tPZH tPZL Output Enable time to High or Low level Waveform 6 Waveform 7 2.0 2.0 4.5 5.0 7.5 7.5 2.0 2.0 8.5 8.5 ns tPHZ tPLZ Output Disable time from High or Low level Waveform 6 Waveform 7 2.0 2.0 3.5 3.5 6.5 5.5 2.0 2.0 7.5 6.5 ns tPLH tPHL Propagation delay Dn to Qn tPLH tPHL Propagation delay E to Qn tPZH tPZL 74F533 74F534 * Discontinued part. Please see the Discontinued Products List. 1999 Jan 08 6 135 MHz Philips Semiconductors Product specification Latch/flip-flop 74F533,* 74F534 AC SETUP REQUIREMENTS LIMITS SYMBOL Tamb= +25°C VCC = +5V CL = 50pF, RL = 500Ω TEST CONDITIONS PARAMETER MIN ts(H) ts(L) Setup time, Dn to E th(H) th(L) Hold time, Dn to E tw(H) TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX Waveform 4 1.5 0 1.5 0 ns Waveform 4 2.5 2.5 2.5 2.5 ns E Pulse width, High Waveform 3 3.0 3.0 ns ts(H) ts(L) Setup time, Dn to CP Waveform 5 2.0 2.0 2.5 2.5 ns th(H) th(L) Hold time, Dn to CP Waveform 5 0 0 0 0 ns tw(H) tw(L) CP pulse width, High or Low Waveform 1 3.0 3.5 3.5 4.0 ns 74F533 74F534 AC WAVEFORMS For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX Dn CP VM VM tW(H) Qn tPHL VM Qn VM tW(H) Qn VM tW(L) tPHL VM VM SF00991 Waveform 3. Propagation Delay, Enable Input to Output, and Enable Pulse Width * Discontinued part. Please see the Discontinued Products List. 1999 Jan 08 VM Waveform 2. Propagation Delay for Data to Output Dn tPLH VM SF00990 Waveform 1. Propagation Delay, Clock and Enable Inputs to Output, Enable, Clock Pulse Widths, and Maximum Clock Frequency VM tPLH VM SF00989 E VM tPHL tW(L) tPLH VM VM 7 Philips Semiconductors Product specification Latch/flip-flop 74F533,* 74F534 AC WAVEFORMS (Continued) For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. Dn VM VM VM ts(H) ts(L) th(H) E Dn VM th(L) VM VM VM VM VM ts(H) th(H) ts(L) th(L) CP VM VM VM SF00992 SF00191 Waveform 4. Data Setup and Hold Times Waveform 5. Data Setup and Hold Times OE OE VM VM VM VM tPZH Qn tPZL VOH -0.3V tPHZ tPLZ Qn VM VM VOL +0.3V 0V SF00994 SF00995 Waveform 6. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 7. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00777 * Discontinued part. Please see the Discontinued Products List. 1999 Jan 08 8 Philips Semiconductors Product specification Latch/flip-flop 74F533*, 74F534 DIP20: plastic dual in-line package; 20 leads (300 mil) * Discontinued part. Please see the Discontinued Product List. 1999 Jan 08 9 SOT146-1 Philips Semiconductors Product specification Latch/flip-flop 74F533*, 74F534 SO20: plastic small outline package; 20 leads; body width 7.5 mm * Discontinued part. Please see the Discontinued Product List. 1999 Jan 08 10 SOT163-1 Philips Semiconductors Product specification Latch/flip-flop 74F533*, 74F534 NOTES * Discontinued part. Please see the Discontinued Product List. 1999 Jan 08 11 Philips Semiconductors Product specification Latch/flip-flop 74F533*, 74F534 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: * Discontinued part. Please see the Discontinued Product List. yyyy mmm dd 12 Date of release: 10-98 9397-750-05132