PHILIPS 74F163A

INTEGRATED CIRCUITS
74F160A*, 74F161A,
74F162A*, 74F163A
4-bit binary counter
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Product specification
IC15 Data Handbook
1996 Jan 29
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
A Low level at the Master Reset (MR) input sets all the four outputs
of the flip-flops (Q0 – Q3) in 74F161A to Low levels, regardless of
the levels at CP, PE, CET and CEP inputs (thus providing an
asynchronous clear function). For the 74F163A, the clear function is
synchronous. A Low level at the Synchronous Reset (SR) input sets
all four outputs of the flip-flops (Q0 – Q3) to Low levels after the next
positive-going transition on the clock (CP) input (provided that the
setup and hold time requirements for SR are met). This action
occurs regardless of the levels at PE, CET, and CEP inputs. The
synchronous reset feature enables the designer to modify the
maximum count with only one external NAND gate (see Figure 1).
The carry look-ahead simplifies serial cascading of the counters.
Both Count Enable (CEP and CET) inputs must be High to count.
The CET input is fed forward to enable the TC output. The TC
output thus enabled will produce a High output pulse of a duration
approximately equal to the High level output of Q0. This pulse can
be used to enable the next cascaded stage (see Figure 2). The TC
output is subjected to decoding spikes due to internal race
conditions. Therefore, it is not recommended for use as clock or
asynchronous reset for flip-flops, registers, or counters.
FEATURES
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive edge-triggered clock
• Asynchronous Master Reset (74F161A)
• Synchronous Reset (74F163A)
• High speed synchronous expansion
• Typical count rate of 130MHz
• Industrial range (–40°C to +85°C) available
DESCRIPTION
4-bit binary counters feature an internal carry look-ahead and can be
used for high-speed counting. Synchronous operation is provided by
having all flip-flops clocked simultaneously on the positive-going
edge of the clock. The clock input is buffered.
The outputs of the counters may be preset to High or Low level. A
Low level at the Parallel Enable (PE) input disables the counting
action and causes the data at the D0–D3 inputs to be loaded into
the counter on the positive-going edge of the clock (provided that
the setup and hold requirements for PE are met). Preset takes place
regardless of the levels at Count Enable (CEP, CET) inputs.
TYPE
TYPICAL
fMAX
TYPICAL SUPPLY CURRENT
(TOTAL)
74F161A
74F163A
130MHz
46mA
ORDERING INFORMATION
ORDER CODE
DRAWING
NUMBER
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
INDUSTRIAL RANGE
VCC = 5V ±10%, Tamb = –40°C to +85°C
16-pin plastic DIP
N74F161AN, N74F163AN
I74F161AN, I74F163AN
SOT38-4
16-pin plastic SO
N74F161AD, N74F163AD
I74F161AD, I74F163AD
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0 – D3
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
Data inputs
1.0/1.0
20µA/0.6mA
CEP
Count Enable Parallel input
1.0/1.0
20µA/0.6mA
CET
Count Enable Trickle input
1.0/2.0
20µA/1.2mA
CP
Clock input (active rising edge)
1.0/1.0
20µA/0.6mA
PE
Parallel Enable input (active Low)
1.0/2.0
20µA/1.2mA
MR
Asynchronous Master Reset input
(active Low) for 74F161A
1.0/1.0
20µA/0.6mA
SR
Synchronous Reset input
(active Low) for 74F163A
1.0/1.0
20µA/0.6mA
TC
Terminal count output
50/33
1.0mA/20mA
Flip-flop outputs
50/33
1.0mA/20mA
Q0 – Q3
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1996 Jan 29
2
853–0347 16300
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
74F161A PIN CONFIGURATION
74F163A PIN CONFIGURATION
SR
1
16
VCC
TC
CP
2
15
TC
3
14
Q0
MR
1
16
VCC
CP
2
15
D0
3
14
Q0
D0
D1
4
13
Q1
D1
4
13
Q1
D2
5
12
Q2
D2
5
12
Q2
D3
6
11
Q3
D3
6
11
Q3
7
10
CET
8
9
PE
CEP
7
10
CET
CEP
GND
8
9
PE
GND
SF00656
SF00657
74F161A LOGIC SYMBOL
9
PE
7
CEP
10
CET
2
CP
1
MR
74F163A LOGIC SYMBOL
3
4
5
D0
D1
D2
6
D3
TC
Q0
Q1
Q2
Q3
14
13
12
11
VCC = Pin 16
GND = Pin 8
15
9
PE
7
CEP
10
CET
2
CP
1
SR
3
4
5
D0
D1
D2
6
D3
TC
Q0
Q1
Q2
Q3
14
13
12
11
VCC = Pin 16
GND = Pin 8
15
SF00658
SF00659
74F161A LOGIC SYMBOL (IEEE/IEC)
1
9
7
10
2
3
74F163A LOGIC SYMBOL (IEEE/IEC)
CTR DIV 16
R
1
9
M1
7
G3
10
G4
2
C2 /1,3,4+
CTR DIV 16
M1
G3
G4
C2 /1,3,4+
14
3
4
13
4
13
5
12
5
12
6
11
6
11
1,2 D
4 CT=15
15
14
1,2 D
4 CT=15
SF00660
1996 Jan 29
2R
15
SF00661
3
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
STATE DIAGRAM
APPLICATIONS
+VCC
0
1
2
3
4
D0 D1
PE
15
5
CEP
CET
14
74F163A
TC
CP
CLOCK
6
SR
13
D2 D3
Q0 Q1 Q2 Q3
7
12
11
10
9
SF00665
8
Figure 1. Maximum count modifying scheme
Terminal count = 6
SF00664
H H = Enable count
or
L L = Disable count
PE
CEP
D0 D1 D2 D3
CET
74F163A
PE
CEP
TC
CET
D0 D1 D2 D3
74F163A
PE
CEP
TC
CET
D0 D1 D2 D3
74F163A
PE
CEP
TC
CET
D0 D1 D2 D3
74F163A
TC
PE
CEP
CET
D0 D1 D2 D3
74F163A
TC
CP
CP
CP
CP
CP
SR Q0 Q1 Q2 Q3
SR Q0 Q1 Q2 Q3
SR Q0 Q1 Q2 Q3
SR Q0 Q1 Q2 Q3
SR Q0 Q1 Q2 Q3
CP
SF00666
Figure 2. Synchronous multistage counting scheme
74F161A MODE SELECT – FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
MR
CP
CEP
CET
PE
Dn
Qn
TC
L
X
X
X
X
X
L
L
Reset (clear)
H
H
↑
↑
X
X
X
X
l
l
l
h
L
H
L
(1)
Parallel load
H
↑
h
h
h
X
count
(1)
Count
H
H
X
X
l
X
X
l
h
h
X
X
qn
qn
(1)
L
Hold (do nothing)
1996 Jan 29
4
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
74F163A MODE SELECT – FUNCTION TABLE
INPUTS
H
h
L
l
qn
X
↑
(1)
(2)
OUTPUTS
SR
CP
CEP
CET
PE
Dn
Qn
TC
l
↑
X
X
X
X
L
L
h
↑
X
X
l
l
L
L
h
↑
X
X
l
h
H
(2)
h
↑
h
h
h
X
count
(2)
h
X
l
X
h
X
qn
(2)
h
X
X
l
h
X
qn
L
=
=
=
=
=
=
=
=
=
OPERATING MODE
Reset (clear)
Parallel load
Count
Hold (do nothing)
High voltage level
High voltage level one setup prior to the Low-to-High clock transition
Low voltage level
Low voltage level one setup prior to the Low-to-High clock transition
Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
Don’t care
Low-to-High clock transition
The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F161A)
The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F163A)
74F161A LOGIC DIAGRAM
CP
MR
PE
CET
CEP
D0
2
1
9
10
7
3
D R Q
CP
D1
Q
14
Q0
4
D R Q
CP
D2
Q
13
Q1
5
D R Q
CP
D3
Q
12
Q2
6
D R Q
CP
Q
11
15
VCC = Pin 16
GND = Pin 8
1996 Jan 29
Q3
TC
SF00662
5
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
74F163A LOGIC DIAGRAM
CP
SR
PE
CET
CEP
D0
D1
D2
D3
2
1
9
10
7
3
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
D
Q
CP
Q
14
Q0
4
13
Q1
5
12
Q2
6
11
15
VCC = Pin 16
GND = Pin 8
Q3
TC
SF00663
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
VCC
Supply voltage
–0.5 to +7.0
VIN
Input voltage
–0.5 to +7.0
V
IIN
Input current
–30 to +5
mA
VOUT
Voltage applied to output in High output state
–0.5 to VCC
V
IOUT
Current applied to output in Low output state
40
mA
Commercial range
0 to +70
Tamb
Operating free-air
free air temperature range
°C
Industrial range
–40 to +85
°C
Tstg
Storage temperature range
–65 to +150
°C
1996 Jan 29
6
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN
NOM
MAX
5.0
5.5
UNIT
VCC
Supply voltage
4.5
VIH
High-level input voltage
2.0
V
VIL
Low-level input voltage
0.8
V
IIK
Input clamp current
–18
mA
IOH
High-level output current
–1
mA
IOL
Low-level output current
20
mA
Tamb
Operating free-air
free air temperature range
V
Commercial range
0
+70
°C
Industrial range
–40
+85
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
VCC = MIN,, VIL = MAX,,
VIH = MIN
IOH
O = MAX
Low level output voltage
Low-level
VCC = MIN,, VIL = MAX,,
VIH = MIN
IOL
O = MAX
VIK
Input clamp voltage
VCC = MIN, II = IIK
II
Input current at maximum input voltage
VCC = MAX, VI = 7.0V
IIH
High-level input current
VCC = MAX, VI = 2.7V
VOH
O
High level output voltage
High-level
VOL
O
LIMITS
TEST CONDITIONS1
PARAMETER
MIN
±10%VCC
2.5
±5%VCC
2.7
±10%VCC
±5%VCC
TYP2
Low level input current
Low-level
IOS
Short-circuit output current3
ICC
Supply current (total)
others
3.4
ICCH
ICCL
0.50
V
0.30
0.50
V
–0.73
–1.2
V
100
µA
20
µA
–1.2
mA
–0.6
mA
–150
mA
42
55
mA
49
65
mA
-60
VCC = MAX
V
0.30
VCC = MAX,
MAX VI = 0
0.5V
5V
VCC = MAX
UNIT
V
CET, PE
IIL
MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
1996 Jan 29
7
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF
RL = 500Ω
MIN
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF
RL = 500Ω
MIN
MAX
90
Tamb = –40°C to +85°C
VCC = +5.0V ± 10%
CL = 50pF
RL = 500Ω
MIN
UNIT
MAX
fmax
Maximum clock frequency
Waveform 1
100
130
75
MHz
tPLH
tPHL
Propagation delay
CP to Qn (PE = High)
Waveform 1
2.0
4.0
4.0
6.5
6.5
10.0
2.0
4.0
7.0
11.0
2.0
4.0
7.0
11.0
ns
tPLH
tPHL
Propagation delay
CP to Qn (PE = Low)
Waveform 1
2.0
3.5
4.5
5.5
6.5
8.5
2.0
3.5
7.5
9.5
2.0
3.5
7.5
9.5
ns
tPLH
tPHL
Propagation delay
CP to TC
Waveform 1
5.0
4.5
7.5
7.5
10.5
10.5
5.0
4.0
11.5
11.5
5.0
4.0
11.5
11.5
ns
tPLH
tPHL
Propagation delay
CET to TC
Waveform 2
1.5
2.5
3.5
5.0
6.5
7.5
1.5
2.5
7.0
8.0
1.5
2.5
7.0
8.0
ns
tPHL
Propagation delay
MR to Qn
’F161A
Waveform 3
6.0
8.5
12.0
5.5
13.0
5.5
13.0
ns
tPHL
Propagation delay
MR to TC
’F161A
Waveform 3
5.0
8.5
10.0
5.0
11.0
5.0
11.0
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF
RL = 500Ω
MIN
TYP
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF
RL = 500Ω
Tamb = –40°C to +85°C
VCC = +5.0V ± 10%
CL = 50pF
RL = 500Ω
MIN
MIN
UNIT
ts(H)
ts(L)
Setup time, High or Low
Dn to CP
Waveform 6
5.0
5.0
5.0
5.0
5.0
5.0
ns
th(H)
th(L)
Hold time, High or Low
Dn to CP
Waveform 6
0
0
0
0
0
0
ns
ts(H)
ts(L)
Setup time, High or Low
PE or SR to CP
Waveform
5 or 6
9.0
6.5
9.5
7.0
9.5
7.0
ns
th(H)
th(L)
Hold time, High or Low
PE or SR to CP
Waveform
5 or 6
0
0
0
0
0
0
ns
ts(H)
ts(L)
Setup time, High or Low
CET or CEP to CP
Waveform 4
10.5
6.0
10.5
7.0
10.5
7.0
ns
th(H)
th(L)
Hold time, High or Low
CET or CEP to CP
Waveform 4
0
0
0
0
0
0
ns
tw(H)
tw(L)
CP pulse width (Load)
High or Low
Waveform 1
4.0
5.0
4.0
5.5
4.0
7.0
ns
tw(H)
tw(L)
CP pulse width (Count)
High or Low
Waveform 1
4.0
6.0
4.0
7.0
4.0
7.0
ns
tw(L)
MR pulse width
Low
’F161A
Waveform 3
4.5
4.5
4.5
ns
tREC
Recovery time
MR to CP
’F161A
Waveform 3
6.0
6.5
6.5
ns
1996 Jan 29
8
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX
CP
VM
VM
tw(H)
VM
tw(L)
CET
tPHL
VM
VM
tPLH
tPHL
tPLH
VM
Qn, TC
VM
VM
TC
VM
SF00667
SF00668
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
Waveform 2. Propagation Delay, CET Input to TC Output
tw(L)
MR
VM
VM
CEP
tREC
CET
VM
VM
ts(H)
VM
CP
VM
tPHL
th(H)
VM
ts(L)
th(L)
VM
CP
VM
VM
Qn, TC
SF00669
SF00670
Waveform 3. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Recovery Time
Waveform 4. CEP and CET Reset Setup and Hold Times
Dn
SR
VM
VM
VM
ts(L)
CP
th(L)
VM
VM
ts(H)
th(H)
PE
VM
ts
th
VM
VM
ts(L)
VM
CP
SF00671
th(L)
VM
VM
VM
ts(H)
th(H)
VM
SF00672
Waveform 5. Synchronous Reset Setup and Hold Times
1996 Jan 29
VM
Waveform 6. Parallel Data and Parallel Enable
Setup and Hold Times
9
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
TEST CIRCUIT AND WAVEFORMS
VCC
VIN
tw
90%
NEGATIVE
PULSE
VM
D.U.T.
RT
CL
RL
AMP (V)
VM
10%
VOUT
PULSE
GENERATOR
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
AMP (V)
90%
90%
POSITIVE
PULSE
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
RL = Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
VM
VM
10%
10%
tw
0V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude VM
74F
3.0V
1.5V
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
SF00006
1996 Jan 29
10
Philips Semiconductors
Product specification
74F160A*, 74F161A,
74F162A*, 74F163A
4-bit binary counters
DIP16: plastic dual in-line package; 16 leads (300 mil)
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
1996 Jan 29
11
SOT38-4
Philips Semiconductors
Product specification
74F160A*, 74F161A,
74F162A*, 74F163A
4-bit binary counters
SO16: plastic small outline package; 16 leads; body width 3.9 mm
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
1996 Jan 29
12
SOT109-1
Philips Semiconductors
Product specification
74F160A*, 74F161A,
74F162A*, 74F163A
4-bit binary counters
NOTES
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
1996 Jan 29
13
Philips Semiconductors
Product specification
74F160A*, 74F161A,
74F162A*, 74F163A
4-bit binary counter
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
yyyy mmm dd
14
Date of release: 10-98
9397-750-05084