PHILIPS 74F173

INTEGRATED CIRCUITS
74F173
Quad D-type flip-flop (3-State)
Product specification
IC15 Data Handbook
1990 Aug 31
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
74F173
Data inputs and clock enable inputs are fully edge–triggered
and must be stable only one setup time before the
low–to–high clock transition.
FEATURES
• Edge–triggered D–type register
• Gated clock enable for hold ”do nothing” mode
• 3–state output buffers
• Gated output enable control
• Speed upgrade of N8T10 and current sink upgrade
• Controlled output edges to minimize ground bounces
• 48mA sinking capability
The master reset (MR) is an active–high asynchronous
input. When the MR is high, all four flip–flops are reset
(cleared) independently of any other input condition.
The 3–state output buffers are controlled by a 2–input NOR
gate. When both output enable (OE0 and OE1) inputs are
low, the data in the register is presented at the Q output.
When one or both OE inputs are high, the outputs are forced
to a high impedance ”off” state.
DESCRIPTION
The 3–state output buffers are completely independent of
the register operation; the OE transition does not affect the
clock and reset operations.
The 74F173 is a high speed 4–bit parallel load register with
clock enable control, 3–state buffered outputs, and master
reset (MR). When the two clock enable (E0 and E1) inputs
are low, the data on the D inputs is loaded into the register
simultaneously with low–to–high clock (CP) transition. When
one or both enable inputs are high one setup time before the
low–to–high clock transition, the register retains the previous
data.
TYPE
TYPICAL fmax
TYPICAL SUPPLY CURRENT (TOTAL)
125MHz
23mA
74F173
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
PKG DWG #
16–pin plastic DIP
N74F173N
SOT38-4
16–pin plastic SO
N74F173D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
LOAD VALUE
HIGH/LOW
D0 – D3
Data inputs
1.0/1.0
20µA/0.6mA
CP
Clock input
1.0/1.0
20µA/0.6mA
Clock enable inputs
1.0/1.0
20µA/0.6mA
Master reset input
1.0/1.0
20µA/0.6mA
Output enable inputs
1.0/1.0
20µA/0.6mA
Data outputs
750/80
15mA/48mA
E0, E1
MR
OE0, OE1
Q0 – Q3
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
August 31, 1990
2
853–1160 00286
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
74F173
PIN CONFIGURATION
IEC/IEEE SYMBOL
9
OE0 1
16 V
CC
OE1 2
15 MR
7
Q0 3
14 D0
1
Q1 4
13 D3
12 D2
Q3 6
11 Q2
CP 7
10 E1
GND
8
C1
&
2
15
Q2 5
&
10
14
9 E0
EN
R
3
1D
13
4
12
5
11
6
SF00290
SF00292
LOGIC SYMBOL
14 13 12 11
9
10
E0
E1
7
15
1
CP
MR
OE0
2
OE1
VCC = Pin 16
GND = Pin 8
D0 D1 D2 D3
Q0 Q1 Q2 Q3
3
4
5
6
SF00291
FUNCTION TABLE
INPUTS
OUTPUTS
OUTPUTS
MR
CP
E0
E1
Dn
Qn (register)
H
X
X
X
X
L
Reset (clear)
L
↑
l
l
l
L
Parallel load
L
↑
l
l
h
H
L
X
h
X
X
qn
Hold (do nothing)
L
X
X
h
X
qn
Notes to function table
H = High–voltage level
h = High state one setup time before the low–to–high clock transition
L = Low–voltage level
l = Low state one setup time before the low–to–high clock transition
qn = Lower case letters indicate the state of the referenced input (or output) on setup time prior to the low–to–high clock transition
X = Don’t care
↑ = Low–to–high clock transition
August 31, 1990
3
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
74F173
FUNCTION TABLE
INPUTS
OUTPUTS
Qn (register)
OE0
OE1
Qn
L
L
L
L
H
L
L
H
X
H
X
Z
H
Z
X
X
Notes to function table
H = High–voltage level
L = Low–voltage level
X = Don’t care
Z = High impedance ”off” state
OUTPUTS
Read
Disabled
LOGIC DIAGRAM
D1
D0
E0
E1
9
D3
D2
13
14
11
12
10
7
CP
D
D
Q
D
CP
CP
RD
Q
Q
RD
D
Q
CP
CP
Q
RD
Q
Q
RD
Q
15
MR
OE0
OE1
1
2
4
3
Q1
Q0
VCC = Pin 16
GND = Pin 8
6
5
Q2
Q3
SF00293
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
VCC
Supply voltage
–0.5 to +7.0
VIN
Input voltage
–0.5 to +7.0
V
IIN
Input current
–30 to +5
mA
VOUT
Voltage applied to output in high output state
–0.5 to VCC
V
IOUT
Current applied to output in low output state
96
mA
Tamb
Operating free air temperature range
0 to +70
°C
Tstg
Storage temperature range
–65 to +150
°C
August 31, 1990
4
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
74F173
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
NOM
MAX
5.0
5.5
VCC
Supply voltage
4.5
VIH
High–level input voltage
2.0
V
VIL
Low–level input voltage
0.8
V
IIk
Input clamp current
–18
mA
IOH
High–level output current
–15
mA
IOL
Low–level output current
48
mA
Tamb
Operating free air temperature range
+70
°C
V
0
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
PARAMETER
SYMBOL
TEST
LIMITS
CONDITIONS1
VOH
High-level output voltage
MIN
VCC = MIN, VIL = MAX,
±10%VCC
2.4
VIH = MIN, IOH = MAX
±5%VCC
2.7
VCC = MIN, VIL = MAX,
±10%VCC
2.0
VIH = MIN, IOH = –15mA
±5%VCC
2.0
VCC = MIN, VIL = MAX,
±10%VCC
VIH = MIN, IOL = MAX
±5%VCC
VOL
Low-level output voltage
VIK
Input clamp voltage
VCC = MIN, II = IIK
II
Input current at maximum input voltage
IIH
High–level input current
IIL
TYP2
UNIT
MAX
V
3.4
V
V
3.1
V
0.35
0.50
V
0.35
0.50
V
–0.73
-1.2
V
VCC = MAX, VI = 7.0V
100
µA
VCC = MAX, VI = 2.7V
20
µA
Low–level input current
VCC = MAX, VI = 0.5V
–0.6
mA
IOZH
Off–state output current, high–level voltage applied
VCC = MAX, VO = 2.7V
50
µA
IOZL
Off–state output current, low–level voltage applied
VCC = MAX, VO = 0.5V
–50
µA
IOS
Short–circuit output current3
VCC = MAX
-150
mA
19
26
mA
27
37
mA
23
32
ICCH
ICC
Supply current (total)
ICCL
VCC = MAX
ICCZ
-60
mA
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
August 31, 1990
5
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
74F173
AC ELECTRICAL CHARACTERISTICS
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
TYP
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MAX
MIN
UNIT
MAX
fmax
Maximum clock frequency
Waveform 1
100
125
90
MHz
tPLH
tPHL
Propagation delay
CP to Qn
Waveform 1
4.5
6.0
6.5
8.0
9.0
10.5
4.0
5.5
10.0
11.5
ns
tPHL
Propagation delay
MR to Qn
Waveform 2
6.5
8.5
11.5
6.0
12.5
ns
tPZH
tPZL
Output enable time
to high or low level
Waveform 4
Waveform 5
3.5
5.5
5.0
7.0
8.0
10.0
2.5
4.5
8.5
11.0
ns
tPHZ
tPLZ
Output disable time
from high or low level
Waveform 4
Waveform 5
1.5
3.0
3.5
5.0
7.0
8.5
1.0
2.5
8.0
9.0
ns
tTHL
tTLH
Transition time
10% to 90%, 90% to 10%
Waveform 5
Waveform 4
2.0
4.0
5.0
7.5
8.0
10.0
2.0
4.0
8.5
11.0
ns
AC SETUP REQUIREMENTS
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
tsu (H)
tsu (L)
Setup time, high or low level
Dn to CP
th (H)
th (L)
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL= 50pF, RL = 500Ω
MIN
UNIT
MAX
Waveform 3
2.5
2.5
3.0
4.0
ns
Hold time, high or low level
Dn to CP
Waveform 3
0
0
0
0
ns
tsu (H)
tsu (L)
Setup time, high or low level
E to CP
Waveform 3
4.5
7.5
5.0
8.5
ns
th (H)
th (L)
Hold time, high or low level
E to CP
Waveform 3
0
0
0
0
ns
tw (H)
tw (L)
CP Pulse width,
high or low
Waveform 1
3.0
6.0
3.0
6.0
ns
tw (H)
MR Pulse width, high
Waveform 2
3.5
3.5
ns
trec
Recovery time, MR to CP
Waveform 2
4.5
5.5
ns
AC WAVEFORMS
1/fmax
CP
VM
VM
VM
tw(H)
tPHL
Qn
tw(L)
VM
tPLH
VM
SF00294
Waveform 1. Propagation delay for clock input to output, clock
pulse widths, and maximum clock frequency
August 31, 1990
6
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
MR
VM
74F173
OE
VM
trec
tw(H)
CP
VM
VM
tPZH
tPHZ
90%
VM
Qn
VM
VOH -0.3V
10%
0V
tPHL
SF00297
VM
VM
Qn
Waveform 4. 3-state output enable time to high level, output
disable time from high level and transition time to high level
SF00295
OE
Waveform 2. Master reset pulse width, master reset to output
delay and master reset to clock recovery time
VM
VM
tPZL
tPLZ
90%
En, Dn
VM
tsu(H)
VM
VM
tsu(L)
th(H)
Qn
VM
3.5V
VM
10%
VOL +0.3V
th(L)
SF00298
CP
VM
VM
Waveform 5. 3-state output enable time to low level, output
disable time from low level and transition time to low level
SF00296
Waveform 3. Data and enable setup time and hold times
Notes to AC waveforms
1. For all waveforms, VM = 1.5V.
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORMS
VCC
7.0V
VIN
RL
VOUT
PULSE
GENERATOR
tw
90%
NEGATIVE
PULSE
VM
CL
AMP (V)
VM
10%
D.U.T.
RT
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
RL
AMP (V)
90%
90%
Test Circuit for Open Collector Outputs
POSITIVE
PULSE
VM
VM
10%
TEST
tPLZ
tPZL
All other
SWITCH
closed
closed
open
DEFINITIONS:
RL = Load resistor;
see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
10%
tw
SWITCH POSITION
0V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude VM
74F
3.0V
1.5V
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
SF00128
August 31, 1990
7
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
DIP16: plastic dual in-line package; 16 leads (300 mil)
1990 Aug 31
8
SOT38-4
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
SO16: plastic small outline package; 16 leads; body width 3.9 mm
1990 Aug 31
9
SOT109-1
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
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Date of release: 10-98
9397-750-05088